118 lines
5.6 KiB
Python
118 lines
5.6 KiB
Python
# -*- Mode:Python; explicit-buffer-name: "devices.conf<common>" -*-
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import helpers
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analogDir = helpers.sysConfDir + '/share/coriolis2/analog'
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spiceDir = analogDir + 'spice/'
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devicesTable = \
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( { 'name' : 'DifferentialPairBulkConnected'
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, 'spice' : spiceDir+'DiffPairBulkConnected.spi'
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, 'connectors' : ( 'D1', 'D2', 'G1', 'G2', 'S' )
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, 'layouts' : ( ('Horizontal M2' , 'DP_horizontalM2.py' )
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, ('Symmetrical' , 'DP_symmetrical.py' )
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, ('Common centroid', 'DP_2DCommonCentroid.py')
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, ('Interdigitated' , 'DP_interdigitated.py' )
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, ('WIP DP' , 'WIP_DP.py' )
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)
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}
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, { 'name' : 'DifferentialPairBulkUnconnected'
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, 'spice' : spiceDir+'DiffPairBulkUnconnected.spi'
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, 'connectors' : ( 'D1', 'D2', 'G1', 'G2', 'S', 'B' )
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, 'layouts' : ( ('Horizontal M2' , 'DP_horizontalM2.py' )
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, ('Symmetrical' , 'DP_symmetrical.py' )
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, ('Common centroid', 'DP_2DCommonCentroid.py')
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, ('Interdigitated' , 'DP_interdigitated.py' )
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, ('WIP DP' , 'WIP_DP.py' )
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)
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}
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, { 'name' : 'LevelShifterBulkUnconnected'
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, 'spice' : spiceDir+'LevelShifterBulkUnconnected.spi'
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, 'connectors' : ( 'D1', 'D2', 'S1', 'S2', 'B' )
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, 'layouts' : ( ('Horizontal M2' , 'LS_horizontalM2.py' )
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, ('Symmetrical' , 'LS_symmetrical.py' )
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, ('Common centroid', 'LS_2DCommonCentroid.py')
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, ('Interdigitated' , 'LS_interdigitated.py' )
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)
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}
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, { 'name' : 'TransistorBulkConnected'
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, 'spice' : spiceDir+'TransistorBulkConnected.spi'
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, 'connectors' : ( 'D', 'G', 'S' )
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, 'layouts' : ( ('Rotate transistor', 'Transistor_rotate.py' )
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, ('Common transistor', 'Transistor_common.py' )
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, ('WIP Transistor' , 'WIP_Transistor.py' )
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)
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}
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, { 'name' : 'TransistorBulkUnconnected'
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, 'spice' : spiceDir+'TransistorBulkUnconnected.spi'
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, 'connectors' : ( 'D', 'G', 'S', 'B' )
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, 'layouts' : ( ('Rotate transistor', 'Transistor_rotate.py' )
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, ('Common transistor', 'Transistor_common.py' )
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, ('WIP Transistor' , 'WIP_Transistor.py' )
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)
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}
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, { 'name' : 'CrossCoupledPairBulkConnected'
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, 'spice' : spiceDir+'CCPairBulkConnected.spi'
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, 'connectors' : ( 'D1', 'D2', 'S' )
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, 'layouts' : ( ('Horizontal M2' , 'CCP_horizontalM2.py' )
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, ('Symmetrical' , 'CCP_symmetrical.py' )
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, ('Common centroid', 'CCP_2DCommonCentroid.py')
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, ('Interdigitated' , 'CCP_interdigitated.py' )
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)
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}
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, { 'name' : 'CrossCoupledPairBulkUnconnected'
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, 'spice' : spiceDir+'CCPairBulkUnconnected.spi'
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, 'connectors' : ( 'D1', 'D2', 'S', 'B' )
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, 'layouts' : ( ('Horizontal M2' , 'CCP_horizontalM2.py' )
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, ('Symmetrical' , 'CCP_symmetrical.py' )
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, ('Common centroid', 'CCP_2DCommonCentroid.py')
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, ('Interdigitated' , 'CCP_interdigitated.py' )
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)
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}
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, { 'name' : 'CommonSourcePairBulkConnected'
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, 'spice' : spiceDir+'CommonSourcePairBulkConnected.spi'
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, 'connectors' : ( 'D1', 'D2', 'S', 'G' )
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, 'layouts' : ( ('Horizontal M2' , 'CSP_horizontalM2.py' )
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, ('Symmetrical' , 'CSP_symmetrical.py' )
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, ('Interdigitated' , 'CSP_interdigitated.py' )
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, ('WIP CSP' , 'WIP_CSP.py' )
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)
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}
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, { 'name' : 'CommonSourcePairBulkUnconnected'
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, 'spice' : spiceDir+'CommonSourcePairBulkUnconnected.spi'
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, 'connectors' : ( 'D1', 'D2', 'S', 'G', 'B' )
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, 'layouts' : ( ('Horizontal M2' , 'CSP_horizontalM2.py' )
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, ('Symmetrical' , 'CSP_symmetrical.py' )
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, ('Interdigitated' , 'CSP_interdigitated.py' )
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, ('WIP CSP' , 'WIP_CSP.py' )
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)
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}
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, { 'name' : 'SimpleCurrentMirrorBulkConnected'
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, 'spice' : spiceDir+'CurrMirBulkConnected.spi'
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, 'connectors' : ( 'D1', 'D2', 'S' )
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, 'layouts' : ( ('Horizontal M2' , 'SCM_horizontalM2.py' )
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, ('Symmetrical' , 'SCM_symmetrical.py' )
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, ('Common centroid', 'SCM_2DCommonCentroid.py')
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, ('Interdigitated' , 'SCM_interdigitated.py' )
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)
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}
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, { 'name' : 'SimpleCurrentMirrorBulkUnconnected'
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, 'spice' : spiceDir+'CurrMirBulkUnconnected.spi'
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, 'connectors' : ( 'D1', 'D2', 'S', 'B' )
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, 'layouts' : ( ('Horizontal M2' , 'SCM_horizontalM2.py' )
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, ('Symmetrical' , 'SCM_symmetrical.py' )
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, ('Common centroid', 'SCM_2DCommonCentroid.py')
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, ('Interdigitated' , 'SCM_interdigitated.py' )
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)
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}
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, { 'name' : 'MIMCapacitor'
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, 'spice' : spiceDir+'MIMCapacitor.spi'
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, 'connectors' : ( 'P1', 'P2' )
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, 'layouts' : ( ('SimpleMatrix' , 'MIM_simpleMatrix.py' )
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,
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)
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}
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)
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