--
-- Generated by VASY
--
ENTITY coeur IS
PORT(
  a_from_pads	: IN BIT_VECTOR(3 DOWNTO 0);
  b_from_pads	: IN BIT_VECTOR(3 DOWNTO 0);
  cin_from_pads	: IN BIT;
  ck	: IN BIT;
  cout_to_pads	: OUT BIT;
  d_from_pads	: IN BIT_VECTOR(3 DOWNTO 0);
  i_from_pads	: IN BIT_VECTOR(8 DOWNTO 0);
  ng_to_pads	: OUT BIT;
  noe_from_pads	: IN BIT;
  np_to_pads	: OUT BIT;
  ovr_to_pads	: OUT BIT;
  q0_from_pads	: IN BIT;
  q0_to_pads	: OUT BIT;
  q3_from_pads	: IN BIT;
  q3_to_pads	: OUT BIT;
  r0_from_pads	: IN BIT;
  r0_to_pads	: OUT BIT;
  r3_from_pads	: IN BIT;
  r3_to_pads	: OUT BIT;
  shift_l	: OUT BIT;
  shift_r	: OUT BIT;
  f3_to_pads	: OUT BIT;
  vdd	: IN BIT;
  vss	: IN BIT;
  y_oe	: OUT BIT;
  y_to_pads	: OUT BIT_VECTOR(3 DOWNTO 0);
  zero_to_pads	: OUT BIT
);
END coeur;

ARCHITECTURE VST OF coeur IS

  SIGNAL alu_out	: BIT_VECTOR(3 DOWNTO 0);
  SIGNAL r	: BIT_VECTOR(3 DOWNTO 0);
  SIGNAL ra	: BIT_VECTOR(3 DOWNTO 0);
  SIGNAL rb	: BIT_VECTOR(3 DOWNTO 0);
  SIGNAL s	: BIT_VECTOR(3 DOWNTO 0);
  SIGNAL saccu	: BIT_VECTOR(3 DOWNTO 0);

  COMPONENT muxs
  PORT(
  alu_out	: IN BIT_VECTOR(3 DOWNTO 0);
  i	: IN BIT_VECTOR(2 DOWNTO 0);
  noe	: IN BIT;
  oe	: OUT BIT;
  ra	: IN BIT_VECTOR(3 DOWNTO 0);
  shift_l	: OUT BIT;
  shift_r	: OUT BIT;
  vdd	: IN BIT;
  vss	: IN BIT;
  y	: OUT BIT_VECTOR(3 DOWNTO 0)
  );
  END COMPONENT;

  COMPONENT alu
  PORT(
  alu_out	: INOUT BIT_VECTOR(3 DOWNTO 0);
  cin	: IN BIT;
  cout	: OUT BIT;
  i	: IN BIT_VECTOR(2 DOWNTO 0);
  ng	: OUT BIT;
  np	: OUT BIT;
  ovr	: OUT BIT;
  r	: IN BIT_VECTOR(3 DOWNTO 0);
  s	: IN BIT_VECTOR(3 DOWNTO 0);
  f3	: OUT BIT;
  vdd	: IN BIT;
  vss	: IN BIT;
  zero	: OUT BIT
  );
  END COMPONENT;

  COMPONENT accu
  PORT(
  accu	: INOUT BIT_VECTOR(3 DOWNTO 0);
  alu_out	: IN BIT_VECTOR(3 DOWNTO 0);
  cke	: IN BIT;
  i	: IN BIT_VECTOR(2 DOWNTO 0);
  q0_from	: IN BIT;
  q0_to	: OUT BIT;
  q3_from	: IN BIT;
  q3_to	: OUT BIT;
  vdd	: IN BIT;
  vss	: IN BIT
  );
  END COMPONENT;

  COMPONENT ram
  PORT(
  a	: IN BIT_VECTOR(3 DOWNTO 0);
  alu_out	: IN BIT_VECTOR(3 DOWNTO 0);
  b	: IN BIT_VECTOR(3 DOWNTO 0);
  clk	: IN BIT;
  i	: IN BIT_VECTOR(2 DOWNTO 0);
  r0_from_pads	: IN BIT;
  r0_to_pads	: OUT BIT;
  r3_from_pads	: IN BIT;
  r3_to_pads	: OUT BIT;
  ra	: OUT BIT_VECTOR(3 DOWNTO 0);
  rb	: OUT BIT_VECTOR(3 DOWNTO 0);
  vdd	: IN BIT;
  vss	: IN BIT
  );
  END COMPONENT;

  COMPONENT muxe
  PORT(
  accu	: IN BIT_VECTOR(3 DOWNTO 0);
  d	: IN BIT_VECTOR(3 DOWNTO 0);
  i	: IN BIT_VECTOR(2 DOWNTO 0);
  r	: OUT BIT_VECTOR(3 DOWNTO 0);
  ra	: IN BIT_VECTOR(3 DOWNTO 0);
  rb	: IN BIT_VECTOR(3 DOWNTO 0);
  s	: OUT BIT_VECTOR(3 DOWNTO 0);
  vdd	: IN BIT;
  vss	: IN BIT
  );
  END COMPONENT;

BEGIN

  iram : ram
  PORT MAP (
    a(3 downto 0) => a_from_pads,
    alu_out => alu_out,
    b(3 downto 0) => b_from_pads,
    i(2 downto 0) => i_from_pads(8 downto 6),
    ra => ra,
    rb => rb,
    vss => vss,
    vdd => vdd,
    r3_to_pads => r3_to_pads,
    r3_from_pads => r3_from_pads,
    r0_to_pads => r0_to_pads,
    r0_from_pads => r0_from_pads,
    clk => ck
  );
  iaccu : accu
  PORT MAP (
    accu(3 downto 0) => saccu,
    alu_out => alu_out,
    i(2 downto 0) => i_from_pads(8 downto 6),
    vss => vss,
    vdd => vdd,
    q3_to => q3_to_pads,
    q3_from => q3_from_pads,
    q0_to => q0_to_pads,
    q0_from => q0_from_pads,
    cke => ck
  );
  ialu : alu
  PORT MAP (
    alu_out => alu_out,
    i(2 downto 0) => i_from_pads(5 downto 3),
    r => r,
    s => s,
    zero => zero_to_pads,
    vss => vss,
    vdd => vdd,
    f3 => f3_to_pads,
    ovr => ovr_to_pads,
    np => np_to_pads,
    ng => ng_to_pads,
    cout => cout_to_pads,
    cin => cin_from_pads
  );
  imuxs : muxs
  PORT MAP (
    alu_out => alu_out,
    i(2 downto 0) => i_from_pads(8 downto 6),
    ra => ra,
    y(3 downto 0) => y_to_pads,
    vss => vss,
    vdd => vdd,
    shift_r => shift_r,
    shift_l => shift_l,
    oe => y_oe,
    noe => noe_from_pads
  );
  imuxe : muxe
  PORT MAP (
    accu(3 downto 0) => saccu,
    d(3 downto 0) => d_from_pads,
    i(2 downto 0) => i_from_pads(2 downto 0),
    r => r,
    ra => ra,
    rb => rb,
    s => s,
    vss => vss,
    vdd => vdd
  );
END VST;