Presentation | AGDS | CIF | DTR | OPENCHAMS | SPICE | Links & Contact |
| DSlicingNode (OpenChams) | IntermediatePoint (OpenChams) | Operator (OpenChams) | SpiceException (SPICE) | |
DTRException (DTR) |
|
| Structure (AGDS) | ||
ARule (DTR) |
| Subckt (SPICE) | |||
| Layout (OpenChams) | Parameters (OpenChams) |
| ||
Element (AGDS) | Library (AGDS) | Polygon (CIF) | |||
Bloc (OpenChams) | Equation (OpenChams) |
| Port (OpenChams) | Techno (DTR) | |
|
| PortPoint (OpenChams) | Transistor (OpenChams) | ||
map_item (SPICE) |
|
| |||
Capacitor (SPICE) | Group (OpenChams) | map_item (OpenChams) | |||
Circuit (SPICE) |
| Mosfet (SPICE) | Rectangle (AGDS) | Value (SPICE) | |
Circuit (OpenChams) |
| Resistor (SPICE) | Voltage (SPICE) | ||
Circuit (CIF) | HighLevelCstr (OpenChams) | RSlicingNode (OpenChams) | VSlicingNode (OpenChams) | ||
Net::Connection (OpenChams) | HSlicingNode (OpenChams) | Name | Rule (DTR) |
| |
Operator::Constraint (OpenChams) | HVSlicingNode (OpenChams) | Net (OpenChams) |
| ||
Current (SPICE) |
| Netlist (OpenChams) | Wire (OpenChams) | ||
| Node (OpenChams) | Schematic (OpenChams) | WirePoint (OpenChams) | ||
Schematic::Infos (OpenChams) | NRCCstr (OpenChams) | SimulModel (OpenChams) | |||
DDP (OpenChams) | Instance (SPICE) |
| Sizing (OpenChams) | ||
DesignerCstrOC (OpenChams) | Instance (OpenChams) | SlicingNode (OpenChams) | |||
Device (OpenChams) | InstancePoint (OpenChams) | OpenChamsException (OpenChams) | Source (SPICE) | ||
Generated by doxygen 1.8.5 on Mon Oct 1 2018 | Return to top of page |
VLSI SAPD Documentation | Copyright © 2010 - 2011 UPMC All rights reserved |