\section{Data Structures}
Here are the data structures with brief descriptions\-:\begin{DoxyCompactList}
\item\contentsline{section}{\hyperlink{class_d_t_r_1_1_a_rule}{A\-Rule} }{\pageref{class_d_t_r_1_1_a_rule}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_bloc}{Bloc} }{\pageref{class_open_chams_1_1_bloc}}{}
\item\contentsline{section}{\hyperlink{class_s_p_i_c_e_1_1_capacitor}{Capacitor} }{\pageref{class_s_p_i_c_e_1_1_capacitor}}{}
\item\contentsline{section}{\hyperlink{class_c_i_f_1_1_circuit}{Circuit} }{\pageref{class_c_i_f_1_1_circuit}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_circuit}{Circuit} }{\pageref{class_open_chams_1_1_circuit}}{}
\item\contentsline{section}{\hyperlink{class_s_p_i_c_e_1_1_circuit}{Circuit} }{\pageref{class_s_p_i_c_e_1_1_circuit}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_net_1_1_connection}{Net\-::\-Connection} }{\pageref{class_open_chams_1_1_net_1_1_connection}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_operator_1_1_constraint}{Operator\-::\-Constraint} }{\pageref{class_open_chams_1_1_operator_1_1_constraint}}{}
\item\contentsline{section}{\hyperlink{class_s_p_i_c_e_1_1_current}{Current} }{\pageref{class_s_p_i_c_e_1_1_current}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_d_d_p}{D\-D\-P} }{\pageref{class_open_chams_1_1_d_d_p}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_designer_cstr_o_c}{Designer\-Cstr\-O\-C} }{\pageref{class_open_chams_1_1_designer_cstr_o_c}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_device}{Device} }{\pageref{class_open_chams_1_1_device}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_d_slicing_node}{D\-Slicing\-Node} }{\pageref{class_open_chams_1_1_d_slicing_node}}{}
\item\contentsline{section}{\hyperlink{class_d_t_r_1_1_d_t_r_exception}{D\-T\-R\-Exception} }{\pageref{class_d_t_r_1_1_d_t_r_exception}}{}
\item\contentsline{section}{\hyperlink{class_a_g_d_s_1_1_element}{Element} }{\pageref{class_a_g_d_s_1_1_element}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_equation}{Equation} }{\pageref{class_open_chams_1_1_equation}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_group}{Group} }{\pageref{class_open_chams_1_1_group}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_high_level_cstr}{High\-Level\-Cstr} }{\pageref{class_open_chams_1_1_high_level_cstr}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_h_slicing_node}{H\-Slicing\-Node} }{\pageref{class_open_chams_1_1_h_slicing_node}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_h_v_slicing_node}{H\-V\-Slicing\-Node} }{\pageref{class_open_chams_1_1_h_v_slicing_node}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_schematic_1_1_infos}{Schematic\-::\-Infos} }{\pageref{class_open_chams_1_1_schematic_1_1_infos}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_instance}{Instance} }{\pageref{class_open_chams_1_1_instance}}{}
\item\contentsline{section}{\hyperlink{class_s_p_i_c_e_1_1_instance}{Instance} }{\pageref{class_s_p_i_c_e_1_1_instance}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_instance_point}{Instance\-Point} }{\pageref{class_open_chams_1_1_instance_point}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_intermediate_point}{Intermediate\-Point} }{\pageref{class_open_chams_1_1_intermediate_point}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_layout}{Layout} }{\pageref{class_open_chams_1_1_layout}}{}
\item\contentsline{section}{\hyperlink{class_a_g_d_s_1_1_library}{Library} }{\pageref{class_a_g_d_s_1_1_library}}{}
\item\contentsline{section}{\hyperlink{struct_open_chams_1_1map__item}{map\-\_\-item$<$ Key, Val $>$} }{\pageref{struct_open_chams_1_1map__item}}{}
\item\contentsline{section}{\hyperlink{struct_s_p_i_c_e_1_1map__item}{map\-\_\-item$<$ Key, Val $>$} }{\pageref{struct_s_p_i_c_e_1_1map__item}}{}
\item\contentsline{section}{\hyperlink{class_s_p_i_c_e_1_1_mosfet}{Mosfet} }{\pageref{class_s_p_i_c_e_1_1_mosfet}}{}
\item\contentsline{section}{\hyperlink{class_name}{Name} }{\pageref{class_name}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_net}{Net} }{\pageref{class_open_chams_1_1_net}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_netlist}{Netlist} }{\pageref{class_open_chams_1_1_netlist}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_node}{Node} }{\pageref{class_open_chams_1_1_node}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_n_r_c_cstr}{N\-R\-C\-Cstr} }{\pageref{class_open_chams_1_1_n_r_c_cstr}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_open_chams_exception}{Open\-Chams\-Exception} }{\pageref{class_open_chams_1_1_open_chams_exception}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_operator}{Operator} }{\pageref{class_open_chams_1_1_operator}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_parameters}{Parameters} }{\pageref{class_open_chams_1_1_parameters}}{}
\item\contentsline{section}{\hyperlink{class_c_i_f_1_1_polygon}{Polygon} }{\pageref{class_c_i_f_1_1_polygon}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_port}{Port} }{\pageref{class_open_chams_1_1_port}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_port_point}{Port\-Point} }{\pageref{class_open_chams_1_1_port_point}}{}
\item\contentsline{section}{\hyperlink{class_a_g_d_s_1_1_rectangle}{Rectangle} }{\pageref{class_a_g_d_s_1_1_rectangle}}{}
\item\contentsline{section}{\hyperlink{class_s_p_i_c_e_1_1_resistor}{Resistor} }{\pageref{class_s_p_i_c_e_1_1_resistor}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_r_slicing_node}{R\-Slicing\-Node} }{\pageref{class_open_chams_1_1_r_slicing_node}}{}
\item\contentsline{section}{\hyperlink{class_d_t_r_1_1_rule}{Rule} }{\pageref{class_d_t_r_1_1_rule}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_schematic}{Schematic} }{\pageref{class_open_chams_1_1_schematic}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_simul_model}{Simul\-Model} }{\pageref{class_open_chams_1_1_simul_model}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_sizing}{Sizing} }{\pageref{class_open_chams_1_1_sizing}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_slicing_node}{Slicing\-Node} }{\pageref{class_open_chams_1_1_slicing_node}}{}
\item\contentsline{section}{\hyperlink{class_s_p_i_c_e_1_1_source}{Source} }{\pageref{class_s_p_i_c_e_1_1_source}}{}
\item\contentsline{section}{\hyperlink{class_s_p_i_c_e_1_1_spice_exception}{Spice\-Exception} }{\pageref{class_s_p_i_c_e_1_1_spice_exception}}{}
\item\contentsline{section}{\hyperlink{class_a_g_d_s_1_1_structure}{Structure} }{\pageref{class_a_g_d_s_1_1_structure}}{}
\item\contentsline{section}{\hyperlink{class_s_p_i_c_e_1_1_subckt}{Subckt} }{\pageref{class_s_p_i_c_e_1_1_subckt}}{}
\item\contentsline{section}{\hyperlink{class_d_t_r_1_1_techno}{Techno} }{\pageref{class_d_t_r_1_1_techno}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_transistor}{Transistor} }{\pageref{class_open_chams_1_1_transistor}}{}
\item\contentsline{section}{\hyperlink{class_s_p_i_c_e_1_1_value}{Value} }{\pageref{class_s_p_i_c_e_1_1_value}}{}
\item\contentsline{section}{\hyperlink{class_s_p_i_c_e_1_1_voltage}{Voltage} }{\pageref{class_s_p_i_c_e_1_1_voltage}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_v_slicing_node}{V\-Slicing\-Node} }{\pageref{class_open_chams_1_1_v_slicing_node}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_wire}{Wire} }{\pageref{class_open_chams_1_1_wire}}{}
\item\contentsline{section}{\hyperlink{class_open_chams_1_1_wire_point}{Wire\-Point} }{\pageref{class_open_chams_1_1_wire_point}}{}
\end{DoxyCompactList}
