-- =======================================================================
-- Coriolis Structural VHDL Driver
-- Generated on Dec 12, 2019, 11:42
-- 
-- To be interoperable with Alliance, it uses it's special VHDL subset.
-- ("man vhdl" under Alliance for more informations)
-- =======================================================================

entity capacitor is
  port ( b0 : linkage bit
       ; b1 : linkage bit
       ; b2 : linkage bit
       ; b3 : linkage bit
       ; t0 : linkage bit
       ; t1 : linkage bit
       ; t2 : linkage bit
       ; t3 : linkage bit
       );
end capacitor;

architecture structural of capacitor is



begin

end structural;