# -*- Mode:Python; explicit-buffer-name: "devices.conf" -*- import helpers analogDir = helpers.sysConfDir + '/share/coriolis2/analog' spiceDir = analogDir + 'spice/' devicesTable = \ ( { 'name' : 'DifferentialPairBulkConnected' , 'spice' : spiceDir+'DiffPairBulkConnected.spi' , 'connectors' : ( 'D1', 'D2', 'G1', 'G2', 'S' ) , 'layouts' : ( ('Horizontal M2' , 'DP_horizontalM2.py' ) , ('Symmetrical' , 'DP_symmetrical.py' ) , ('Common centroid', 'DP_2DCommonCentroid.py') , ('Interdigitated' , 'DP_interdigitated.py' ) , ('WIP DP' , 'WIP_DP.py' ) ) } , { 'name' : 'DifferentialPairBulkUnconnected' , 'spice' : spiceDir+'DiffPairBulkUnconnected.spi' , 'connectors' : ( 'D1', 'D2', 'G1', 'G2', 'S', 'B' ) , 'layouts' : ( ('Horizontal M2' , 'DP_horizontalM2.py' ) , ('Symmetrical' , 'DP_symmetrical.py' ) , ('Common centroid', 'DP_2DCommonCentroid.py') , ('Interdigitated' , 'DP_interdigitated.py' ) , ('WIP DP' , 'WIP_DP.py' ) ) } , { 'name' : 'LevelShifterBulkUnconnected' , 'spice' : spiceDir+'LevelShifterBulkUnconnected.spi' , 'connectors' : ( 'D1', 'D2', 'S1', 'S2', 'B' ) , 'layouts' : ( ('Horizontal M2' , 'LS_horizontalM2.py' ) , ('Symmetrical' , 'LS_symmetrical.py' ) , ('Common centroid', 'LS_2DCommonCentroid.py') , ('Interdigitated' , 'LS_interdigitated.py' ) ) } , { 'name' : 'TransistorBulkConnected' , 'spice' : spiceDir+'TransistorBulkConnected.spi' , 'connectors' : ( 'D', 'G', 'S' ) , 'layouts' : ( ('Rotate transistor', 'Transistor_rotate.py' ) , ('Common transistor', 'Transistor_common.py' ) , ('WIP Transistor' , 'WIP_Transistor.py' ) ) } , { 'name' : 'TransistorBulkUnconnected' , 'spice' : spiceDir+'TransistorBulkUnconnected.spi' , 'connectors' : ( 'D', 'G', 'S', 'B' ) , 'layouts' : ( ('Rotate transistor', 'Transistor_rotate.py' ) , ('Common transistor', 'Transistor_common.py' ) , ('WIP Transistor' , 'WIP_Transistor.py' ) ) } , { 'name' : 'CrossCoupledPairBulkConnected' , 'spice' : spiceDir+'CCPairBulkConnected.spi' , 'connectors' : ( 'D1', 'D2', 'S' ) , 'layouts' : ( ('Horizontal M2' , 'CCP_horizontalM2.py' ) , ('Symmetrical' , 'CCP_symmetrical.py' ) , ('Common centroid', 'CCP_2DCommonCentroid.py') , ('Interdigitated' , 'CCP_interdigitated.py' ) ) } , { 'name' : 'CrossCoupledPairBulkUnconnected' , 'spice' : spiceDir+'CCPairBulkUnconnected.spi' , 'connectors' : ( 'D1', 'D2', 'S', 'B' ) , 'layouts' : ( ('Horizontal M2' , 'CCP_horizontalM2.py' ) , ('Symmetrical' , 'CCP_symmetrical.py' ) , ('Common centroid', 'CCP_2DCommonCentroid.py') , ('Interdigitated' , 'CCP_interdigitated.py' ) ) } , { 'name' : 'CommonSourcePairBulkConnected' , 'spice' : spiceDir+'CommonSourcePairBulkConnected.spi' , 'connectors' : ( 'D1', 'D2', 'S', 'G' ) , 'layouts' : ( ('Horizontal M2' , 'CSP_horizontalM2.py' ) , ('Symmetrical' , 'CSP_symmetrical.py' ) , ('Interdigitated' , 'CSP_interdigitated.py' ) , ('WIP CSP' , 'WIP_CSP.py' ) ) } , { 'name' : 'CommonSourcePairBulkUnconnected' , 'spice' : spiceDir+'CommonSourcePairBulkUnconnected.spi' , 'connectors' : ( 'D1', 'D2', 'S', 'G', 'B' ) , 'layouts' : ( ('Horizontal M2' , 'CSP_horizontalM2.py' ) , ('Symmetrical' , 'CSP_symmetrical.py' ) , ('Interdigitated' , 'CSP_interdigitated.py' ) , ('WIP CSP' , 'WIP_CSP.py' ) ) } , { 'name' : 'SimpleCurrentMirrorBulkConnected' , 'spice' : spiceDir+'CurrMirBulkConnected.spi' , 'connectors' : ( 'D1', 'D2', 'S' ) , 'layouts' : ( ('Horizontal M2' , 'SCM_horizontalM2.py' ) , ('Symmetrical' , 'SCM_symmetrical.py' ) , ('Common centroid', 'SCM_2DCommonCentroid.py') , ('Interdigitated' , 'SCM_interdigitated.py' ) ) } , { 'name' : 'SimpleCurrentMirrorBulkUnconnected' , 'spice' : spiceDir+'CurrMirBulkUnconnected.spi' , 'connectors' : ( 'D1', 'D2', 'S', 'B' ) , 'layouts' : ( ('Horizontal M2' , 'SCM_horizontalM2.py' ) , ('Symmetrical' , 'SCM_symmetrical.py' ) , ('Common centroid', 'SCM_2DCommonCentroid.py') , ('Interdigitated' , 'SCM_interdigitated.py' ) ) } , { 'name' : 'MIMCapacitor' , 'spice' : spiceDir+'MIMCapacitor.spi' , 'connectors' : ( 'P1', 'P2' ) , 'layouts' : ( ('SimpleMatrix' , 'MIM_simpleMatrix.py' ) , ) } )