Oroshi - Analog Devices Layout

AUTHOR
Version 1.0
Fri Oct 1 2021 

Table of Contents

Table of contents

Hierarchical Index
Class Hierarchy
This inheritance list is sorted roughly, but not completely, alphabetically:
CapacitorUnit	pagenum
CapacitorStack	pagenum
RoutMatchedCapacitor	pagenum
VerticalRoutingTracks	pagenum
RoutMatchedCapacitor	pagenum

RoutMatchedCapacitor	pagenum
VerticalRoutingTracks	pagenum

Stack	pagenum

Class Index
Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
CapacitorStack (Draws the layout of a compact capacitor or a matrix of adjacent identical capacitors ) 	pagenum
CapacitorUnit (Draws a capacitor of type Poly-Poly or Metal-Metal in 350 nm AMS CMOS technology ) 	pagenum
RoutMatchedCapacitor (Routs two matched capacitors, C1 and C2, drawn in a capacitor matrix ) 	pagenum
Stack (Draw a Stack of Transistors ) 	pagenum
VerticalRoutingTracks (Route two matched capacitors, C1 and C2, drawn in a capacitor matrix ) 	pagenum

Class Documentation
CapacitorStack Class Reference

Draws the layout of a compact capacitor or a matrix of adjacent identical capacitors. 
Inheritance diagram for CapacitorStack:
IMAGE

Public Member Functions
def __init__ (self, device, capacitance, capacitorType, abutmentBoxPosition, nets, unitCap=0, matrixDim=[1, matchingMode=False, matchingScheme=[], dummyRing=False, dummyElement=False)
This is the class constructor. 
def __isUnitCap__ (self)
def __isMatchingSchemeOK__ (self)
def capacitorIdOccurence (self, capacitorIdentifier)
def create (self, bbMode=False)
Draw the compact or matrix of capacitors. 
def capacitorLine (self, dy, abutmentBox_spacing, matchingSchemeRowIndex=0)
Iteratively draws a horizontal or vertical line of capacitors according to the direction  parameter. 
def capacitorMatrix (self, abutmentBox_spacing=0)
Draws a matrix of identical capacitors. 
def drawAbutmentBox (self, abutmentBox_spacing=0)
Draws the abutment box of the matrix or campact capacitor. 
def drawBottomPlatesRLayers (self, bottomPlateRLayer, drawnCapacitor)
Draws the routing layers connecting the bottom plate in the matrix of capacitors. 
def drawTopPlatesRLayers (self, topPlateRLayer, drawnCapacitor)
Draws the routing layers connecting the top plates in the matrix of capacitors. 
def getVerticalRoutingTrack_width (self)
def getMatrixDim (self)
def getMatchingScheme (self)

Detailed Description
Draws the layout of a compact capacitor or a matrix of adjacent identical capacitors. 
The matrix can be composed of one type of capacitors, either Poly-Poly or Metal-Metal in 350 nm AMS CMOS technology. When matching mode is off, every adjacent plates of any consecutive elementary capacitors are connected to each other using vertical routing layers. Otherwise, when matching mode is on, any of elementary capacitors can belong to, $ C_1 $ or $ C_2 $ according to the entered matching scheme. Thus, routing is not done in this class. In both modes, the complete routing process is done using the RoutCapacitor  class. 

Constructor & Destructor Documentation
def __init__ (  self,   device,   capacitance,   capacitorType,   abutmentBoxPosition,   nets,   unitCap = 0,   matrixDim = [1,   matchingMode = False,   matchingScheme = [],   dummyRing = False,   dummyElement = False)

This is the class constructor. 
Basically, the class there are three categories of attributes. There are the ones related to the capacitor caracteristics, its type, dimensions. Also, there are attributes to parametrize the class into matching mode or not and there are other attributes realted to the layout varibales. The class has defaut input values, thus, in this constructor, there are two "sub-constructors" according to the entered input parameters. The class attributes are :
Parameters:
device 	The Hurricane AMS device into which the layout is drawn. 	
capacitance 	The value of the capacitor, expressed in femto Farad (fF). 	
capacitorType 	Can be MIM or PIP type capacitor. 	
abutmentPosition 	Refers to the abscissa (XMin) of the bottom left corner of the abutment Box. 	
abutmentBoxYMin 	Refers to the ordinate (YMin) of the bottom left corner of the abutment Box.	
Except the two last arguments, all the parameters are common with the CapacitorUnit class because the CapacitorStack  constructor calls the mother class constructor to create either a compact capacitor of capacitance  value or rowNumber*  columnNumber  unity capacitors.
Parameters:
rowNumber 	Number of rows in the matrix of capacitors. 	
columnNumber 	Number of columns in the matrix of capacitors. 	
References CapacitorStack.__areInputDataOK__(), CapacitorUnit.__computeCapDim__(), CapacitorStack.__initGivenNonZeroUnitCap__(), CapacitorStack.__initGivenNonZeroUnitCapInMatchingMode__(), CapacitorStack.__initGivenZeroUnitCap__(), CapacitorStack.__initGivenZeroUnitCapInMatchingMode__(), CapacitorStack.__initMatrixMode__(), CapacitorUnit.__isCapacitorUnitOK__(), CapacitorUnit.abutmentBox, CapacitorStack.abutmentBox_spacing, CapacitorStack.abutmentBoxPosition, CapacitorStack.capacitance, CapacitorStack.capacitorIdOccurence(), CapacitorStack.capacitorsNumber, CapacitorUnit.capacitorType, CapacitorStack.compactCapDim, CapacitorStack.computeUnitCap(), CapacitorUnit.device, Stack.device, CapacitorStack.doMatrix, CapacitorStack.dummyElement, CapacitorStack.dummyRing, CapacitorStack.dummyRingPosition, CapacitorStack.evaluateUnitCap(), CapacitorStack.matchingMode, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, CapacitorStack.minEnclosure_hRoutingLayer_topPlate_cut, CapacitorStack.minEnclosure_vRoutingTrackCut, CapacitorStack.minSpacing_vRoutingTrack, CapacitorStack.minSpacing_vRoutingTrackCut, CapacitorStack.minWidth_hRoutingLayer_topPlate_cut, CapacitorStack.minWidth_vRoutingTrack, CapacitorStack.minWidth_vRoutingTrackCut, CapacitorStack.nets, CapacitorStack.unitCapacitance, CapacitorStack.unitCapDim, and CapacitorStack.vRoutingTrack_width.

Member Function Documentation
def __isUnitCap__ (  self)

Returns:
True if the drawn capacitor is a compact one. This function is useful when an instance is called in another class. Example  : when the matrix or the compact capacitors are to be fully routed. 
Referenced by RoutMatchedCapacitor.route().
def __isMatchingSchemeOK__ (  self)

Returns:
True  if the matching scheme specifications are correct. Specifications are :
Similar number of elements as total number of elementary capacitor in the matrix.
Equal number of affected capacitors to C1 as to C2.
Capacitor identifiers equal to '1' or '2' only.
Otherwise, the function returns False . 
References CapacitorStack.matchingScheme, and CapacitorStack.matrixDim.
Referenced by CapacitorStack.capacitorIdOccurence().
def capacitorIdOccurence (  self,   capacitorIdentifier)

Returns:
occurence of capacitor identifier in the entered matching scheme. This is useful to verify that self.matchingScheme  is correct. 
References CapacitorStack.__areMatrixDimOK__(), CapacitorStack.__isMatchingSchemeOK__(), CapacitorStack.capacitorsNumber, CapacitorStack.dummyElement, CapacitorStack.dummyRing, CapacitorStack.matchingMode, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, and CapacitorStack.nets.
Referenced by CapacitorStack.__init__().
def create (  self,   bbMode = False)

Draw the compact or matrix of capacitors. 
First, . Second, . Finally, . 
References CapacitorStack.__initMatchingMode__(), CapacitorStack.abutmentBox_spacing, CapacitorStack.abutmentBoxPosition, CapacitorStack.capacitance, CapacitorStack.capacitorMatrix(), CapacitorUnit.capacitorType, CapacitorStack.computeBondingBoxDimensions(), CapacitorUnit.device, Stack.device, CapacitorStack.doMatrix, CapacitorUnit.drawAbutmentBox(), CapacitorStack.drawBottomPlatesRLayers(), CapacitorStack.drawCapacitorStack(), CapacitorStack.drawTopPlatesRLayers(), CapacitorStack.dummyRing, CapacitorStack.matchingMode, CapacitorStack.matrixDim, CapacitorStack.nets, and CapacitorUnit.setRules().
Referenced by CapacitorStack.capacitorLine(), and CapacitorStack.capacitorMatrix().
def capacitorLine (  self,   dy,   abutmentBox_spacing,   matchingSchemeRowIndex = 0)

Iteratively draws a horizontal or vertical line of capacitors according to the direction  parameter. 
An exception is raised if the specified direction is different from {'horizontal' ,'vertical'}. At every iteration, an instance of the CapacitorUnit class is created and its layout is drawn. 
Returns:
a list containing the drawn capacitors. 
Parameters:
dy 	the vertical position of the first cut in cut line. 	
Remarks:
An exception is raised if the specified direction is different from {'horizontal' ,'vertical'} 
References CapacitorStack.abutmentBoxPosition, CapacitorUnit.capacitorType, CapacitorStack.create(), CapacitorStack.createElementInCapacitorLine(), CapacitorUnit.device, Stack.device, CapacitorStack.dummyRing, CapacitorStack.matchingMode, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, CapacitorStack.nets, and CapacitorStack.unitCapacitance.
Referenced by CapacitorStack.capacitorMatrix().
def capacitorMatrix (  self,   abutmentBox_spacing = 0)

Draws a matrix of identical capacitors. 
The matrix is iterativelly constructed. At every iteration, a new horizontal line of capacitors is drawn. 
Returns:
a nested list of elementary capacitors. 
References CapacitorStack.abutmentBox_spacing, CapacitorStack.abutmentBoxPosition, CapacitorStack.capacitorLine(), CapacitorUnit.capacitorType, CapacitorStack.create(), CapacitorUnit.device, Stack.device, CapacitorStack.dummyRing, CapacitorStack.getCapDim(), CapacitorStack.matrixDim, CapacitorStack.nets, and CapacitorStack.unitCapacitance.
Referenced by CapacitorStack.create().
def drawAbutmentBox (  self,   abutmentBox_spacing = 0)

Draws the abutment box of the matrix or campact capacitor. 

References CapacitorUnit.abutmentBox, CapacitorStack.abutmentBox_spacing, CapacitorStack.abutmentBoxPosition, CapacitorUnit.computeAbutmentBoxDimensions(), CapacitorUnit.device, and Stack.device.
def drawBottomPlatesRLayers (  self,   bottomPlateRLayer,   drawnCapacitor)

Draws the routing layers connecting the bottom plate in the matrix of capacitors. 
First, the relative positions of the routing layer is of the is extracted from the elementary capacitor instance. Then, its width is computed in a way to connect adjacent plates. Then, the routing layers are iterativelly drawn. The two borders are . 
References CapacitorUnit.getBotPlateLeftRLayerXMax(), CapacitorUnit.getBotPlateRLayerWidth(), CapacitorUnit.getBotPlateRLayerYMax(), CapacitorUnit.getBottomPlateLeftCutXMin(), CapacitorUnit.getBottomPlateRightCutXMin(), CapacitorStack.matrixDim, and CapacitorStack.nets.
Referenced by CapacitorStack.create().
def drawTopPlatesRLayers (  self,   topPlateRLayer,   drawnCapacitor)

Draws the routing layers connecting the top plates in the matrix of capacitors. 
First, the relative positions of the routing layers is of the is extracted from the elementary capacitor instance. Then, its width is computed in a way to connect adjacent plates. Then, the routing layers are iterativelly drawn. The two borders are . 
Remarks:
An exception is raised if the number of rows in the matrix is lower than 2. 
References CapacitorUnit.getTopPlateRLayerWidth(), CapacitorUnit.getTopPlateRLayerXCenter(), CapacitorUnit.getTopPlateRLayerYMax(), CapacitorUnit.getTopPlateRLayerYMin(), CapacitorStack.matrixDim, and CapacitorStack.nets.
Referenced by CapacitorStack.create().
def getVerticalRoutingTrack_width (  self)

Returns:
The width of the vertical routing tracks in matching mode. 
Remark: This function is useful in matching mode, ie., in  RoutCapacitor class, when routing the two capacitors. 

def getMatrixDim (  self)

Returns:
A dictionary contaning capacitor matrix's dimensions 
References CapacitorStack.compactCapDim, and CapacitorStack.doMatrix.
def getMatchingScheme (  self)

Returns:
the matching scheme. The function is useful in RoutMatchedCapacitor  class to load self.matchingScheme  attribute. 

The documentation for this class was generated from the following file:
capacitormatrix.py

CapacitorUnit Class Reference

Draws a capacitor of type Poly-Poly or Metal-Metal in 350 nm AMS CMOS technology. 
Inheritance diagram for CapacitorUnit:
IMAGE

Public Member Functions
def __init__ (self, device, capacitorType, abutmentBoxPosition, capacitance=0, capDim={})
This is the class constructor. 
def __setCapacitorPerUnit__ (self, capacitorType)
Sets the area and perimeter capacitances as specified in 350 nm AMS technology and according to capacitorType  (MIM or PIP). 
def __computeCapDim__ (self, capacitance, capacitorType)
Computes width and length of the capacitor. 
def __isCapacitorUnitOK__ (self, capDim)
Checks if the computed capacitor dimensions exceed or are less than maximum and minimum limits, respectively, as specified in technology rules. 
def setRules (self)
Selects technological rules according to the capacitor type. 
def getCapacitorType (self)
def getMaximumCapWidth (self)
maximum size of capacitor's top plate. 
def getMinimumCapWidth (self)
def getLayers (self)
Loads the technology file then extracts the adequate layers according to the capacitor type (MIM or PIP). 
def create (self, t, b, bbMode=False, vEnclosure_botPlate_abtBox=None, hEnclosure_botPlate_abtBox=None)
When bonding box mode is activated, the function draws all layout physical layers of the capacitor after checking its dimensions. 
def drawCapacitor (self, layerDict, t, b)
Draws all layout physicial layers of the capacitor. 
def computeBottomPlateCuts (self)
Computes needed parameters to draw bottom plate cuts in its exact position, including : 
def computeTopPlateCuts (self)
Computes needed parameters to draw top plate cuts in its exact position, including : 
def drawAbutmentBox (self)
Draws the abutment box of the capacitor in position < (abutmentBoxXMin, abutmentBoxYMin)>. 
def drawOnePlate (self, layer, net, boxDimensions)
Draws the top or bottom plate through inflation of the Box under it. 
def drawBottomPlateCut (self, layer, b)
Draws the required cuts to connect the bottom plate. 
def drawTopPlateCut (self, layer, t)
Draws the top plate's cuts after computing the maximal number of cuts that can be placed and its exact enclosure in the top plate. 
def drawRoutingLayers (self, bottomPlateLayer, topPlateLayer, t, b)
Draws the routing layers of both bottom and top plates after computing widths and the exact position of these layers. 
def cutMaxNumber (self, width_layer, width_cut, spacing_cut, enclosure_cut)
Computes the maximal number of cuts to be placed on a layer of width width_layer  considering specifications such as the spacing between the cuts, its width and its enclosure in the layer. 
def cutLine (self, net, layer, firstCutXCenter, firstCutYCenter, width_cut, height_cut, spacing_cut, cutNumber, direction)
Creates a horizontal or vertical line of contacts according to the specified direction. 
def cutMatrix (self, net, layer, firstCutXCenter, firstCutYCenter, width_cut, height_cut, spacing_cut, cutColumnNumber, cutRowNumber)
Creates a matrix of cuts by vertically stacking horizontal lines of identical cuts. 
def getBottomPlateYMax (self)
def getBottomPlateLeftCutXMin (self)
def getBottomPlateLeftCutYMin (self)
def getBottomPlateLeftCutYMax (self)
def getBottomPlateRightCutXMin (self)
def getBottomPlateRightCutYMin (self)
def getBottomPlateRightCutYMax (self)
def getBotPlateLeftRLayerXMax (self)
def getBottomPlateRightCutYCenter (self)
def getBotPlateLeftRLayerXMin (self)
def getBotPlateRLayerYMin (self)
def getBotPlateRLayerYMax (self)
def getBotPlateRLayerWidth (self)
def getBotPlateRightRLayerXCenter (self)
def getBotPlateLeftRLayerXCenter (self)
def getTopPlateRLayerYMin (self)
def getTopPlateRLayerYMax (self)
def getTopPlateRLayerWidth (self)
def getTopPlateRLayerXCenter (self)
def getTopPlateRLayerXMin (self)
def getTopPlateRLayerXMax (self)

Detailed Description
Draws a capacitor of type Poly-Poly or Metal-Metal in 350 nm AMS CMOS technology. 
PIP and MIM capacitors are the result of surface superposition between poly1 and poly2 or metal2 and metalcap layers, respectively. Given the capacitor value, layout dimensions are computed, then, capacitor layers are drawn. Capacitor value, $C$, is given in the expression below, where $ C_a, C_p, A $ and $ P $ are, area capacitance, perimeter capacitance, area and permiter of the capacitor, respectively :  C = C_aA + C_pP  The drawn layout shape is square. Thus, metcap or poly2 length and width are equal and are computed using the capacitor expression. Furthermore, given $ C_a $, $ C_p $ and enclosure technological rules, dimensions and positions of the abutment box as well as the bottom plate are computed. Layouts with dimensions that exceed technological limits cannot be drawn. 

Constructor & Destructor Documentation
def __init__ (  self,   device,   capacitorType,   abutmentBoxPosition,   capacitance = 0,   capDim = {})

This is the class constructor. 
Few of the class attributes final values are computed in this level. Most of attributes are only initialized to zero or empty values. Then, it is computed in dedicated class method. Input parameters are : 
Parameters:
device 	Hurricane AMS device into which layout is drawn. 	
capacitance 	Capacitor value, expressed in $ femto Farad (fF) $. 	
abutmentBoxPosition 	A list containing abscissa and ordinate of the bottom left corner of the abutment box.	
Class attributes are described in the list below. Most of class attributes refer to layout dimensions. Dictionaries are used to group attributes related to the same layout varibale. Layout dimensions and variables are described in Figure 1.
Parameters:
device 	Hurricane AMS device into which layout is drawn. 	
capacitance 	Capacitor value, expressed in $ femto Farad (fF) $. 	
capacitorType 	Can be 'MIMCap' or 'PIPCap' as capacitor type. 	
abutmentBoxDict 	A dictionary containing abscissa and ordinate of the bottom left corner of the abutment box, (XMin) and (YMin), respectively. 	
abutmentBox 	Abutment box drawn square. It is an object of type Box . 	
bottomPlateBox 	Bottom plate drawn square. It is an object of type Box . 	
topPlateBox 	Top plate drawn square. It is an object of type Box . 	
cut2MatrixDict 	A dictionary containing center position of the left bottom, which is cut the first to be drawn in the matrix of cuts. Initially, the dictionary is empty. It is only updated when self.capacitorType  is equal to 'MIMCap' .	
cutLeftLineDict 	A dictionary containing abcissa and ordinate of the bottom cut in the left line of cuts to be drawn on bottom plate's layer. 	
cutRightLineDict 	A dictionary containing abcissa and ordinate of the bottom cut in the right line of cuts to be drawn on bottom plate's layer. 	
topCutLineDict 	A dictionary containing abcissa and ordinate of the bottom cut in the right line of cuts to be drawn on top plate's layer. Initially, the dictionary is empty. It is only updated when self.capacitorType  is equal to 'PIPCap' .	
topPlateRLayerDict 	A dictionary containing position information of the top plate's routing layer. The dictionary includes ordinates of the layer's top and bottom extremities, 'XMin'  and 'YMin' , respectively, the abcissa of it's center, 'XCenter'  and its width, 'width' .	
bottomPlateRLayerDict 	A dictionary containing 	
enclosure_botPlate_topPlate 	Top plate's layer encolusre in bottom plate's layer. 	
minheight_topPlatecut 	Minimum height of cuts for top plate connection to other metal layer. 	
topCutLineNumber 	Maximum possible number cuts to be drawn for top plate's connection. 	
bottomCutLineNumber 	Maximum possible number cuts to be drawn for top plate's connection.	
Remark: Abutment box must be defined as an attribute because the position of dummy capacitor in NonUnitCapacitor  class must be precisely defined. 

References CapacitorUnit.__computeCapacitance__(), CapacitorUnit.__computeCapDim__(), CapacitorUnit.__initCapDim__(), CapacitorUnit.abutmentBox, CapacitorUnit.abutmentBoxDict, CapacitorUnit.bottomCutLineNumber, CapacitorUnit.bottomPlateBox, CapacitorUnit.bottomPlateBoxDict, CapacitorUnit.bottomPlateRLayerDict, CapacitorUnit.capacitorType, CapacitorUnit.capDim, CapacitorUnit.cut2MatrixDict, CapacitorUnit.cutLeftLineDict, CapacitorUnit.cutRightLineDict, CapacitorUnit.device, Stack.device, CapacitorUnit.enclosure_botPlate_abtBox, CapacitorUnit.enclosure_botPlate_topPlate, CapacitorUnit.minheight_topPlatecut, CapacitorUnit.topCutLineDict, CapacitorUnit.topCutLineNumber, CapacitorUnit.topPlateBox, CapacitorUnit.topPlateBoxDict, and CapacitorUnit.topPlateRLayerDict.

Member Function Documentation
def __setCapacitorPerUnit__ (  self,   capacitorType)

Sets the area and perimeter capacitances as specified in 350 nm AMS technology and according to capacitorType  (MIM or PIP). 

Returns:
a list containing the area and perimeter capacitances. 
Remarks:
An exception is raised if the entered capacitor type is unknown. 
Referenced by CapacitorUnit.__computeCapDim__().
def __computeCapDim__ (  self,   capacitance,   capacitorType)

Computes width and length of the capacitor. 
Given capacitance  value as well as the permiter and area capacitances, a quadratic equation is solved where the unknown parameter is the width (also equivalent to the length). 
Returns:
a dictionary containing width and length. 
Remark: The capacitor is square. Thus, length and width are equal. 

References CapacitorUnit.__setCapacitorPerUnit__().
Referenced by CapacitorStack.__init__(), and CapacitorUnit.__init__().
def __isCapacitorUnitOK__ (  self,   capDim)

Checks if the computed capacitor dimensions exceed or are less than maximum and minimum limits, respectively, as specified in technology rules. 

Returns:
True  if all rules are respected. 
Remark: Maximum poly2 layer dimensions for PIP capacitor are not specified in technology rules. Thus, only minimum limit condition is checked. 

References CapacitorUnit.capacitorType, CapacitorUnit.getMaximumCapWidth(), and CapacitorUnit.getMinimumCapWidth().
Referenced by CapacitorStack.__init__(), and CapacitorUnit.create().
def setRules (  self)

Selects technological rules according to the capacitor type. 

Returns:
a dictionary with rules labels as keys and rules as values. Example of technology rules are :
minimum spacing between cuts or metals,
minimum width of a plate, a cut or a routing metal.
etc. Every rule takes two possible value according to the capacitor type (MIM or PIP). Therefore, dictionary keys are generic and its values are specific to the capacitor type. 
Remark: An exception is raised if the entered capacitor type is unknown. 

References CapacitorUnit.capacitorType, CapacitorUnit.hpitch, CapacitorUnit.isVH, Stack.isVH, CapacitorUnit.METAL2Pitch, CapacitorUnit.metal2Width, CapacitorUnit.METAL3Pitch, CapacitorUnit.metal3Width, CapacitorUnit.minEnclo_botPlate_botPlateCut, CapacitorUnit.minEnclo_botPlateRMetal_botPlateCut, CapacitorUnit.minEnclo_routingTrackMetal_cut, CapacitorUnit.minEnclo_topPlate_topPlateCut, CapacitorUnit.minEnclo_topPlateRMetal_topPlateCut, CapacitorUnit.minheight_topPlatecut, CapacitorUnit.minSpacing_botPlate, CapacitorUnit.minSpacing_botPlateCut_topPlate, CapacitorUnit.minSpacingOnBotPlate_cut, CapacitorUnit.minSpacingOnTopPlate_cut, CapacitorUnit.minWidth_botPlatecut, CapacitorUnit.minWidth_botRMetal, CapacitorUnit.minWidth_routingTrackcut, CapacitorUnit.minWidth_topPlate, CapacitorUnit.minWidth_topPlatecut, CapacitorUnit.minWidth_topRMetal, and CapacitorUnit.vpitch.
Referenced by CapacitorStack.create(), CapacitorUnit.create(), RoutMatchedCapacitor.route(), and VerticalRoutingTracks.setRules().
def getCapacitorType (  self)

Returns:
capacitor type 'MIMCap'  or 'PIPCap' . 
Remarks:
getCapacitorType()  is especially useful when an instance of CapacitorUnit  class is called in another classes instances to identify the capacitor's type. 
def getMaximumCapWidth (  self)

maximum size of capacitor's top plate. 
getMaximumCapWidth()  is called to check if capacitor dimensions are within acceptable technological limits. An exception is raised if the entered capacitor type is unknown. 
Remarks:
1. This function is especially usefull in drawing the layout of a unity capacitor, where it is important to garantee that the capacitor size does not exeed the maximum possible value. It is also useful when drawing a matrix of capacitors to make sure that also the unity capacitor respects the maximal values specified. 
2. The maximum value of the poly2 size in PIP capacitor is not specified. Thus, it is not considered in getMaximumCapWidth()  
References CapacitorUnit.capacitorType.
Referenced by CapacitorUnit.__isCapacitorUnitOK__().
def getMinimumCapWidth (  self)

Returns:
The minimum size of the capacitor's top plate. An exception is raised if the entered capacitor type is unknown. 
Remarks:
This function is especially usefull in drawing the layout of a matrix of capacitors where it is important to ensure that the unity capacitor respects the minimal values specified. 
An exception is raised if the entered capacitor type is unknown. 
References CapacitorUnit.capacitorType.
Referenced by CapacitorUnit.__isCapacitorUnitOK__().
def getLayers (  self)

Loads the technology file then extracts the adequate layers according to the capacitor type (MIM or PIP). 

Returns:
a dictionary containing the layer labels as attributes and its values. 
Remarks:
An exception is raised if the entered capacitor type is unknown. 
References CapacitorUnit.capacitorType.
Referenced by CapacitorUnit.create().
def create (  self,   t,   b,   bbMode = False,   vEnclosure_botPlate_abtBox = None,   hEnclosure_botPlate_abtBox = None)

When bonding box mode is activated, the function draws all layout physical layers of the capacitor after checking its dimensions. 
All functions are excecuted in a new Update Session. In the contrary, only an exact estimation of layout dimensions is given. An error is raised when dimensions reach technological limits for MIM and PIP capacitors or when bbMode  parameters is other than True  or False .
Parameters:
( 	t , b ) nets of top and bottom plates, respectively 	
bbMode 	activates bonding box dimensions computing when set to True  	
References CapacitorUnit.__isCapacitorUnitOK__(), CapacitorUnit.abutmentBoxDict, CapacitorUnit.capDim, CapacitorUnit.computeDimensions(), Stack.computeDimensions(), CapacitorUnit.drawAbutmentBox(), CapacitorUnit.drawCapacitor(), Technology.getLayers(), CapacitorUnit.getLayers(), and CapacitorUnit.setRules().
def drawCapacitor (  self,   layerDict,   t,   b)

Draws all layout physicial layers of the capacitor. 

Parameters:
layerDict 	a dictionary containing a description of the required physical layers according to capacitor type 	
( 	t , b ) nets of top and bottom plates, respectively 	
References CapacitorUnit.bottomPlateBox, CapacitorUnit.bottomPlateBoxDict, CapacitorUnit.drawBottomPlateCut(), CapacitorUnit.drawOnePlate(), CapacitorUnit.drawRoutingLayers(), CapacitorUnit.drawTopPlateCut(), CapacitorUnit.topPlateBox, and CapacitorUnit.topPlateBoxDict.
Referenced by CapacitorUnit.create().
def computeBottomPlateCuts (  self)

Computes needed parameters to draw bottom plate cuts in its exact position, including : 

maximum number of cuts to draw on both sides of bottom plate,
adjusted enclosure of
abcissas of the two bottom cuts on left and right sides of bottom plate,
ordinate of the same two cuts.
Given parameters described above, it is possible to draw the entire lines of cuts on both sides of bottom plate using cutLine  function. 
References CapacitorUnit.bottomCutLineNumber, CapacitorUnit.bottomPlateBoxDict, CapacitorUnit.cutLeftLineDict, CapacitorUnit.cutMaxNumber(), CapacitorUnit.cutRightLineDict, CapacitorUnit.minEnclo_botPlate_botPlateCut, CapacitorUnit.minheight_topPlatecut, CapacitorUnit.minSpacing_botPlateCut_topPlate, CapacitorUnit.minSpacingOnBotPlate_cut, CapacitorUnit.minWidth_topPlatecut, and CapacitorUnit.topPlateBoxDict.
Referenced by CapacitorUnit.drawAbutmentBox().
def computeTopPlateCuts (  self)

Computes needed parameters to draw top plate cuts in its exact position, including : 

maximum number of cuts to draw on both sides of top plate,
adjusted enclosure of
abcissas of the two top cuts on left and right sides of top plate,
ordinate of the same two cuts.
Given parameters described above, it is possible to draw the entire lines of cuts on both sides of bottom plate using cutLine  function. 
References CapacitorUnit.abutmentBoxDict, CapacitorUnit.bottomPlateBoxDict, CapacitorUnit.bottomPlateRLayerDict, CapacitorUnit.capacitorType, CapacitorUnit.cut2MatrixDict, CapacitorUnit.cutLeftLineDict, CapacitorUnit.cutMaxNumber(), CapacitorUnit.cutRightLineDict, CapacitorUnit.enclosure_botPlate_topPlate, CapacitorUnit.hEnclosure_botPlate_abtBox, CapacitorUnit.minEnclo_botPlate_botPlateCut, CapacitorUnit.minEnclo_botPlateRMetal_botPlateCut, CapacitorUnit.minEnclo_routingTrackMetal_cut, CapacitorUnit.minEnclo_topPlate_topPlateCut, CapacitorUnit.minEnclo_topPlateRMetal_topPlateCut, CapacitorUnit.minheight_topPlatecut, CapacitorUnit.minSpacing_botPlate, CapacitorUnit.minSpacing_botPlateCut_topPlate, CapacitorUnit.minSpacingOnTopPlate_cut, CapacitorUnit.minWidth_botPlatecut, CapacitorUnit.minWidth_botRMetal, CapacitorUnit.minWidth_routingTrackcut, CapacitorUnit.minWidth_topPlatecut, CapacitorUnit.setBottomPlateAbtBoxEnclosure(), CapacitorUnit.topCutLineDict, CapacitorUnit.topCutLineNumber, CapacitorUnit.topPlateBoxDict, CapacitorUnit.topPlateRLayerDict, and CapacitorUnit.vEnclosure_botPlate_abtBox.
Referenced by CapacitorUnit.drawAbutmentBox().
def drawAbutmentBox (  self)

Draws the abutment box of the capacitor in position < (abutmentBoxXMin, abutmentBoxYMin)>. 
First, the minimum enclosure of the top plate inside the bottom plate is computed. Second, using this parameters as well as the capacitor dimensions, the width and height of the abutment box are computed. The box is finally drawn. 
References CapacitorUnit.abutmentBox, CapacitorUnit.abutmentBoxDict, CapacitorUnit.bottomPlateBoxDict, CapacitorUnit.computeAbutmentBoxDimensions(), CapacitorUnit.computeBottomPlateCuts(), CapacitorUnit.computeOnePlateBoxDimensions(), CapacitorUnit.computeRoutingLayersDimensions(), CapacitorUnit.computeTopPlateCuts(), CapacitorUnit.enclosure_botPlate_topPlate, CapacitorUnit.hEnclosure_botPlate_abtBox, CapacitorUnit.topPlateBoxDict, and CapacitorUnit.vEnclosure_botPlate_abtBox.
Referenced by CapacitorStack.create(), and CapacitorUnit.create().
def drawOnePlate (  self,   layer,   net,   boxDimensions)

Draws the top or bottom plate through inflation of the Box under it. 
These boxes are the abutment box in the case of the bottom plate and the bottom plate's box in the case of the top plate. This function also creates a a net for the drawn plate and sets it as external. 
Returns:
The drawn box. 
Referenced by CapacitorUnit.drawCapacitor().
def drawBottomPlateCut (  self,   layer,   b)

Draws the required cuts to connect the bottom plate. 
First, the maximal possible number of cuts that can be drawn is computed. Second, using the computed number, the enclosure of this cuts in the bottom plate's layer is adjusted while the minimal enclosure is respected. Third, the relative positions of the cuts on both sides of the plate are computed. Finally, two vertical lines of cuts are drawns. 
Remark: The relative positions describe the cordinates of the first bottom cut in every line of cuts. Then, knowing the spacing and width specifications of these cuts the rest of the line is easilly constructed. 

References CapacitorUnit.bottomCutLineNumber, CapacitorUnit.cutLeftLineDict, CapacitorUnit.cutLine(), CapacitorUnit.cutRightLineDict, CapacitorUnit.minheight_topPlatecut, CapacitorUnit.minSpacingOnBotPlate_cut, and CapacitorUnit.minWidth_botPlatecut.
Referenced by CapacitorUnit.drawCapacitor().
def drawTopPlateCut (  self,   layer,   t)

Draws the top plate's cuts after computing the maximal number of cuts that can be placed and its exact enclosure in the top plate. 

References CapacitorUnit.capacitorType, CapacitorUnit.cut2MatrixDict, CapacitorUnit.cutLine(), CapacitorUnit.cutMatrix(), CapacitorUnit.minheight_topPlatecut, CapacitorUnit.minSpacingOnTopPlate_cut, CapacitorUnit.minWidth_topPlatecut, CapacitorUnit.topCutLineDict, and CapacitorUnit.topCutLineNumber.
Referenced by CapacitorUnit.drawCapacitor().
def drawRoutingLayers (  self,   bottomPlateLayer,   topPlateLayer,   t,   b)

Draws the routing layers of both bottom and top plates after computing widths and the exact position of these layers. 
Also computes positions if rlayers that are crucial for routing. 
References CapacitorUnit.bottomPlateRLayerDict, CapacitorUnit.cutLeftLineDict, CapacitorUnit.cutRightLineDict, and CapacitorUnit.topPlateRLayerDict.
Referenced by CapacitorUnit.drawCapacitor().
def cutMaxNumber (  self,   width_layer,   width_cut,   spacing_cut,   enclosure_cut)

Computes the maximal number of cuts to be placed on a layer of width width_layer  considering specifications such as the spacing between the cuts, its width and its enclosure in the layer. 

Referenced by CapacitorUnit.computeBottomPlateCuts(), and CapacitorUnit.computeTopPlateCuts().
def cutLine (  self,   net,   layer,   firstCutXCenter,   firstCutYCenter,   width_cut,   height_cut,   spacing_cut,   cutNumber,   direction)

Creates a horizontal or vertical line of contacts according to the specified direction. 

Referenced by CapacitorUnit.cutMatrix(), CapacitorUnit.drawBottomPlateCut(), and CapacitorUnit.drawTopPlateCut().
def cutMatrix (  self,   net,   layer,   firstCutXCenter,   firstCutYCenter,   width_cut,   height_cut,   spacing_cut,   cutColumnNumber,   cutRowNumber)

Creates a matrix of cuts by vertically stacking horizontal lines of identical cuts. 

Parameters:
net 	net to which the cuts belong 	
layer 	cuts physical layer 	
firstCutXCenter 	center's abcissa of the bottom left cut ( that is the first cut to be drawn in the matrix ) 	
firstCutYCenter 	center's abcissa of the bottom left cut 	
(width_cut,height_cut,spacing_cut) 	cuts dimenions 	
(cutColumnNumber,cutRowNumber) 	matrix dimensions	
Remarks:
The matrix can have any dimensions zero or negative one. 
References CapacitorUnit.cutLine().
Referenced by CapacitorUnit.drawTopPlateCut().
def getBottomPlateYMax (  self)

Returns:
the ordinate of the bottom plate's highest end-point ( that is equivalent to dySource  of the bottom plate's box ) . 
References CapacitorUnit.bottomPlateBoxDict.
def getBottomPlateLeftCutXMin (  self)

Returns:
the abcissa of the bottom plate's left line of cuts. 
Referenced by CapacitorStack.drawBottomPlatesRLayers(), and RoutMatchedCapacitor.drawCuts_vRoutingTrack_hRoutingTrack().
def getBottomPlateLeftCutYMin (  self)

Returns:
the ordinate of the first ( or bottom) cut in the left line of cuts on the bottom plate. 
def getBottomPlateLeftCutYMax (  self)

Returns:
the ordinate of the highest cut of the bottom plate's left line of cuts. 
References CapacitorUnit.bottomCutLineNumber, CapacitorUnit.minSpacingOnBotPlate_cut, and CapacitorUnit.minWidth_botPlatecut.
def getBottomPlateRightCutXMin (  self)

Returns:
the absissa of the bottom plate's right line of cuts. 
Referenced by CapacitorStack.drawBottomPlatesRLayers(), and RoutMatchedCapacitor.drawCuts_vRoutingTrack_hRoutingTrack().
def getBottomPlateRightCutYMin (  self)

Returns:
the ordinate of the first ( or bottom) cut in the right line of cuts on the bottom plate. 
Referenced by RoutMatchedCapacitor.computeHRLayerYCenter(), and CapacitorUnit.getBottomPlateRightCutYCenter().
def getBottomPlateRightCutYMax (  self)

Returns:
the ordinate of the highest ( or top) cut in the right line of cuts on the bottom plate. 
References CapacitorUnit.bottomCutLineNumber, CapacitorUnit.minSpacingOnBotPlate_cut, and CapacitorUnit.minWidth_botPlatecut.
Referenced by RoutMatchedCapacitor.computeHRLayerYCenter(), and CapacitorUnit.getBottomPlateRightCutYCenter().
def getBotPlateLeftRLayerXMax (  self)

Returns:
the center's ordinate of the bottom plate's left cut (the cut that is the first one in the line). 
Referenced by CapacitorStack.drawBottomPlatesRLayers().
def getBottomPlateRightCutYCenter (  self)

Returns:
the position of the bottom plate's right cuts on the horitontal axis (also applicable to left cuts). 
References CapacitorUnit.getBottomPlateRightCutYMax(), and CapacitorUnit.getBottomPlateRightCutYMin().
def getBotPlateLeftRLayerXMin (  self)

Returns:
the position of the bottom plate's left cuts on the horitontal axis. 
def getBotPlateRLayerYMin (  self)

Returns:
the position of bottom plate's left cuts on the horitontal axis. 
Referenced by RoutMatchedCapacitor.route().
def getBotPlateRLayerYMax (  self)

Returns:
the position of bottom plate's left cuts on the horitontal axis. 
Referenced by CapacitorStack.drawBottomPlatesRLayers().
def getBotPlateRLayerWidth (  self)

Returns:
the position of bottom plate's left cuts on the horitontal axis. 
Referenced by CapacitorStack.drawBottomPlatesRLayers(), RoutMatchedCapacitor.drawCuts_vRoutingTrack_hRoutingTrack(), and RoutMatchedCapacitor.route().
def getBotPlateRightRLayerXCenter (  self)

Returns:
the position of bottom plate's left cuts on the horitontal axis. 
Referenced by RoutMatchedCapacitor.route().
def getBotPlateLeftRLayerXCenter (  self)

Returns:
the position of bottom plate's left cuts on the horitontal axis. 
Referenced by RoutMatchedCapacitor.route().
def getTopPlateRLayerYMin (  self)

Returns:
the ordinate of the bottom end points of the top plate routing layer. 
Referenced by CapacitorStack.drawTopPlatesRLayers(), and RoutMatchedCapacitor.route().
def getTopPlateRLayerYMax (  self)

Returns:
the ordinate of the higher end points of the top plate routing layer. 
Referenced by CapacitorStack.drawTopPlatesRLayers().
def getTopPlateRLayerWidth (  self)

Returns:
the width of top plate's routing layer. 
Referenced by RoutMatchedCapacitor.drawCuts_vRoutingTrack_hRoutingTrack(), CapacitorStack.drawTopPlatesRLayers(), and RoutMatchedCapacitor.route().
def getTopPlateRLayerXCenter (  self)

Returns:
the center's abcissa of the bottom plate routing layer. 
Referenced by CapacitorStack.drawTopPlatesRLayers().
def getTopPlateRLayerXMin (  self)

Returns:
the origin (bottom-left end point) abcissa of the top plate routing layers. 
References CapacitorUnit.topPlateRLayerDict.
Referenced by RoutMatchedCapacitor.__computeConnections__(), and RoutMatchedCapacitor.drawCuts_vRoutingTrack_hRoutingTrack().
def getTopPlateRLayerXMax (  self)

Returns:
the abscissa of the bottom-right end-point of the top plate routing layer. 
References CapacitorUnit.topPlateRLayerDict.

The documentation for this class was generated from the following file:
capacitorunit.py

RoutMatchedCapacitor Class Reference

Routs two matched capacitors, C1 and C2, drawn in a capacitor matrix. 
Inheritance diagram for RoutMatchedCapacitor:
IMAGE

Public Member Functions
def __init__ (self, vRTInstance)
A special method used to customize the class instance to an initial state in which : 
def route (self, bbMode=False)
Draws the complete layout given the capacitor matrix. 
def setRules (self)
Defines technology rules used to draw the layout. 
def setLayers (self)
Defines all physical layers used to draw the layout. 
def computeDimensions (self, bbMode)
Computes, through simple instructions and functions calls, layout variables detailed in Figure 2. 
def computeHRoutingTrackYCenter (self)
Computes centers' ordinates of the eight horizontal routing tracks. 
def computeHRLayerYCenter (self)
Sets the stretching value of top plates. 
def drawHRoutingTracks (self, routingTracksLayer)
Iteratively draws horizontal routing tracks on top and bottom positions of the matrix using physical layer routingTracksLayer . 
def drawHRLayers (self, xPlateRLayer)
Iteratively draws the horizontal routing layers starting with bottom left elementary capacitor $ C_00 $. 
def drawCuts (self, layer_hRTrack_hRLayer, layer_tracksCut, layer_topPlateCut)
Draws all required cuts using physical layers : 
def drawOneCut_vRoutingTrack_HRLayer (self, net, cutLayer, cutXMin, cutYMin, cutNumber)
Draws one cut, in layer cutLayer , in order to connect a vertical routing track, at position cutXMin  in metal 2, and a horizontal routing track, at position cutYMin  in metal 3. 
def drawCuts_vRoutingTrack_hRoutingTrack (self, cutLayer, cutNumber, enclosure_cut)
Draws cuts to connect vertical routing tracks in metal 2 and horizontal routing tracks in metal 3. 
def __stretchTopPlates__ (self, capacitor, rlayer)
Iteratively performs top plates stretching for the capacitor matrix. 
def __stretchTopPlateCompactCap__ (self, net, capacitor, routingLayer, j=0)
Draws vertical stretched layers for a given elementary capacitor. 
def __setStretchingDySourceDyTarget__ (self, capacitor, deltay)
Sets the abcissas of the extremities of the vertical stretching to be applied to capacitor's top plates for a given elementary capacitor in the matrix. 
def __computeConnections__ (self, i, j, capacitorIdentifier)
Computes horizontal routing layers source and target abcissas for top and bottom plates connections to its associated routing track. 

Detailed Description
Routs two matched capacitors, C1 and C2, drawn in a capacitor matrix. 
Connections are put in place with reference to a given matching scheme. Elementary capacitor units are connected to horizontal and vertical routing tracks that represent top plates and bottom plates nets of C1 and C2 . Supported types of capacitors are Poly-Poly and Metal-Metal. Technologycal rules are provided by 350 nm AMS CMOS technology with three-four metal layers. Metal layers that are used for routing are placed similarly to horziontal-vertical (HV) symbolic Alliance CAD tool router, where horizontal metal channels are drawn in metal 2 and the vertical ones are in metal 3. Given a matrix of dimensions $ R*C $, the total number of vertical tracks is $ 2C+2 $ equivalent to $ C+1 $ couples, ensuring that every elementary capacitor is positioned between four vertical tracks, two from each side. In fact, every adjacent couple of these tracks represent top plates and bottom plates of C1 or C2 as shown in Figure 1.  An elementary capacitor unit can be a part of C1 or C2 according to the matching scheme. However, to respect common-centroid layout specifications, for C1 and C2 to be equal, the matrix number of colums and number of rows must be both even. Addionnally, the number of elementary capacitors dedicated to C1 must be equal to those dedicated to C2. These two conditions are tested in one of the class methods. An exception is raised if at least one of the two is not respected. 

Constructor & Destructor Documentation
def __init__ (  self,   vRTInstance)

A special method used to customize the class instance to an initial state in which : 

the class attirbutes describing positions and dimensions of the layout are computed in dedicated class methods,
the attributes related to the capacitor matrix are copied from the CapacitorStack  instance.
Position and dimensions attributes, also refered by layout variables, in Figure 2, are defined below : 
Parameters:
device 	The Hurricane AMS device onto which the layout is drawn. 	
capacitorInstance 	Instance of CapacitorStack  class. 	
capacitor 	A nested list containing the matrix elements, which are CapacitorUnit  objects. 	
matchingScheme 	A nested list, with equal dimensions as capacitor  attribute, containing assignements of matrix elementary units to C1 and C2, identified by 1 and 2, respectively. Therefore, self.matchingScheme  content is a succession of 1 and 2 values, defined as \ capacitor identifiers. For example, given a matrix of dimensions 2x2, the matching scheme can be $ [ [1,2], [1,2] ] or [ [2,1], [2,1] ] $. The first sub-list dictates that the first elementary capacitor, $ C_00 $. The second element $ C_01 $ is affected to C2 and so on. An immediate and obvious consequence to this, is that an error is raised if self.matchingSchem  and self.capacitor  dimensions are not identical or if self.matchingScheme  content is different from supported capacitor identifiers, '1' and '2'.	
capacitorType 	Supported types of capacitors are MIM and PIP only. An exception is raised otherwise. 	
abutmentBox 	The matrix's abutment box. 	
matrxiDim 	The matrix dimensions, also equal to self.matchingScheme  nested list dimensions. 	
abutmentBox_spacing 	The spacing between elementary units in the matrix. It is computed in CapacitorStack  and is reloaded in RoutMatchedCapacitor . self.abutmentBox_spacing  includes, vertical routing tracks width and minimum allowed spacing between two adjacent ones. 	
hRoutingLayer_width 	The width of horizontal routing layers in metal 2, which connect capacitors plates to vertical routing tracks. 	
vRoutingTrack_width 	The width of vertical routing tracks in metal 3, which connects identical nets together ( ie : bottom plates of C1, top plates of C2, bottom plates of C2 and top plates of C2 ). 	
hRoutingTrack_width 	The width of horizontal routing tracks in metal 2, which connect identical vertical routing tracks together. 	
minSpacing_hRoutingTrack 	Minimum spacing between horizontal routing tracks. Wide metal 2 specifications are considered since metal 2 dimensions may exceed 10 $ m$.	
Remark: For more information about wide metal specifications, refer to ENG-183_rev8.pdf technology manual. 

Parameters:
minimumPosition 	The ordinate of the top plate's routing layer's bottom extremity after stretching. 	
maximumPosition 	The ordinate of the top plate's routing layer's top extremity, also equivalent to the top plate's top extremity. 	
vRoutingTrackXCenter 	A nested list of ordered dictionaries, with dimensions equal to self.matrixDim , containing abcissas of vertical routing tracks. All sub-lists' lengths are identical and are equal to 2. The first and second elements describe position of top plate track and bottom plate track, respectively. For example, given a matrix of dimensions 2x2, self.vRoutingTrackXCenter  can be [[0, 2], [4,6], [8,10]] $ m$. Elements of this nested list have particular indexing as described in Figure 2.	
hRoutingtrackYCenter 	A nested dictonary containing two keys, topTracks  and bottomTracks . Each key contains as value a dictionary describing centers' ordinates of four parallel horizontal tracks. The reason why four tracks are needed on top and bottom positions of the matrix is that four nets are used, two for every capacitor Ci , were i  is in [1,2]. 	
hRoutingLayerYCenter 	A nested dicitonary containing two keys, top  and bottom . Each key contains as value a dictionary describing centers' ordinates of horizontal routing layers. 	
vRoutingTrackDict 	A dictionary of routing tracks top and bottom extremities ordinates. 	
topPlateStretching 	Since not only the same metal 2 layer is used to draw top/bottom plates connections to vertical tracks but also the two plates are superimposed, the top plate's routing tracks is stretched. self.topPlateStretching  is therefore the length added to top plate's routing layer in order to avoid short circuits between top and bottom plates routing to vertical tracks since the same metal is used for both. 	
References RoutMatchedCapacitor.capacitor, CapacitorStack.dummyRing, RoutMatchedCapacitor.dummyRingCapacitor, RoutMatchedCapacitor.hRoutingLayer_width, RoutMatchedCapacitor.hRoutingLayerYCenter, RoutMatchedCapacitor.hRoutingTrack_width, RoutMatchedCapacitor.hRoutingtrackYCenter, CapacitorStack.matrixDim, RoutMatchedCapacitor.maximumPosition, RoutMatchedCapacitor.minimumPosition, RoutMatchedCapacitor.minSpacing_hRoutingTrack, RoutMatchedCapacitor.topPlateStretching, and RoutMatchedCapacitor.vRTInstance.

Member Function Documentation
def route (  self,   bbMode = False)

Draws the complete layout given the capacitor matrix. 
route  method is succession of calls to user-defined methods inside a newly created Updatesession . The following tasks are excecuted :
1.	A nex UpdateSession  is created,
2.	all required physical layers are loaded,
3.	technology rules are defined according to capacitor type,
4.	layout dimension parameters are computed,
5.	routing tracks and layers are drawn,
6.	top plates are stretched,
7.	all required cuts are drawn,
8.	The UpdateSession  is closed.
Meanwhile, an exception is raised when the entered capacitor  is not a capacitor matrix or if the capacitor type is unsupported. 
References CapacitorStack.__isUnitCap__(), RoutMatchedCapacitor.__stretchTopPlates__(), CapacitorUnit.abutmentBox, RoutMatchedCapacitor.capacitor, VerticalRoutingTracks.capacitorInstance, CapacitorUnit.computeDimensions(), Stack.computeDimensions(), CapacitorUnit.device, Stack.device, RoutMatchedCapacitor.drawCuts(), RoutMatchedCapacitor.drawDummyRing_hRTracks_Cuts(), RoutMatchedCapacitor.drawHRLayers(), RoutMatchedCapacitor.drawHRoutingTracks(), CapacitorStack.dummyRing, RoutMatchedCapacitor.dummyRingCapacitor, CapacitorUnit.getBotPlateLeftRLayerXCenter(), CapacitorUnit.getBotPlateRightRLayerXCenter(), CapacitorUnit.getBotPlateRLayerWidth(), CapacitorUnit.getBotPlateRLayerYMin(), CapacitorUnit.getTopPlateRLayerWidth(), CapacitorUnit.getTopPlateRLayerYMin(), VerticalRoutingTracks.getVTrackYMax(), VerticalRoutingTracks.getVTrackYMin(), CapacitorUnit.hpitch, RoutMatchedCapacitor.hRoutingtrackYCenter, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, RoutMatchedCapacitor.maximumPosition, CapacitorUnit.metal3Width, RoutMatchedCapacitor.minimumPosition, CapacitorStack.nets, RoutMatchedCapacitor.routeDummyRing(), RoutMatchedCapacitor.routeLeftAndRightSides(), RoutMatchedCapacitor.routeTopOrBottomSide(), RoutMatchedCapacitor.setLayers(), CapacitorUnit.setRules(), CapacitorUnit.vpitch, CapacitorStack.vRoutingTrack_width, and RoutMatchedCapacitor.vRoutingTrackXCenter.
def setRules (  self)

Defines technology rules used to draw the layout. 
Some of the rules, namely those describing routing layers and tracks are applicable for both MIM and PIP capacitors. However, cuts rules are different.
Remark: All CapacitorStack  class rules are also reloaded in this class.
An exception is raised if the entered capacitor type is unsupported.
Returns:
a dictionary with rules labels as keys and rules content as values. 
References CapacitorUnit.capacitorType, CapacitorStack.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minSpacing_hRoutingLayer, RoutMatchedCapacitor.minSpacing_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minSpacing_hRoutingLayer_vRoutingTrack_cut, RoutMatchedCapacitor.minSpacing_hRoutingTrackCut, CapacitorStack.minSpacing_vRoutingTrackCut, and CapacitorStack.minWidth_hRoutingLayer_topPlate_cut.
def setLayers (  self)

Defines all physical layers used to draw the layout. 
Layers are loaded using DataBase  API. The same routing layers are used for both capacitor types except cuts layers that connect top plates to vertical routing tracks. Basicaly, metal 2, meta 3, cut 1 and cut 2 are the ones defined. 
Returns:
a dictionary composed of layers labels as keys and layers as values. 
References CapacitorUnit.capacitorType, and CapacitorStack.dummyRing.
Referenced by RoutMatchedCapacitor.route().
def computeDimensions (  self,   bbMode)

Computes, through simple instructions and functions calls, layout variables detailed in Figure 2. 

References CapacitorStack.abutmentBox_spacing, VerticalRoutingTracks.capacitorInstance, CapacitorStack.capacitorsNumber, RoutMatchedCapacitor.computeBondingBoxDimInbbMode(), RoutMatchedCapacitor.computeHRLayerYCenter(), RoutMatchedCapacitor.computeHRoutingTrackYCenter(), RoutMatchedCapacitor.hRoutingLayer_width, CapacitorStack.matrixDim, RoutMatchedCapacitor.maximumPosition, CapacitorStack.minEnclosure_hRoutingLayer_topPlate_cut, VerticalRoutingTracks.minEnclosure_hRoutingLayer_vRoutingTrack_cut, RoutMatchedCapacitor.minimumPosition, VerticalRoutingTracks.minWidth_hRoutingLayer, CapacitorStack.minWidth_hRoutingLayer_topPlate_cut, VerticalRoutingTracks.minWidth_hRoutingLayer_vRoutingTrack_cut, RoutMatchedCapacitor.vRoutingTrack_spacing, CapacitorStack.vRoutingTrack_width, RoutMatchedCapacitor.vRoutingTrackDict, RoutMatchedCapacitor.vRoutingTrackXCenter, and RoutMatchedCapacitor.vRTInstance.
def computeHRoutingTrackYCenter (  self)

Computes centers' ordinates of the eight horizontal routing tracks. 
The tracks include four on top and four on bottom of the matrix. To do the computations, fist, center of the first bottom or top track, given in Figure 2, is computed. Then, all adjacent three centers are deduced by simples translation of the first one. Translation quantity is equal to the sum of distance between adjacent routing tracks, self.hRoutingTracks_spacing, and half width of the routing track itself, self.hRoutingTrack_width . 
References RoutMatchedCapacitor.__setPlatesIds__(), CapacitorUnit.hpitch, RoutMatchedCapacitor.hRoutingtrackYCenter, RoutMatchedCapacitor.maximumPosition, and RoutMatchedCapacitor.minimumPosition.
Referenced by RoutMatchedCapacitor.computeDimensions().
def computeHRLayerYCenter (  self)

Sets the stretching value of top plates. 
Then iteratively computes the centers of horizontal routing layer regarding top and bottom plates. 
References RoutMatchedCapacitor.__findPossibleShortCircuits__(), VerticalRoutingTracks.__setStretching__(), RoutMatchedCapacitor.__setStretchingDySourceDyTarget__(), RoutMatchedCapacitor.bondingBox, RoutMatchedCapacitor.capacitor, CapacitorUnit.getBottomPlateRightCutYMax(), CapacitorUnit.getBottomPlateRightCutYMin(), RoutMatchedCapacitor.hRoutingLayer_width, RoutMatchedCapacitor.hRoutingLayerYCenter, RoutMatchedCapacitor.hRoutingTrack_width, RoutMatchedCapacitor.hRoutingtrackYCenter, CapacitorStack.matrixDim, RoutMatchedCapacitor.minSpacing_hRoutingLayer, RoutMatchedCapacitor.topPlateStretching, CapacitorStack.vRoutingTrack_width, and RoutMatchedCapacitor.vRoutingTrackXCenter.
Referenced by RoutMatchedCapacitor.computeDimensions().
def drawHRoutingTracks (  self,   routingTracksLayer)

Iteratively draws horizontal routing tracks on top and bottom positions of the matrix using physical layer routingTracksLayer . 

References CapacitorUnit.device, Stack.device, RoutMatchedCapacitor.hRoutingTrack_width, RoutMatchedCapacitor.hRoutingtrackYCenter, CapacitorStack.nets, and RoutMatchedCapacitor.vRoutingTrackXCenter.
Referenced by RoutMatchedCapacitor.route().
def drawHRLayers (  self,   xPlateRLayer)

Iteratively draws the horizontal routing layers starting with bottom left elementary capacitor $ C_00 $. 

References RoutMatchedCapacitor.__computeConnections__(), RoutMatchedCapacitor.hRoutingLayer_width, RoutMatchedCapacitor.hRoutingLayerYCenter, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, and CapacitorStack.nets.
Referenced by RoutMatchedCapacitor.route().
def drawCuts (  self,   layer_hRTrack_hRLayer,   layer_tracksCut,   layer_topPlateCut)

Draws all required cuts using physical layers : 

layer_hRTrack_hRLayer  to connect bottom plates to vertical routing tracks,
layer_tracksCut  to connect vertical routing tracks to horizontal ones,
layer_topPlateCut  to connect top plates to vertical routing tracks. ALso in drawCuts , nUmber of maximum cuts number on every layer is computed and cuts enclosure is adjusted according to layer's width. 
References RoutMatchedCapacitor.__setPlatesLabels__(), VerticalRoutingTracks.capacitorIds, CapacitorStack.capacitorsNumber, RoutMatchedCapacitor.drawCuts_stretchedTopPlate(), RoutMatchedCapacitor.drawCuts_vRoutingTrack_HRLayer(), RoutMatchedCapacitor.drawCuts_vRoutingTrack_hRoutingTrack(), RoutMatchedCapacitor.drawOneCut_vRoutingTrack_HRLayer(), RoutMatchedCapacitor.hRoutingLayerYCenter, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, CapacitorStack.minEnclosure_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_hRoutingTrackCut, CapacitorStack.minSpacing_vRoutingTrackCut, VerticalRoutingTracks.minWidth_hRoutingTrackCut, CapacitorStack.minWidth_vRoutingTrackCut, CapacitorStack.nets, CapacitorStack.vRoutingTrack_width, and RoutMatchedCapacitor.vRoutingTrackXCenter.
Referenced by RoutMatchedCapacitor.route().
def drawOneCut_vRoutingTrack_HRLayer (  self,   net,   cutLayer,   cutXMin,   cutYMin,   cutNumber)

Draws one cut, in layer cutLayer , in order to connect a vertical routing track, at position cutXMin  in metal 2, and a horizontal routing track, at position cutYMin  in metal 3. 

References RoutMatchedCapacitor.minSpacing_hRoutingLayer_vRoutingTrack_cut, and VerticalRoutingTracks.minWidth_hRoutingLayer_vRoutingTrack_cut.
Referenced by RoutMatchedCapacitor.drawCuts().
def drawCuts_vRoutingTrack_hRoutingTrack (  self,   cutLayer,   cutNumber,   enclosure_cut)

Draws cuts to connect vertical routing tracks in metal 2 and horizontal routing tracks in metal 3. 

References RoutMatchedCapacitor.__setPlatesIds__(), RoutMatchedCapacitor.capacitor, RoutMatchedCapacitor.dummyRingCapacitor, CapacitorUnit.getBotPlateRLayerWidth(), CapacitorUnit.getBottomPlateLeftCutXMin(), CapacitorUnit.getBottomPlateRightCutXMin(), CapacitorUnit.getTopPlateRLayerWidth(), CapacitorUnit.getTopPlateRLayerXMin(), RoutMatchedCapacitor.hRoutingLayerYCenter, RoutMatchedCapacitor.hRoutingtrackYCenter, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, CapacitorStack.minEnclosure_hRoutingLayer_topPlate_cut, CapacitorStack.minEnclosure_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minSpacing_hRoutingTrackCut, CapacitorStack.minSpacing_vRoutingTrackCut, CapacitorStack.minWidth_hRoutingLayer_topPlate_cut, VerticalRoutingTracks.minWidth_hRoutingTrackCut, CapacitorStack.minWidth_vRoutingTrackCut, CapacitorStack.nets, CapacitorStack.vRoutingTrack_width, and RoutMatchedCapacitor.vRoutingTrackXCenter.
Referenced by RoutMatchedCapacitor.drawCuts().
def __stretchTopPlates__ (  self,   capacitor,   rlayer)

Iteratively performs top plates stretching for the capacitor matrix. 
Vertical segments are connected to top plate routing layer. 
Parameters:
capacitor 	Capacitor matrix. 	
rlayer 	Layer of the drawn vertical rectangle. 	
References RoutMatchedCapacitor.__stretchTopPlateCompactCap__(), CapacitorStack.matchingScheme, CapacitorStack.matrixDim, and CapacitorStack.nets.
Referenced by RoutMatchedCapacitor.route().
def __stretchTopPlateCompactCap__ (  self,   net,   capacitor,   routingLayer,   j = 0)

Draws vertical stretched layers for a given elementary capacitor. 

References RoutMatchedCapacitor.__setStretchingDySourceDyTarget__(), and RoutMatchedCapacitor.topPlateStretching.
Referenced by RoutMatchedCapacitor.__stretchTopPlates__().
def __setStretchingDySourceDyTarget__ (  self,   capacitor,   deltay)

Sets the abcissas of the extremities of the vertical stretching to be applied to capacitor's top plates for a given elementary capacitor in the matrix. 

Parameters:
capacitor 	.values() Elementary unit capacitor. 	
deltay 	Stretching value. 	
Returns:
A list that contains dySource  and  as top extremity and bottom extermity, respectively. 
Referenced by RoutMatchedCapacitor.__stretchTopPlateCompactCap__(), and RoutMatchedCapacitor.computeHRLayerYCenter().
def __computeConnections__ (  self,   i,   j,   capacitorIdentifier)

Computes horizontal routing layers source and target abcissas for top and bottom plates connections to its associated routing track. 

Parameters:
(i,j) 	row and column indexes, respectively, in the matrix which describe the elementary capacitor position in the matrix. 	
capacitorIdentifier 	equal to '1' if C1 and '2' if C2. 	
Returns:
A nested dicitionary. The overal dictionary is composed of keys equal to topPlate  and  bottomPlate and values equal to sub-dictionaries. The sub-dictionaries, are in their turn composed of two keys standing for the abcissa of the source and the abcissa of the target. 
Remark: Naturally, an exception is raised if an unsupported capacitor identifier is given. 

References RoutMatchedCapacitor.__findHRLDyTrarget__(), RoutMatchedCapacitor.__isCapacitorAdummy__(), RoutMatchedCapacitor.__setPlatesLabels__(), RoutMatchedCapacitor.capacitor, VerticalRoutingTracks.capacitorIds, CapacitorStack.capacitorsNumber, CapacitorStack.dummyElement, CapacitorStack.dummyRing, CapacitorUnit.getTopPlateRLayerXMin(), CapacitorStack.matchingScheme, CapacitorStack.matrixDim, CapacitorStack.nets, CapacitorStack.vRoutingTrack_width, RoutMatchedCapacitor.vRoutingTrackXCenter, RoutMatchedCapacitor.vRTInstance, and RoutMatchedCapacitor.vRTsDistribution.
Referenced by RoutMatchedCapacitor.drawHRLayers().

The documentation for this class was generated from the following file:
capacitorrouted.py

Stack Class Reference

Draw a Stack of Transistors. 
Inherits object.
Public Member Functions
def __init__ (self, device, NERC, NIRC)
[API]  Constructor 
def setWirings (self, wiringSpec)
[API]  Set the Stack wiring specification. 
def computeDimensions (self)
[internal]  Compute Stack dimensions from the technological rules. 
def doLayout (self, bbMode)
[API]  Draw the complete layout. 

Detailed Description
Draw a Stack of Transistors. 
A Stack of Transistors is a set of transistor put into a regular band and connected through their sources/drains. All share the exact same W & L. The way they are connecteds defines what functionnality the Stack implement.
The abutment box of the stack is adjusted so that both height and width are even multiples of the track pitches, so the device can be easily placed and handled by the mixed router. The extra space needed for padding is added around the active area. Due to the presence of tracks at the top and bottom of the stack, the active area will be horizontally centered but not  vertically.
The drawing of the stack is controlled through a set of variables (attributes) that allows to create it regardless of the technology. The technology is taken into account in the way those variables are computed and, obviously, their values. The following schematics details the main stack drawing variables along with their computations.
Stack Layout
Gate pitch

self.gatePitch  : the pitch of transistors gates, inside the stack. It also applies to dummy transistors.
 
Active Side Width

self.activeSideWidth  : the distance between the axis of the last transistor gate (on the left or right) and the edge of the active area (not  the diffusion area).
 
H-Track Distance

self.hTrackDistance  : the minimal distance between either the top or bottom edge of the active area and the axis  of the first track.
 
BoundingBox & Overall Variables

self.xpitches  : the number of vertical track pitches needed to fully enclose the active area.
self.ypitches  : the number of horizontal track pitches needed to fully enclose the active area.
self.activeOffsetX  & self.activeOffsetY  : the offsets of the active area from the bottom left corner of the abutment box.
self.diffusionWidth  & self.diffusionHeight  are the minimun dimensions required to fit the active area.
self.topTracksNb()  : the number of tracks at the top of the stack.
self.botTracksNb()  : the number of tracks at the bottom of the stack.

Wiring Specifications
Stack routing is done through vertical metal1  wires coming from the gates and diffusions areas and metal2  horizontal wires that can be either above or below the active area. metal2  wires (or track) goes through the whole stack and are assigned to one net only. A net will have at least one track above or below and may have both.
The connections to the diffusions areas and gates of the various fingers are specified through a list. The stack is made of a regular alternation of diffusions and gates. The list tells, for each one starting from the left, to which net and track they are connected. For a stack of $NFs$ transistor fingers, the must wiring specification must contains $ 3 + (NFs-1) 2$ elements. The list is given through one string  with each elements separated by one or more whitespace. The syntax for one  element is detailed Atomic Wiring Specification.
Track numbering scheme 
Tracks above (top) the active area and below (bottom) each have their own numbering. In both case, the count start from  the active area. This, the top tracks will be numbered by increasing Y and the bottom tracks by decreasing  Y.
Track/Net assignement 
The track/net assignement is deduced from the atomic wiring specifications. It also allows to compute the total number of tracks needed above and below the active area.
 
Atomic Wiring Specification
An atomic wiring specification has the same syntax for either diffusions or gates. It must  not comprise any whitespaces. it is made of the following parts:
The net name to connect to.
Whether the track is above the active area ("t" ) or below ("b" ). The special case ("z" ) means that this element must be left unconnected (is such case possible?).
The number of the track.

Stack Implementation Details
The __setattr__()  and __getattr__  functions have been redefined so that the technological values (rules) can be accessed has normal attributes of the Stack class, in addition to the regular ones. 

Constructor & Destructor Documentation
def __init__ (  self,   device,   NERC,   NIRC)

[API]  Constructor 
param rules The physical rule set. 
Parameters:
device 	The Hurricane AMS device into which the layout will be drawn. 	
NERC 	Number of contact rows in external (first & last) diffusion connectors. 	
NIRC 	Number of contact rows in middle diffusion connectors. param w The width  of every transistor of the stack (aka fingers ). param L The length  of every transistor. param NFs The total number of fingers (dummies includeds). param NDs The number of dummies to put on each side of the stack. 	
References Stack.bImplantLayer, Stack.botTracks, Stack.botWTracks, Stack.bulkNet, Stack.bulks, Stack.device, Stack.dimensioned, Bulk.flags, Stack.flags, Stack.isNmos(), Stack.L, Stack.metaTnb(), Stack.metaTransistors, Stack.NDs, Stack.NERC, Stack.NFs, Stack.NIRC, Stack.tImplantLayer, Stack.topTracks, Stack.topWTracks, Stack.w, Stack.wellLayer, and Stack.wirings.

Member Function Documentation
def setWirings (  self,   wiringSpec)

[API]  Set the Stack wiring specification. 

Parameters:
wiringSpec 	A string defining the connections for the gates and diffusion areas.	
For a comprehensive explanation of the wiring specification, refers to Wiring Specifications . 
References Stack.botTracks, Stack.botTracksNb(), Stack.botWTracks, Stack.bulkNet, Stack.computeDimensions(), Stack.device, Stack.dimensioned, Stack.eDiffMetal1Width, Bulk.flags, Stack.flags, Stack.gatePitch, Stack.getBotTrackY(), Stack.getHorizontalWidth(), Stack.horPitch, Stack.L, Stack.metal1ToGate, Stack.metaTransistors, Stack.sideActiveWidth, Stack.topTracks, Stack.topTracksNb(), Stack.topWTracks, Stack.wirings, and Stack.ypitches.
def computeDimensions (  self)

[internal]  Compute Stack dimensions from the technological rules. 
Internal function.  Perform the computation of:
self.metal1Pitch  
self.minWidth_metal1  
self.metal2Pitch  
self.minWidth_metal2  
self.gatePitch  
self.sideActiveWidth  
self.hTrackDistance  
self.xpitches  
self.ypitches  
self.activeOffsetX  
self.activeOffsetY  
self.boundingBox  
References Stack.activeBox, Stack.activeOffsetX, Stack.activeOffsetY, Stack.bbHeight, Stack.bbWidth, Stack.botWTracks, Stack.boundingBox, Stack.bulks, Stack.bulkWidth, Stack.computeLayoutParasitics(), Stack.computeStressEffect(), Stack.contactDiffPitch, Stack.contactDiffSide, Stack.DGG, Stack.DGI, Stack.dimensioned, Stack.DMCG, Stack.DMCGT, Stack.DMCI, Stack.eDiffMetal1Width, Bulk.flags, Stack.flags, Stack.gatePitch, Stack.gateVia1Pitch, Stack.getBotTrackY(), Stack.getHorizontalWidth(), Stack.getLastTopTrackY(), Stack.horPitch, Stack.hTrackDistance, Stack.iDiffMetal1Width, Stack.isVH, Stack.L, Stack.metal1ToGate, Stack.metal2Pitch, Stack.metal2TechnoPitch, Stack.metal3Pitch, Stack.metaTransistors, Stack.NERC, Stack.NFs, Stack.NIRC, Stack.sideActiveWidth, Stack.tracksNbPitch(), Stack.vBulkDistance, Stack.verPitch, Stack.w, Stack.wire1Width, Stack.wire2Width, Stack.wire3Width, Stack.wirings, Stack.xpitches, and Stack.ypitches.
Referenced by CapacitorUnit.create(), Stack.doLayout(), RoutMatchedCapacitor.route(), and Stack.setWirings().
def doLayout (  self,   bbMode)

[API]  Draw the complete layout. 
Draw the commplete layout of the Stack. 
References Stack.activeOffsetX, Stack.activeOffsetY, Stack.bbWidth, Stack.botTracks, Stack.botWTracks, Stack.boundingBox, Stack.bulkNet, Stack.bulks, Stack.bulkWidth, Stack.computeDimensions(), Stack.contactDiffPitch, Stack.device, Stack.DGG, Stack.DGI, Stack.DMCG, Stack.DMCGT, Stack.DMCI, Stack.drawActive(), Stack.drawGate(), Stack.drawSourceDrain(), Stack.drawWell(), Stack.eDiffMetal1Width, Bulk.flags, Stack.flags, Stack.gatePitch, Stack.gateVia1Pitch, Stack.getBotTrackY(), Stack.getHorizontalAxis(), Stack.getHorizontalWidth(), Stack.getTopTrackY(), Stack.getWiringWidth(), Stack.horPitch, Stack.iDiffMetal1Width, Stack.isBotTrack(), Stack.isVH, Stack.L, Stack.metal1ToGate, Stack.NERC, Stack.NFs, Stack.NIRC, Stack.sideActiveWidth, Stack.tImplantLayer, Stack.topTracks, Stack.topWTracks, Stack.w, Stack.wellLayer, Stack.wire1Width, Stack.wire2Width, Stack.wire3Width, and Stack.wirings.

The documentation for this class was generated from the following file:
stack.py

VerticalRoutingTracks Class Reference

Route two matched capacitors, C1 and C2, drawn in a capacitor matrix. 
Inheritance diagram for VerticalRoutingTracks:
IMAGE

Public Member Functions
def __setStretching__ (self)
Sets vertical stretching value considering spacing between elementary capacitors in the matrix. 
def setRules (self)
Defines technology rules used to draw the layout. 
def drawVRoutingTracks (self, vRoutingTracksLayer)
Iteratively draws vertical routing tracks given the physical layer vRoutingTracksLayer . 

Detailed Description
Route two matched capacitors, C1 and C2, drawn in a capacitor matrix. 
Connections are put in place with reference to a given matching scheme. Elementary capacitor units are connected to horizontal and vertical routing tracks that represent top plates and bottom plates nets of C1 and C2. Supported types of capacitors are Poly-Poly and Metal-Metal. Technologycal rules are provided by 350 nm AMS CMOS technology with three-four metal layers. Metal layers that are used for routeing are placed similarly to horziontal-vertical (HV) symbolic Alliance CAD tool router, where horizontal metal channels are drawn in metal 2 and the vertical ones are in metal 3. Given a matrix of dimensions $ R*C $, the total number of vertical tracks is $ 2C+2 $ equivalent to $ C+1 $ couples, ensuring that every elementary capacitor is positioned between four vertical tracks, two from each side. In fact, every adjacent couple of these tracks represent top plates and bottom plates of C1 or C2 as shown in Figure 1.
An elementary capacitor unit can be a part of C1 or C2 according to the matching scheme. However, to respect common-centroid layout specifications, for C1 and C2 to be equal, the matrix number of colums and number of rows must be both even. Addionnally, the number of elementary capacitors dedicated to C1 must be equal to those dedicated to C2. These two conditions are tested in one of the class methods. An exception is raised if at least one of the two is not respected. 

Member Function Documentation
def __setStretching__ (  self)

Sets vertical stretching value considering spacing between elementary capacitors in the matrix. 

Returns:
stratching value. 
References CapacitorStack.abutmentBox_spacing.
Referenced by RoutMatchedCapacitor.computeHRLayerYCenter(), and VerticalRoutingTracks.drawVRoutingTracks().
def setRules (  self)

Defines technology rules used to draw the layout. 
Some of the rules, namely those describing routeing layers and tracks are applicable for both MIM and PIP capacitors. However, cuts rules are different. 
Remark: All CapacitorStack  class rules are also reloaded in this class. An exception is raised if the entered capacitor type is unsupported. 

Returns:
a dictionary with rules labels as keys and rules content as values. 
References VerticalRoutingTracks.capacitorInstance, CapacitorStack.capacitorsNumber, VerticalRoutingTracks.computeVRTDimensions(), VerticalRoutingTracks.drawVRoutingTracks(), VerticalRoutingTracks.minEnclosure_hRoutingLayer_vRoutingTrack_cut, VerticalRoutingTracks.minEnclosure_hRoutingTrackCut, VerticalRoutingTracks.minimizeVRTs(), VerticalRoutingTracks.minSpacing_hRoutingTrack, RoutMatchedCapacitor.minSpacing_hRoutingTrack, VerticalRoutingTracks.minWidth_hRoutingLayer, VerticalRoutingTracks.minWidth_hRoutingLayer_vRoutingTrack_cut, VerticalRoutingTracks.minWidth_hRoutingTrack, VerticalRoutingTracks.minWidth_hRoutingTrackCut, and CapacitorUnit.setRules().
def drawVRoutingTracks (  self,   vRoutingTracksLayer)

Iteratively draws vertical routing tracks given the physical layer vRoutingTracksLayer . 
Every elementary capacitor is consequently positioned between four routing tracks, two from each side. Each couple of adjacent routeing tracks represent top plate and bottom plate nets of Ci, where i is in [1,2]. As given in Figure 2, capacitor $ C_ij $ with an even j value situated in even columns have and inversely for odd columns numbers. 
References VerticalRoutingTracks.__computeVRTsNumber__(), VerticalRoutingTracks.__findCapIdsToEliminate__(), VerticalRoutingTracks.__findCapIdsToEliminatePerColumn__(), VerticalRoutingTracks.__findUsedCapIdsPerColumn__(), VerticalRoutingTracks.__findVRTsToEliminate__(), VerticalRoutingTracks.__setNetsDistribution__(), VerticalRoutingTracks.__setPlatesDistribution__(), VerticalRoutingTracks.__setStretching__(), VerticalRoutingTracks.__setVRTsDistribution__(), CapacitorUnit.abutmentBox, CapacitorStack.abutmentBox_spacing, VerticalRoutingTracks.capacitorIds, VerticalRoutingTracks.capacitorInstance, CapacitorStack.capacitorsNumber, VerticalRoutingTracks.computeXCenters(), CapacitorStack.dummyElement, CapacitorStack.dummyRing, VerticalRoutingTracks.getVTrackYMax(), VerticalRoutingTracks.getVTrackYMin(), CapacitorUnit.hpitch, RoutMatchedCapacitor.hRoutingTrack_width, VerticalRoutingTracks.hRoutingTrack_width, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, RoutMatchedCapacitor.maximumPosition, VerticalRoutingTracks.maximumPosition, CapacitorUnit.metal2Width, VerticalRoutingTracks.minEnclosure_hRoutingTrackCut, VerticalRoutingTracks.minimizeVRT, RoutMatchedCapacitor.minimumPosition, VerticalRoutingTracks.minimumPosition, VerticalRoutingTracks.minWidth_hRoutingTrack, VerticalRoutingTracks.minWidth_hRoutingTrackCut, CapacitorStack.nets, VerticalRoutingTracks.platesDistribution, CapacitorStack.vRoutingTrack_width, VerticalRoutingTracks.vRoutingTrackDict, RoutMatchedCapacitor.vRoutingTrackDict, VerticalRoutingTracks.vRoutingTrackXCenter, RoutMatchedCapacitor.vRoutingTrackXCenter, VerticalRoutingTracks.vRTsDistribution, RoutMatchedCapacitor.vRTsDistribution, and VerticalRoutingTracks.vRTsToEliminate.
Referenced by VerticalRoutingTracks.setRules().

The documentation for this class was generated from the following file:
capacitorvrtracks.py

Index
INDEX