* Change: To allow multiple tools, and not only Knik, to link and use
FLUTE, remove it from Knik and put it at top level.
Bootsrap must compile this new tool and the library must be
included in all CMakeLists.txt depending on Knik (and soon
Anabatic).
* Change: In Hurricane::CellWidget, set the minimal size to 350 pixels
to fit my normal DPI secondary screen...
* Change: In Hurricane::Error(), reactivate the backtrace generation by
default. Seriously slow down the program each time an Error is to
be constructed.
* Bug: In Analog::Device::preCreate(), check for NULL Technology before
attempting to use it.
* Change: In Hurricane/Analog, remove all '*Arguments*' classes and their
Python interface. It was an obsoleted way of passing devices parameters
to the Python layout generators (located in Oroshi). Now we just get
them straight from the Device with the getParamter() method.
* Change: In CRL::System CTOR, add Python pathes for Oroshi & Karakaze.
* Change: In Oroshi/Python/WIP_*.py layout generator scripts, remove
all uses of the "Arguments". Directly access the parameters through
the device itself. Make the checkCoherency() with identical arguments
as of layout().
* New: Bora tool that performs analog place & route. Based on a slicing
tree representation. It is the thesis work of Eric Lao.
Code beautyfication and some programming cleanup.
* New: Karakaze tool, provide the Python base class AnalogDesign used
to build an analog design. Create/configure devices and assemble
them in a slicing tree.
* Change: In Unicorn/cgt.py, display the stack trace in case of an
ImportError exception as well as for other exceptions.
Add Bora to the set for included tool engines.
* Change: In boostrap, remove support for Chams.
* New: In Hurricane::Technology, added support for DTR rules, UnitRule,
PhysicalRule and TwoLayersPhysicalrule. Added devices descriptors and
models descriptors (for Spice). Spice description is not used yet
but kept anyway in case of future use.
* New: Hurricane::Analog whole library and it's Python interface. This
provides support for transistors, capacitors and resistors. Only
transistor support is fully implemented as of now.
* New: In CRL/python/coriolisInit.py, read configuration files for the
Analog extension (analog.conf & devices.conf). Thoses are optionals
and a simple warning is issued if not found.
Added helpers/AnalogTechno.py DTR loading helper.
Add analog configuration files for 180/scn6m_deep_09.
* New: Oroshi tool that provides actual layout drawing for transistors.
* Change: In all tools supplying documentation, as we use some specific
software to create the doc, they may not be available, or worse, be
and incompatible version. So, by default, we install the files shipped
with the git repository. To force a full doc rebuild, use the "--doc"
flag of ccb.py.
* Bug: In Kite::NegociateWidow and Katana::NegociateWindow, when creating
the TrackSegment from the AutoSegment, we put it on the nearest track
from its current position. But it may happens that the nearest track
is outside the terminal constraint interval (in the case of "nsxlib").
Add the terminal constraint interval check.
This was not affecting the routing result because the segment was
put inside the right interval afterwards. It was only generating
disgraceful transient error messages...
* Change: In all top CMakeLists.txt, force the use of Python 2.7 as
we do not compile against 3.x flavors. Do not use the "EXACT"
flags as it will not recognize 2.7.x versions.
* Change: In Katana::RoutingEvent::Key::Compare(), preliminary
experiments shows that the best sorting order is:
- Lower layer first (i.e. M2 -> M3 -> M4 -> ... )
- Longer segments first.
The later seems to be counter-intuitive. Guess is that placing
the small ones first generate a more important fragmentation of
the big ones. They are placed too early and are difficult to move
afterwards.
Another feature to test is *not* inserting pushed left/right
segments if they are not *already* routed.
* Change: In PyKatanaEngine.runNegociate() now takes a flag argument,
provided through the new PyKatanaFlags exported object.
(doChip.py must be changed accordingly)
* New: In Katana::Configuration, added "katana.profileEventCosts" to
triggers the event's profiling.
* New: In Katana::NegociateWindow::_negociate(), save a profiling
trace of all the events and their priority, separated by metal,
for later analysis (see doChip.py in alliance-check-toolkit).
* New: In Katana::RoutingEvent::Key::Compare(), start implementing
new segment freedom degree functions.
* Change: In Hurricane::Net::_getString(), put a more complete
information about the Net instead of just only it's name.
* Bug: In Katana, reorder the various stages so that they are
executed in the exact same sequence as in "doChip.py" so now
routing in graphic mode and text mode gives exactly the same
results.
* Bug: In Katana::PyKatanaEngine, runGlobalRouter do not take any
argument.
* Bug: In Kite::RoutingEvent::_processNegociate(), on insertion in free
space of a reduced segment (less than one pitch) no insert event
was generated, but the axis was not set to the selected track, leaving
the segment at it's former place.
Now, generate an insert event, but in Kite::Session::_revalidate()
filter them so that reduced segments are not inserted in tracks but
only have their axis set.
Correction also applied on Katana.
* Bug: In Kite::wipeoutRouting(), the removal was incomplete. We need to
remove anchored Contacts, but in a second stage. This is a fragile
workaround as it require that there is only one level of anchoring.
* Bug: In Hurricane::Net::setExternal(), do not perform an UpdateSession
inside this function, it leads to unbearibly slow operation in the
clock-tree plugin.
* Bug: In Kite, backport corrections done in Katana and also relevant
for Kite.
* New: In Cumulus.ChipPlugin.py add support for Python profiling with
cProfile. Disabled under normal operation, but will certainly come in
handy sometimes.
* Bug: In Hurricane, in tstream (Commons.h), in the *template* overload of
operator<<(), do not use the operator<<() of ostream as it will be
looked up in "stage 1" (template definition) and so will miss all the
overloads added later and built over getString<>(). Instead, make use
of getString<>(), which, as another template will be looked up in
"stage 2" (template instanciation) and at that point will have all the
needed template specialisation of getString<>().
We also need to define new stream manipulators to be able to create
a matching template overload not dependant from the implementation.
To avoid name clashes, we prefix a 't'. For now, only 'tsetw()' is
refined.
As a side effect, we cannot directly print bit-fields into the stream,
we must go through an intermediate variable (happens once in AutoContact).
* Change: In Hurricane Commons.h, even when cdebug print nothing, it slow
down the program (three times for Kite!). Create a macro cdebug_log
which calls cdebug *only* if the debug level is active.
* Change: In Hurricane, in Flags add operator overload for "int" type
and not only "unsigned int". Otherwise the compiler complaints about
ambiguous overload when using enum values which are considered as
"int".
Simpler code for the BaseFlags::contains() method.
Added implicit conversion from BaseFlags toward bool type.
* Change: In Hurricane, in Commons, complete replacement of the previous
two trace systems (trace & ltrace) by a stream-based one.
As it is a true object it is much less fragile than the one based
on defines (but maybe a little slower).
Define a reservation table for the trace levels for all the
Coriolis & Chams components.
* Change: All tools, use the new trace system.
* In Katabatic, in GCellConfiguration, added support to 3G_2M2 (generic).
* In Katabatic, in GCellGrid, in getUSide() we were not using the correct
contant set (Constant namespace instead of Kb...) so the size returned
was always X. It doesn't show if the chip is square...
* In Kite, in Track::getBeginIndex(), if the position requested was enclosed
in same net segments, we were going one index too far in the "previous"
direction.
* In Kite, in Track::getOverlapBounds() we where going one index too far
in the "next" direction while computing the "end" index.
* New: In CRL Core, in RoutingLayerGauge, adds a new parameter "obstacleDw".
It represents the distance to add from the *edge* of a blockage segment
to the next *axis* of a routing track. This was previously computed as
the pitch minus the mimimum half wire width. This works if the pitch
is *equal* to the wire width plus the minimal distance (edge to edge).
But if the wire width is less, than it leads to too great a distance
around obstacles, making them bigger than they are. And potentially
blocking everything. To summarize:
before: obstacleDw = pitch - wireWidth/2 (deduced)
after: obstacleDw = explicitly setup, usually:
pitch - max(wireWidth)/2
Modify the Alliance configuration helper and the various kite.conf
file accordingly.
* New: In Kite, in BuildPowerRails, make use of "obstacleDw" to compute
the footprint of a blockage.
* Change: In Hurricane, in DataBase::CellDepths() the recursion stop
criterion must be Cell::isLeaf() and not Cell::isTerminal() as
the second one can be used to hide some levels of hierarchy,
and we want all of them in a blob.
* New: In Hurricane, in Cell, create a new Slaveds relation to keep
track of all the Cells with a slaved abutment box. This work is
incomplete as we do not manage the behavior in case of merge or
Cell destruction or slaving Cells with aready slaveds ones.
Modify Cell::setAbutmentBox() to work in both autonomous and
slaved mode.
* New: In Hurricane, in Net, add a new type of Net: BLOCKAGE this
avoid us to be dependant on the framework pattern recognition.
(change propagated to the Python support)
* New: In CRL Core, in the various drivers, recognize blockage nets
as such and set their type accordingly.
* Change: In CRL, in Toolbox::deleteEmptyNets(), preserve blockage
Nets. This was the cause of crashs in Kite::BuildPowerRails() as
we where trying to use a deleted blockage net...
* Bug: In Hurricane, in NetAlias, do not write NetAlias as a name
but as a type. They were not read back and moreover staying in
the JSON parser stack.
* Bug: In CRL Core, in BlifParser, recognize clocks (Alliance patterns).
* Change: In Cumulus, in RSavePlugin, "kw" manage a new "views" to
specify which views must be saved. Physical by default, but sometimes
we need logical as well. If the design contains uniquified cells,
save the logical view.
In ClockTree, abort the clock tree building if the design has no
top level clock.
* Change: In Katabatic, in GCellTopology, adds 2G_5M1 configuration.
* Bug: Kite, in BuildPowerRails, if we are not in a chip the nets
composing the H-Tree must be protecteds be blockages.
* Bug: In Hurricane, in HApplication, ExceptionWidget ans PyHurricane.h,
forgot to catch the Hurricane::Bug exception which was leading to
terminate() without explanations.
* Change: In Katabatic, In GCellTopology, now support one GCell with
five metal1 terminal of the same net. This unlikely configuration
did appear in the SNX for the first time...
* In Katabatic, in AutoSegment::canMoveUp(), adds the ability to reject
the move up if the density of the depth we comes from is below 0.6
in all the GCells, activated with the KbChecklowDensity flag.
* In Katabatic, In LayerAssign, new method moveUpNetTrunk2() which,
unlike the previous one, move up only the part of the Net trunk
which is connex to the seed segment. Use the canMoveUp with
low density checking to avoid unbalancing higher metal layers.
* In Kite, in SegmentFsm, use the canMoveUp() with low density checking.
* Bug: In Hurricane, in Cell::flattenNets(), addition to the topHyperNets
vector was done *inside* the components loop, resulting in multiple
additions of the same top net. This was leading to the RoutingPads
created multiple times on the same connectors. Hence the conflict in
KiteEngine::protectRoutingPads().
* Change: In Hurricane, in Cell::flattenNets(), do not create RoutingPads
or build rings on already routed Nets. A Net is considered already
routed if it has at least one Segment. This way we avoid Rubbers to
be drawn over routed Nets.
* Change: In Hurricane, in DeepNet, do not build RoutingPads & rings on
already routed Nets (same condition as in Cell::flattenNets()).
* New: In Hurricane, in HyperNet, new collection of all component
occurrences of an HyperNet. May or may not (default) include
components from the leaf cells.
* New: in Katabatic, in AutoSegment, recognize segments that are U-turn.
That is, based on two turn Contacts and going both top or bottom.
* New: In Kite, manage one pitch U-turn by making them diseapear from
the tracks. And make them same-metal when saving. Add a pack stage
to try to compact U-turn.
* Change: In Katabatic, in GCellTopology::doRp_AccessPad(), if the supporting
RoutingPad is big (more than two pitch), do not put the access
contact in the center but on the edge. This is to avoid cut violations
between the VIAs and the matrix of VIAs that may be generated under the
RoutingPad itself.
* Change: In Kite, in TrackSegment destructor, if the legnth of the wire,
without extensions is less than one picth, enlarge it so it encompass
it's source & target VIAs (to avoid notches).
* Bug: In Kite, in Track destructor, the TrackElements where detacheds,
but not deleted, causing a memory link.
* Change: In vlsispad, in Dots, add an enable/disable flag because when printing
into a cmess, it is only the base class ostream which is took into account
as none of it's methods are virtuals (silly me).
* Bug: In Etesian, print into cmess instead of cout and make use of the Dots
enabling feature.
* New: In Katabatic, added AutoContact::migrateConstraintBox() to transfert
constraint from one contact to another.
New flag for AutoContact, CntWeakTerminal for AutoContact which are at
the other of a segment directly connected to a terminal. They may hold
special constraints in case of caged terminals (computed in Kite).
In AutoHorizontal & AutoVertical, in ::_makeDogleg(), transfert flags
and constraints when breaking a segment directly connected to a terminal.
* New: In Kite, in protectCagedTerminals(), uses cross constraint on the
AutoContact opposite to the ContactTerminal (CntWeakTerminal) instead
of moving up one terminal over two consecutives. This is simpler without
degrading the routing quality.
* Change: In Knik, in Vertex, add a "blocked" flag to signal disabled
vertexes in the grid (must not be used by the global router).
Modificate the Graph::getVertex() method so that when a vertex
is geometrically queried, if is a blocked one, return a non-blocked
neighbor. This mechanism is introduced to, at last, prevent the
global router to go *under* the pad in case of a commplete chip.
* New: In Katabatic, in AutoSegment, a new state has been added: "reduced".
A reduced segment is in the same layer as it's perpandiculars.
To be reduced, a segments has to be connected on source & target to
AutoContactTurn, both of the perpandiculars must be of the same layer
(below or above) and it's length must not exceed one pitch in the
perpandicular direction.
To reduce an AutoSegment, call ::reduce() and to revert the state,
call ::raise(). Two associated predicates are associated:
::canReduce() and ::mustRaise().
Note: No two adjacent segments can be reduced at the same time.
* Bug: In Katabatic, in GCellTopology, add a new method ::doRp_AccessPad()
to connect to the pads. Create wiring, fixed and non managed by
Katabatic, to connect the pad connector layer to the lowest routing
layers (depth 1 & 2). The former implementation was sometimes leading
to gaps (sheared contact) that *must not* occurs during the building
stage.
Remark: This bug did put under the light the fact that the initial
wiring must be created without gaps. Gaps are closed by making doglegs
on contacts. But this mechanism could only work when the database if
fully initialised (the cache is up to date). Otherwise various problems
arise, in the canonization process for example.
* New: In Katabatic, in AutoContactTerminal::getNativeConstraintBox(),
when anchored on a RoutingPad, now take account the potential rotation
of the Path's transformation. Here again, for the chip's pads.
* New: In Kite, support for reduced AutoSegment. TrackSegment associateds
to reduced AutoSegment are *not* inserted into track to become
effectively invisibles. When a segment becomes reduced, a TrackEvent
is generated to remove it. Conversely when it is raised a RoutingEvent
is created/rescheduled to insert it. All this is mostly managed inside
the Session::revalidate() method.
* New: In Kite, in KiteEngine::createGlobalGraph(), in case of a chip,
mark all global routing vertexes (Knik) that are under a pad, as blockeds.
* Bug: In Cumulus, in PadsCorona.Side.getAxis(), inversion between X and
Y coordinate of the chip size. Did not show until a non-square chip
was routed (i.e. our MIPS R3000).
* Change: In Stratus1, in st_placement.py add the ClockBuffer class for
backward compatibility with the MIPS32 bench. Have to review this
functionnality coming from the deprecated placeAndroute.py.
In st_instance.py, no longer creates the Plug ring of a Net.
In my opinion it just clutter the display until the P&R is called.
Can re-enable later as an option (in Unicorn).
* Change: In Unicorn, in cgt.py, more reliable way of loading then running
user supplied scripts. Borrowed from alliance-checker-toolkit doChip.py .
* Change: In KiteEngine::wipeoutRouting(), remove only the Contacts
that are *not* anchored. Any other will be indirectly destroyed.
* New: In GraphicKiteEngine, add an encapsulation and a menu for
wipeoutRouting().
* New: In Hurricane, in Cell, no longer create rings of RoutingPads when
flattening the nets. Put that functionnality into a separate method
::createRoutingPadRings().
This allow to perform the Net flattening in Etesian *without*
the rings, which slow it down. Then the rings are created by
Knik/Kite. This also solves the double ring creation when doing
P&R of a complete chip (rings where created twice: in the core
block for Etesian and at chip level for Kite).
* Change: In Etesian, slight beautification of the printed informations.
(psychorigid me)
* New: In Hurricane, dedicated class BaseFlags to wrap a set of flags.
Similar to the Mask class, only with a slightly different semantic.
Encapsulation of <unsigned int>.
Also provide support for the Inspector, to have a human-readable
display of the flags.
* Change: In Hurricane, in Cell, regroup all the flags under a Flags
sub-class of Cell. No more mixing between booleans and bit flags.
(first use of BaseClass).
* In Hurricane, CRL Core & Knik, many small corrections to suppress
annoying warning messages at compile time.
Most noticeably, Bison errors in VstParserGrammar generated by
rules and token with mismatched return value type. This was not
problematic because the badly defined return value where not used.
But still...
* Bug: In CRL Core, in VectorPortMap::VhdlPortMap(), if the connection
was made to *non-contiguous* bits of an otherwise *contiguous* vector,
it was using a span instead of the separate bits. Now check that
bits are contiguous (delta: +1/-1) and the delta do not change of
sign.
* Change: In Etesian & Kite, the Python interface function ::setViewer()
was checking that the argument was indeed a CellViewer, but in text
mode it is None. Now, silently ignore the argument if it cannot be
converted into CellViewer.
* New: In Hurricane, in Collection add simple STL iterator support.
So now the C++11 "for" instruction can be used instead of the
in-house "forEach".
Example:
forEach ( Component*, icomponent, net->getComponents() ) {
cout << (*icomponent) << endl;
}
Become:
for ( Component icomponent : net->getComponents() ) {
cout << icomponent << endl;
}
* New: In Kite, in BuildPowerRails more accurate GCell density computation
under the pad area, to limit the overloaded messages.
* New: In Cumulus, In BlockCorona, remove the vertical METAL3 blockages
and replace them by horizontal blockages completly enclosing the
corona big vias in all layers. This way the I/O wires that goes
through the corona are guided to be straight and do not creates
unsolvable doglegs due to the presence of big vias.
* Change: In Kite & Etesian, small typo: refactor the method
"::wipeOutRouting()" into "::wipeoutRouting()" (indulge me, I'm a
code maniac).
* Bug: In Hurricane, in PyHurricane.h the macro HCATCH was not catching
standard STL exceptions. This was the source of the cryptic message:
"Fatal Python error: Py_EndInterpreter: thread still has a frame"
The Python interpreter was interrupted uncleanly bypassing it's own
exceptions mechanism.
In PyViewer, the Viewer *do not* inherit from a base class (in the
Python export).
* New: In Hurricane, in DbU, compute maximum values (in double) for
grid, lambda & physical (in meter) so now the DbU::toGrid(),
DbU::toLambda() & DbU::toPhysical() methods can check for out of
bound values, and throw an exception.
* Change: In Hurricane, ExceptionWidget::catchAllWrapper() now returns
a boolean, set to <true> if an exception has been catched. Allow
callers to interrupt themselves if a problem has occured.
* Bug: In Kite & Etesian, in the Python wrapper, send a Python exception
if catchAllwrapper() did return true, instead of continuing...
* Change: In Kite & Etesian, adds a setViewer() method (exported in Python)
to use the graphical ExceptionWidget when in graphic mode.
* Bug: In Cumulus, in PadsCorona.py the check for the core vs. chip size
was not returning False when invalid.
* New: In CRL Core, in Vst driver, add a support IEEE VHDL. Inactive for
now as I don't see clearly the policy for selecting it or not.
Remove the code of the old Vst driver.
In Blif parser, check for non-existent models (incomplete or
corrupted Blif file). Found by G. Gouvine.
* New: Added extras file for IDE-like support under Emacs.
* New: In CRL Core, created a LibraryManager widget. It provides a
composite information based on what is present, for each
Alliance library:
1. - A Cell in memory, without Catalog::State.
2. - A Catalog::State, with or whithout the Cell in memory.
3. - The files of the Cell in the librariy's directory.
4. - A file with a format referenced for one of the importers.
File type recognition is based *only* on the file extension,
so it may easily confused. Be careful about what you put in
the library's directory.
One of the big limitation is that it will not display Hurricane
libraries that do not have the AllianceLibrary extension.
This widget is put in a separate library <libmanager>, included
in the default CRLCORE_LIBRARIES.
* Change: In CRL Core, in State (through the loader), now sets the
InMemory flag (event if nobody uses it yet...). Display it in
the state _getString().
In AllianceFramework, new getAllianceLibraries() method.
In CatalogExtension, make the static method "get()" publicly
accessible, for sometimes we want the whole State.
* Bug: In vlsisapd, in Path, the pathcache was not rebuild when it
should, leading to incorrect results.
* New: In vlsisapd, in Path, added a listdir() method to access the
contents of a directory and a stat() method to poll the status
of a file/directory.
Rename the ".string()" method in ".toString()" to avoid
tricky name resolution with std::string, refactor in all the
other tools.
* Change: In Hurricane, in Controller, no longer oversize the fonts
of the table's headers.
* New: In Unicorn, in UnicornGui, integrate LibraryManager.
* New: In Hurricane, In NetAlias & Net, add an AliasList collection to
iterate over all the aliases names (this *not* include the main
net name).
* New: In Hurricane, In Cell, Instance & Net add support for cloning and
uniquification (update documentation).
All Cells that are uniquified from a given model are kept in an
Uniquify relation. This relation allows to get all the clones and
generate unique clone names by adding a "_uXX" suffix.
* Bug: In Hurricane, the Cell::_isFlattenLeaf attribute was not initialized
in the constructor.
* Change: In CRL Core, in AllianceFramework::getCell(), no longer destroy
a partially loaded Cell in case of parser failure, let the incomplete
Cell be.
* New: In CRL Core, in ApParser, if all the instances are placed, sets the
Cell::Placed flag.
* Change: In CRL Core, in BlifParser, complete rewrite of the parser.
Not so good an idea afterwards...
* New: In Etesian, uniquify the design before placing.
* Change: In Kite, display the list of unrouted wired after all other
statistics.
* New: In Hurricane, In Cell, add Placed and Routed flags to know the
state of the Cell.
* Change: In CRL Core, In ApDriver, do not save the RoutingPads as
external connectors if the design is *not* routed (create
conflics on reload with the newly generated RoutingPads).
* Change: In Etesian, set the Placed flag on the Cell.
* Change: In Kite, set the Routed flag on the Cell.
* Change: In Cumulus, in RSavePluginAll, save the layout only if it
has a bounding box.
* New: In Hurricane, In Net & Cell, support for Net aliases names.
Use a structure based on a simple ring of NetAliasHook. The Net
holds a global map, sorted by names of all the aliases of all Nets.
Elements NetAliasesHook of the map are slaves of ring whose master
is an attribute of the Net (it is *not* in the map, as the primary
name of the Net).
In case of merge, the aliases of both Nets are merged and the
name of the merged one become an alias.
The Cell::getNet() looks in both the Net map and the aliases to
find a Net by name.
* Bug: In CRL Core, in coriolisInit.py, reoder the loading of the
configuration files so the real technology is read as early as
possible to set up the <gridsPerLambda> factor before any lambda
is actually computed...
* Bug: In CRL Core, in AcmSigda, do not try to fed the file when it
has failed to be opened. Throw a clean exception instead.
* New: In CRL Core, in Toolbox, add a NamingScheme object to convert
a design into VHDL compliant names (mainly from Blif/Verilog).
This is extensible in any case.
* New: In CRL Core, in BlifParser, slightly more informative warning
messages. Align the loading progress information on the other
parsers.
Add a capability to select which component of the design will
be returned, if there are more than one. Use the "." as separator.
For exemple you can request "Processor.Alu", which will load
the "Alu" component from the design in "Processor.blif".
To be able to save a Blif loaded design, systematically convert
all the name for VHDL compliance, as it is the format used by
the Coriolis native files (vst).
Export the Blif parser to the Python interface.
* New: In Kite, In NegociateWindow, add a counter of the number of
remaining events. Gives an idea of the ETA...
* New: In Unicorn, in cgt.by, add an option to load a Blif design from
the command line.
* New: In Cumulus, new RSave plugin to save both netlist & layout.
Partly redundant with the previous one. Have to better organize
that later.
* Bug: In Hurricane, In CellViewer, pass by a temporary pixmap when
shitfing right (and bottom). We were already using the AutoCopy
buffer for the opposites moves... Seems that the drawPixmap()
may have changed of implementation.
Explanation of the diagonal lines, see QTBUG-31579 that affect
Qt 4.8.5. Temporary work around, force the pen to have a width
of 2 pixels (for _normalPen & _linePen).
* Change: In Hurricane, in CellViewer remove the redraw by whole
strip mechanism (offsetVA).
* New: In Hurricane, In CellViewer::DrawingPLanes add a tracking of
the brush offset to avoid small irregularities at the border of
two separately drawed areas.
* Bug: In Hurricane, in Graphics, display a warning about the
diagonal lines when using Qt 4.8.5.
* New: In VLSISAPD, in Configuration, add a new priority level UserFile
to distinguish between the system configuration files and the user's
configuration files (which take precedence).
* New: In Hurricane, in Script (Python), improve the API to be able
to support Chams (and remove the duplicate capability from it).
Add separate functions to perform the initialize/run(s)/finalize
cycle step by step.
* Change: In CRL Core, rename real technology <hcmos9> to <hcmos9gp>,
it's offcial name from CMP/ST. This is the 130nm.
Move the reading of the symbolic & real technologies names from
coriolisInit.py to helpers.__init__.py, to be shared with
chamsInit.py.
To avoid a clash of names inside of helpers, the two variables
of techno.py are renamed "symbolicTechnology" and "realTechnology".
Move python init system from crlcore/src/crlcore to crlcore/python.
* New: In CRL Core, In Utilities, add site-packages/pharos to the
PYTHONPATH.
* Change: In Kite, move python init system from kite/src/init to
kite/python.
Jean-Paul Chaput
Gabriel Gouvine