* New: In designflow.surelog, support for the Synlig Surelog/UHDM plugin
for Yosys.
* Fix: In designflow.svase, remove the transient file "slang-args.txt".
* Change: In designflow.yosys, remove the direct SystemVerilog support
that is delegated to Surelog and just load the resulting UHDM.
Merge with yosysnp and automatically detect if we can load the
Python plugin or go through a script.
* New: In designflow.yosys, add support to load SystemVerilog with the
synlig plugin (CHIPS Alliance).
Integrate back the "non-Python" version of the task. Now switch
automatically between Python & Non-Python based on the availability
of the plugin. Also select between "yosys" & "yowasp-yosys".
* Change: In svase & sv2v, suppress the requirement of the *first*
dependency file to be used as the default target. Now use the
"top module" argument.