Commit Graph

3 Commits

Author SHA1 Message Date
Jean-Paul Chaput 8f69fa668d More trials on SystemVerilog to Verilog translators.
* New: In designflow.surelog, support for the Synlig Surelog/UHDM plugin
    for Yosys.
* Fix: In designflow.svase, remove the transient file "slang-args.txt".
* Change: In designflow.yosys, remove the direct SystemVerilog support
    that is delegated to Surelog and just load the resulting UHDM.
      Merge with yosysnp and automatically detect if we can load the
    Python plugin or go through a script.
2023-09-19 16:01:00 +02:00
Jean-Paul Chaput 4398770432 Add SystemVerilog support to designflow.yosys. Merge with YosysNp.
* New: In designflow.yosys, add support to load SystemVerilog with the
    synlig plugin (CHIPS Alliance).
      Integrate back the "non-Python" version of the task. Now switch
    automatically between Python & Non-Python based on the availability
    of the plugin. Also select between "yosys" & "yowasp-yosys".
* Change: In svase & sv2v, suppress the requirement of the *first*
    dependency file to be used as the default target. Now use the
    "top module" argument.
2023-09-16 18:12:10 +02:00
Jean-Paul Chaput 662b0124b8 Add partial support for SVase and sv2v to the DesignFlow. 2023-08-31 16:14:51 +02:00