* Bug: In cumulus/plugins.chip.powerplane, while building the connexion
from the corona border to the root of the HTree, the horizontal
wire at the top was too close from the border causing a minimal
spacing error in the DRC. Now put two tracks of distance.
* New: In Track::repair(), the gapset was used to *close* same-net gaps
is now alos used to restore minimal spacing between different nets.
Seems to be not fully working yet.
* In KatanaEngine:
- Former situation:
Each RoutingEvent did store the routing stage it was in. And it
was misnamed "mode".
- New organization:
The routing stage is stored in KatanaEngine itself. It can be
accessed through a proxy in Session.
* Change: In DataNegociate::update(), when in Realign stage and computing
non-preferred perpnadicular routing *do not* expand of one pitch
outside the RoutingPad range.
* Change: In AutoSegment::canMoveUp(), hard code for FlexLib a track
reserve of one when trying to move up.
In FlexLib, the router promotes too easily METAL2 towards METAL4,
clogging the higher level. So we end up with the METAL2 level
under-saturated and the METAL4 over saturated, leading to routing
failures.
Now we assume that there is "one track less available" in METAL4.
As for now, solves the problem for LibreSOC.
* New: In CRM::GdsSteam::makeExternals(), now take into accounts Pad
for Net external components. Also delete the original components
after creating the copy in the right Net.
So now the PLL terminals are correctly seen.
* Bug: In NetBuilderHV::_do_xG_1PinM2(), for METAL2 pins on the EAST
side, we were computing the track from the XMax position of the
GCell. Now, with complete discoupling of the routing pitches and
GCell size, this is most of the time false.
Replace with a true computation of the last track of routing
area.
* Bug: In TrackSegment::getFreeInterval(), if, for whatever reason,
a discrepency happens between the TrackSegment and the Track,
that is the _track fields point to a *wrong* Track. Then the
index lookup will fail (Track::npos), so return an all-span
interval instead of trying to expand it and crash (out of
bound).
* Bug: In NetBuilderHV::_do_xG_1PinM2(), when the M2 pin is on the *east*
side and there are three globals, we must swap htee1 & htee2.
Otherwise, we the SW/NE contacts do not have the right numbers
of free segments attach.
* New: In AnabaticEngine::cleanupGlobal(), check that no global component
is left behind, sure sign that the global to detailed building went
wrong.
* Bug: In Etesian::HFNS::Cluster, all the created nets were systematically
created in the IN direction, which is obviously wrong for the driver.
Now Slice::raddTransPlug() accept a third argument stating if we are
creating a driver or a sink. Direction of the net is now combining
and can be IN, OUT or sometimes INOUT.
The VHDL files where reflecting that problem and made GHDL choke.
* Change: In Etesian::HFNS::Cluster, prefix the instance name by "cmpt_"
so it doesn't clash with the signal name in VHDL.
* Bug: In Etesian::Placement::Slice::fillHole(), do not use the xmin
previous bound, but pitch it (by excess). Insert ties *only* if
they completely fit in the free space.
This bug was showing *between* two SRAMs side-by-side, a column
of tie was inserted...
* Bug: In cumulus/plugins.block.block.py, always import Python modules
using the exact same path. Otherwise the module may get imported
twice and static variables are duplicated, generating a big mess.
This was causing problem for the LUT in macro.py, and got SRAMs
blocks encapsulated twice.
* New: In cumulus/plugins.block.block.Block.addPlaceHolder(), create
a "place holder" instance over a given area to prevent the placer
from using it. Allow to make space reservation.
* New: In cumulus/plugins.block.configuration.BlockConf, copy the
toXPitch() and toYSlice() methods from spare in order to share
them between modules. Still have to remove some other local copies.
* New: In cumulus/plugins.block.spare.QuadTree, keep a list of all
the X centers of the partitionned areas. For yse by the power lines.
* New: In cumulus/plugins.chip.chip, move doPowerLayout() call from
doChipFloorplan() to doConnectCore(), this is to delay the call
until *after* the spare QuadTree has been created and we can
align the power lines to the centers of the QuadTree.
* New: In cumulus/plugins.chip.pads.Corona.doPowerLayout(), if a
spare QuadTree has been created, align the power lines on the
X center of the leaf areas. This is a cheap way to avoid DRC
errors between the power BigVias and the wires from the various
clock trees (on METAL5).
* New: In cumulus/plugins.block.macro, add an ad-hoc patch for Staf's
SRAMs. The blockage areas are slightly too narrow. We enlarge
them by one pitch.
* New: In AnabaticEngine::_gutAnabatic(), perform progessive compaction
of segment of null length.
CAUTION: Reduced segments *may* not be null length segments.
They are "less or equal" than one perpandicular pitch and
can have their layer put into the perpandicular one.
They non-null one *must* be excluded for the compaction.
Null segments are compacted starting from the one connecteds to
non-null length segments. This is to avoid the compaction starting
in the middle of a whole set of zero-segments that will block further
compaction.
This behavior was causing "zero-length" segment on orphaned layers
that were causing minumal area DRC errors.
* Change: AutoSegment::canReduce() is modified so it now takes a flag
argument to tell it to look for collapisble zero-length segments.
* New: AutoSegment::getNonReduceds(): returns the number of non-zero
length segments connecteds to the current one.
* Change: In AutoSegment::reduceDoglegLayer(), use the perpandicular
width of the routing layer instead of the regular (parallel) one.
This was causing DRC errors.
* Change: In AutoSegment::canReduce(), no longer allow short METAL2
connected only to VIA12 to be reduced in METAL1, as we do not
control the METAL1 level of layers. This problem started to
show when connecting to diodes (antenna).
Should get rid of METAL1 DRC violations.
* New: In Track::repair(), short gaps between segments of the same
nets where occuring and being not detected. This was causing
DRC minimal distance violations. Now, fuse the segments when
they are too close. Done by extenting the duSource of the
rightmost one to the leftlost one.
Create ancillary class GapSet to manage the gaps of the
various segment of the same net.
* Bug: In CRL::GdsParser, the PLL was using copies of the standard cell
with the same name. And unfortunately, they where found *before*
the FlexLib one when using DataBase::getCell(). As their I/O where
wrong it was leading to a massive netlist connexion corruption in
blif2vst.
To avoid that, any Cell created by the GDS parser is now prefixed
by "gds_".
* Change: In CRL::GdsStream CTOR, report when the file cannot be opened
instead of saying that the GDS file is corrupted (misleading).
* Change: In AutoSegment::isMiddleStack(), reject configurations where
we have a Tee in the same direction as the segment. That is, (HTee + H)
or (VTee + V). It is unlikely that the two segments of the tee will
be of null size.
When a segment is placed only once (which is to say it is nerver ripped
up) it can sometimes end-up in a non-optimal place. We now add a stage
in Katana where each segment is "re-placed" in order to maximise
alignment on it's neighbor. This is a new stage added to both
RoutingEvent and NegociateWidow. Segments are replaced *only* in free
space, they will not ripup *other* segments, except for their own
perpandiculars. We exclude from re-placement globals (unlikely to move)
and segment that have reduced perpandiculars which *must* not be elongated
and potentially raised.
Add a new katana setting to enable/disable the realign stage (enabled
by default:
- "katana.runRealignStage" ( = True )
* Change: In Cumulus/plupins.chip.pads.Side, in some case (LibreSOCIOPads),
when not put side by side, the I/O pads must be separated by a
minimal distance.
Introduce the new configuration parameter:
cfg.chip.minPadSpacing
Disabled if zero or non-defined.
Fix NWELL DRC errors for TSMC.
* Change: In AutoSegment::isMiddlestack(), we where previously only
detecting (turn+turn) or (turn+terminal) topologies. This was
too restrictive. Added (terminal+XTee) when the tee is perpandicular
to the segment, for example horizontal + VTee.
Fix minimal area DRC error in METAL2 for TSMC.
* Bug: In Vhdl::VhdlPortmap::toVhdlPortMap(), when the mapped names
are part of a vector, but *not* in the "downto" direction,
unvectorize anyway. In the component declarations, vectors are
always in "downto" order, so they must also be mapped in that
order.
* Bug: In CRL::BlifParser::newOne() & newZero(), we have to create
signal names different from instance names for VHDL compliance.
This is complementary to what is done in blif2vst.
No completely satisfied with that. Should find a more generic
way to do it in the future.
* Change: In Hurricane::NetAlias, store additional data in NetAliasName,
the external status of the former Net. When a Net::merge() is
performed, we must keep track of whether the merged (destroyed)
one was external and keep that information.
Add NetAliasHook::isExternal() & NetAliasHook::setExternal()
virtual methods.
* Change: In Net::getNet() add a new optional argument to allow the
search of the net name in *internal* aliases. Otherwise only the
aliases tagged as *external* will be searched.
It was a bug that, when looking for a Plug master net by name
we got an homonymous internal net. In that case we must only
look for net that are (or where) part of the interface.
* New: In Vhdl::VectorSignal, when a vector contains only one bit,
unvectorize it, like when it is non-contiguous (we use the
isCountiguous() method to carry that information).
* New: In Vhdl::VhdlEntity, Catalog::State and NamingScheme, added
a flag UniquifyUpperCase to uniquify the names in uppercases.
In case of a clash with the same name in lowercase.
Prepend 'u' before all previously uppercased letter. For
example 'VexRiscV' becomes 'uvexuriscuv' (urgh!).
The Catalog flags is exported to Python for use by the blif2vst
script.
* Change: In BlifParser, Model::newOne() and Model::newZero(), return
a new gate each time it is called instead of making just one for
each Model. This way, if two outside nets are connected to one
or zero they do not get merged (should work, but will be less
clear).
* Bug: In BlifParser, Model::connectSubckts(), when looking for the
master net in the instances models (by name), limit the search
to the *external* aliases names.
* Change: In NamingScheme::vlogTovhdl(), reactivate the removal of
two consecutive '_'.
* Change: In cumulus/bin/blif2vst.py, prefix the master cells
(i.e. components) with 'cmpt_' to avoid clash names with signals
in VHDL.
We use the segments extensions (dxTarget & dyTarget) to enlarge if
needed the segments. This new implementation is completely at
Anabatic level and should not be seen (i.e. managed) at Katana level.
* Change: In AutoHorizontal & AutoVertical, change the semantic of
getSourceU() and getTargetU(). formerly they where the end
position of the segment (with extension included), now they
gives the position of the anchor contacts, that is the axis
of the perpandiculars.
* New: AutoSegment::getLength() is still a proxy toward the
Segment::getLength() which returns the length of segment with
dxSource & dxTarget. We introduce a getAnchoredlength()
which returns the length between the centers of the S/T
anchors. That is axis to axis.
This is this length which is now used througout Anabatic.
* New: In AutoSegment::_extentionCaps, add a fourth item to hold
the segment minimal length (to respect minimal area given
the wire width).
* New: In AutoSegment::getExtensionCap(), if the segment has
a non-zero S/T extension, returns it instead of the S/T
contact extension *if it is greated*. The check of the
extension can be disabled by the Flag::NoSegExt flag.
* Change: In AutoSegment::isMiddleStack(), security check on
the presence of source and targets. More accurate detection
of perpandicular in "same layer" with a non-zero length,
So the area is OK, even with a short segment.
* New: AutoSegment::expandToMinLength(), check if a segment is
under the minimal length and expand it if need be by playing
with the dxTarget & dxSource. Tag minimal segments with the
AutoSegment::SegAtMinArea flag. Also try to keep the segment
*inside* it's former (supposedly wider) interval.
* New: AutoSegment::unexpandToMinLength(), to be called on a
formerly minimal sized segment which as grown up. Reset
it's S/T extensions to zero and unset the flag SegAtMinArea.
* Change: In AutoHorizontal::updateOrient(), when the extension
are non-zero, also swap them if needed, to keep the exact
footprint of the segment.
* New: In AutoSegment::revalidate(), check that the segment
respect the minimal length (area), and expand it if needed.
Conversely, if the segment has grown up from a minimal
length state, reset it's extensions to zero.
* Change: In Anabatic::Session::revalidate(), invalidateds
segments are now sorted in such a way that the "middle stack"
ones are revalidateds last. Not recall 100% why...
* New: In Katana::TrackCost, add a computation of the free interval
length we are into (if any). Not used yet, keep it for future
use.
* Change: In KatanaEngine::finalizeLayout(), remove the call to
segments minimum area protection. It is now obsoleted by the
new implementation in Anabatic.
* Change: In Track::check(), call the minimum size/area checker
Track::checkMinArea().
* New: In AutoSegment::getExtensionCap(), when a routing layer has a
minimal area defined, compute the minimal wire length (given it's
width). Then, for segments identified as "MiddleStack" (local
with turns at each end towards opposite layers), if their length
is below minimal, return a longer extention cap.
This may be optimized because with this, the segment extension
is symmetric on both side while it could be made assymetric.
* Bug: In Cumulus/plugins.block.configuration.GaugeConf.rpAcces(), start
building the stack of contacts + short segments straps from the
layer of the RoutingPad and *not* from the first layer of the
RoutinhGauge.
* Bug: In Cumulus/plugins.block.configuration.GaugeConf.setStackPosition(),
Only align in the RoutingLayer gauge direction of the top layer of
the stack. For example, METAL2(H) will be y aligned or METAL3(V)
will be x aligned.
* Bug: In Cumulus/plugins.chip.powerplane.Builder._connectClock(),
forgot to call expandMinArea() on the pinRp contact stack.
* Change: In CRL::GdsStream::operator<<(Cell*), external components needs
to be exported twice. First as "METALx.pin" to signal an external
component (and give it's name). And second as a "normal" component
in "METALx". If the METALx part is forgotten, the "Vendor" StreamIn
will not see the METALx.pin as something physical so f***g gaps appears
in the wiring. And furthermore, if the TEXT label is above it, the
name of the net goes away...
* Bug: In EtesianEngine::toHurricane(), when looping over the AB of all the
FIXED instances occurrences, we where excluding contained AB instead of
merging them...
* Change: In Cumulus/plugins.block.spares, allow the QuadTree to have
only *some* of it's four childs (BL, TL, TR, BR).
Modify QuandTree.getLeafUnder() so when there is no leaf under
the point, due to an incomplete tree, we get the closer leaf.
Leaf are suppressed when their center points (where the buffers
are to be put) are under a FIXED Instance (that is, an opaque block).
Those opaque blocks (or macro blocks) must be put *on the periphery*
of the design, because the closer they got to the center, the larger
the chunks of QuadTree that are removeds.
* Change: In Cumulus/plugins.block.clocktree, based on the spare
QuadTree changes, can now build a clock-tree with some of the
leaf missing. Should find a way to compensate for the missing
leaf wires & buffer (dummies).
* New: In Cumulus/plugins.block.matrix.RegisterMatrix, based on pattern
matching the output of DFF, allow to rebuild and place a matrix of
DFF constituting a RAM.
It finally proven not useful because it is a too naive approach.
Intermediate gates (buf_x2) must be found too. Most of the control
signals have more than 20 sinks so gets splitted by HFNS and lastly,
we would want the decoder to be integrated too, but they are not
regulars.
The right way to do it is to create a generator that build it
then expose it in a way nMigen can understand (not the other way
around, nMigen -> Yosys).
Jean-Paul Chaput
Luke Kenneth Casson Leighton