Commit Graph

7 Commits

Author SHA1 Message Date
Jean-Paul Chaput bd3984a313 Correctly manage clock net isolateds from the main clock.
* New: In Bootstrap, in ccb.py, check if cmake is installed and issue
    a warning, if not.
* New: In Hurricane, added Cell::getDeepNet() to search for a deepnet
    given a path and a leaf net. This method is slow and must not be
    used too often. Introduced for Kite::BuildPowerRails().
* Change: In CRL Core, in cmos/alliance.conf, modify the clock name
    pattern to match the sub-clock signals in the datapath operators.
* Bug: In Etesian, do not blindly reset the top cell abutment-box.
    Do it only if it's empty, otherwise keep it.
* Bug: In Kite, in buildPowerRails(), in getRootNet() the management
    of clock nets was incomplete. The case of unrouted clock nets
    that where not connected to the top core clock net, like the
    one in the datapath registers was faulty. They were partly
    recognized as unrouteds and partly as blockage generating a
    routing deadlock: routage impossible due to blockage generated
    from itself...
* New: In Stratus1, add a buildModel() utility function to automate
    the model generation and allow a call by the model name (string).
* Change: In Unicorn, in cgt.py, display the Alliance environement.
2015-02-25 22:22:16 +01:00
Jean-Paul Chaput 1f9ae36554 Bug fixes for MOSIS SCMOS_DEEP support.
* Change: In Hurricane, the NetRoutingProperty is moved into Hurricane
    from Katabatic. Needed for Knik to be able to access thoses
    informations.
* Change: In Hurricane, in RoutingPad::setOnBestComponent(), now in
    case of identical area, select the component of lowest id.
    This should not be needed if the component ordering was fully
    deterministic as it should be (will investigate later).
      This is to ensure that the choosen component is always the
    same, especially between save/load of a global routing.
* Bug: In Katabatic, in AutoContactHTee::updateTopology(), invalidate
    the segments only if the topology is valid (no NULL in the
    cached segments).
* Bug: In Katabatic, in GCellTopology::construct(), throw an error
    if the topology is bad instead of trying to continue (and core
    dump later... ).
* Bug: In Kite, in BuildPowerRails, distinguish the name of the master
    net in the pad (for vddi, vssi, vdde, vsse, ck, cki & cko) and the
    name of the net in the *chip* netlist. Must use the later to make
    comparison as they may differs.
* Change: In Knik, in save/load solution, exclude nets that are not
    globally routed by Knik. That is which NetRoutingProperty is not
    *Automatic*.
* Bug: In Cumulus, in chip.BlockPower take account of the layer
    width extention to sligthy shrink the connector thus avoiding a
    notch with standart cell in some cases.
* Change: In Cumulus, in chip.ClockTree disable the use of fixed Steiner
    trees for the leaf clocks, as it seems overconstrained for the
    router. First move was to lower them in M2/M3 (instead of M3/M4)
    but that was not sufficent.
* New: In Cumulus, RSavePlugin for recursively saving a physical
    hierarchy.
* New: In documentation, first embryo for RDS file. Should have been
    in Alliance git, but I prefer to keep newest doc in Coriolis.
2014-09-21 16:44:37 +02:00
Jean-Paul Chaput a3963716b1 Correction in plugins to support msxlib compatible pads.
* New: In CRL Core, in helpers & alliance.conf, set and read a "PAD"
    variable to define the pad model name extension ("px" for "sxlib
    and "pxr" for vsxlib, this is provisional).
* New: In CRL Core, in plugin.conf, add parameters to define the name
    of used for power & clock supply. We may remove the extention in
    the future (to be more coherent with the previous modification).
* New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no
    longer place the accessing contact *at the center* of the
    RoutingPad. It works under sxlib because buffers & registers all
    have same size terminals. But this is not true under vsxlib,
    leading to misaligned contacts & wires. Now systematically place
    on the slice midlle track (maybe with one pitch above or below).
      This is still very weak as we do not check if the terminal
    reach were the contact is being put. Has to be strenthened in
    the future.
* New: In Cumulus, in chip.Configuration.ChipConf, read the new
    clock & power pad parameters.
* Change: In Isobar (and all other Python wrappers), uses PyLong instead
    of PyInt for DbU conversions. In PyHurricane argument converter,
    automatically check for both PyLong and then PyInt.
* Change: In Cumulus, in chip.PadsCorona, more accurate error message
    in case of discrepency in global net connections (i.e. no net
    of the same name in instance model and instance model owner.
* Change: In Kite, in BuildPowerRails, when looking up at the pads
    model name to find "pck_" or "pvddeck_", do not compare the
    extension part. But we still use hard-coded stem pad names,
    maybe we shouldn't.
* Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there
    was a loop in the search of the best N/E initial RoutingPad.
* Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect
    RoutingPads of fixed nets, they are already through the
    BuildPowerRails stage (and it's causing scary overlap warning
    messages).
* Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create
    deep-plug when the core is flat (not sub-modules). All the new
    nets are at core level.
* Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure
    that the core is aligned on the GCell grid (i.e. the slice
    grid of the overall chip).
* Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop
    while looking for the bigger N-E RoutingPad. Forgot to decrement
    the index...
2014-09-13 17:45:30 +02:00
Jean-Paul Chaput 206309ddd9 No longer directly use C++ exported symbols in configuration files.
* Change: In CRL Core, in Alliance.py, no longer requires the
    configuration file to uses symbols from CRL.Environment or
    CRL.RoutingLayerGauge. This way the <alliance.conf> file can be
    parsed by a different parser.
      In <alliance.conf>, for the various technologies, make uses
    of the new C++ independent constants.
* New: In CRL Core, in helpers/__init__.py, provide a "Dots" class
    (rewrite the C++ one in pure Python).
2014-08-03 16:25:26 +02:00
Jean-Paul Chaput 0fab6087fa Start of Alliance/Python encapsulation layer.
* New: In Cumulus, new Alliance.py module (*not* a plugin) providing
    an encapsulation for Alliance command line tools. The other main
    feature is that it provides a "Makefile like" behavior. Based on
    the command dependencies a DAG is contructed, then a static
    ordering of the commands. Commands are then executed to rebuild
    outdated target.
      The Alliance environment supplied to the commands is read from
    the Coriolis configuration file <alliance.conf>.
      For this first evaluation version, only <boom>, <boog> and
    <loon> support are provided.
      It still not clear how to encapsulate the Coriolis tools in
    the same way.
* Change: In CRL Core, in helpers/__init__.py, change the way the static
    initialization (module) is done. All the commands are put inside
    a "staticInitialization()" function, which is then explicitly
    called by others. This is a better solution agains *no* or *twice*
    initialization. Modificate <coriolisInit.py> accordingly (as
    <Alliance.py> from Cumulus.
2014-07-27 16:23:27 +02:00
Jean-Paul Chaput 8bc7bd38db Add a common/ to share the trunk of symbolic technologies configurations.
In CRL Core configuration files, "display.conf", "patterns.conf" and
"technology.conf" share most of their code. So that common part is put
into "common/" and sourced from the final configuration file.
Update the documentation according the the new initialization scheme.
2014-05-22 00:13:17 +02:00
Jean-Paul Chaput 4439d3a142 Added support for multiple symbolic+real technology in configuration.
In CRL Core, the layout of the files under "/coriolis2/etc" changes.
Instead of having them directly under "etc", they are now replicated,
in subdirectories. Each subdirectory having the name of the associated
symbolic or real technology (they are kept separated). We have, for
now:
* etc/cmos/    : symbolic, the Alliance original one.
* etc/vsc200/  : symbolic, for G. Petley vsclib.
* etc/hcmos9/  : real, generic fake (130nm).
To tell which pair (symbolic,real) technologies must be used we create
a *second* (sigh) configuration file "coriolis2_techno.conf", and it's
hidden counterpart in the user's account, to set it up. It needs to be
separate because it is read as early as possible and select which set
of configuration files would be read.

Also add support up to METAL8 and POLY2 in CRL core and it's Alliance
parser/drivers.
2014-05-21 14:50:22 +02:00