Note: The previous strategy was not fully coherent in chip mode.
Everything added, net and components must be added at
corona level and not separated between corona and core.
* New: In cumulus/plugins/block.configuration, new FeedsConf object
to handle the feeds and provide a filling area helper.
* New: In cumulus/plugins/block.spares.removeUnusedbuffers() to
remove unused buffers in the pools and replace them by feedthrough.
* Change: In cumulus/plugins.block.spares, unify coordinate/slice
computation. If we are in chip mode, the coordinates are
expressed in the corona *but* aligned on the slices of the
*core* model.
* Change: In cumulus/plugins.block.Block.rsave(), add the '_r' suffix
to the routed cells.
* Change: In cumulus/plugins.clocktree.ClockTree, when in chip mode
create everything at corona level. Also forgot to set type of
clock subnet as clock.
Note: The port is not complete. Integration of LKCL patches will
follow shortly.
* Change: In cumulus/plugins/alpha/block, more simple inheritance
scheme. Use classic inheritance instead of @classdecorator.
BlockConf (renamed from BlockState) now inherit from GaugeConf,
Double inheritance tree, for Block/Chip and BlockConf/ChipConf.
Allow an uniform syntax for configuration parameters.
* New: In cumulus/plugins/alpha/chip, port of the chip plugin and
integrate with the block plugin. It is now a derived class of
Block. ChipConf is also a derived from BlockConf.
Obsolete "./coriolis2/ioring.py", all informations are given
though the ChipConf state class.
* New: In cumulus/plugins/alpha/core2chip, only Alliance/pxlib is
ported yet.
Jean-Paul Chaput