* New: In KatanaEngine::digitalInit(), when using a "VH,2RL" style,
protect all RoutingPads of each net, because unlike "2RL+" style,
the standard cell RoutingPads are not in a "below" layer only
used inside the cell, but on the V layer. So the area of the RP,
even if not fully used to connect, must be protected.
* Change: In NegociateOverlapCost(), when computing cost from a fixed
or blockage, do not set the infinite flag if it's the *same* net.
* New: In KatanaEngine::protectRoutingPads(), add a new "flags" argument
to pass on whether we want to protect the the RP candidates or just
the non-used ones.
* Change: In protectRoutingpad(), change the formula (again) to compute
the berth to give to a fixed segment... Should really try to
summarize all the case.
* Change: In TrackFixedSegment::getNet(), no longer return the blockage
net if the real net is tagged as clock.
* Bug: In Anabatic::AutoHorizontal::_makeDogleg(), the up/down flag
was incorrectly computed when the RoutingGauge RL where not the
lower one. This was leading to making doglegs in non-routable
layers (but present in the gauge for other purposes).
* New: In Katana::Configuration, added option:
"cfg.katana.disableStackedVias" (default to false), so the router
do not stack VIAs on top of each other.
* Bug: In NegociateWindow::loadRoutingPads(), create TrackMarkers using
the right depth when the gauge starts with non-routable ones.
* New: In Track::addOverlapCost(), when disableStackedVias is active,
uses the markers from the below terminals to tag the cost as
"infinite", so the track *cannot* be used by the marker's net
owner. Can be refined by checking that we are not at a segment's
end but will do for now.
* New: In cumulus/block.bigvia, add a getBoundingBox() method.
* New: In cumulus/block.configuration.GaugeConf.rpAccess(),
add a vertical strap segment in case the RP is not high enough to
accomodate the potential offset of the contact.
In case of gauge with only two routing layers, if the RP
is vertically accessed, do not put a VIA12 but just a METAL2
contact (there will be *no* turn).
* Change: In cumulus/chip.CoreWire.drawWire(), the wire at *chip level*
going to the pad was shrunk of 3 pitch when *not* in the preferred
routing direction. Removing it as it creates gaps in some cases.
This was likely needed for a specific kind of I/O pad so should
be re-enabled on targeted cases in the future.
* Change: In cumulus/chip.corona.VerticalRail, manage in a smarter way
the conflicts when a rail is accessed from both sides overlapping
on an Y position. That is, from the supply I/O pads *and* from the
*core* supply lines.
Formerly, we just didn't connect the core power line, which was
a mistake potentially leaving power rails unconnected (it it did
occur on both sides).
Also checks if the conflict really arise, that is, the power lines
are both on top or bottom.
* Change: In cumulus/chip.pads.Side._placePad(), manage I/O pads with
a bottom left corner of abutment box *not* at (0,0). Argh!
* Bug: In cumulus/chip.pads, create the filler pad instances in the
chip, not in the corona.
* Change: In Etesian::BloatChannel, when two DFFs are side by side, if
they are not separated by at least one pitch, the track avoid
mechanism will not be able to work. Hence the minimal one pitch.
* Change: In cumulus/plugins.chip.configuration, do not add an extra
slice height to the minHCorona & minVCorona. Now seems a bit overkill
on small chips.
* New: In CRL::RoutingLayerGauge, two new types of gauge are supported:
- Unusable : just do nothing with it, but the layer is stacked.
- BottomPowersupply : can be used for supply routing only, and
is *below* the normal routing layers (instead of on top as
usual).
Both new types must be *below* the real routing layers.
* New: In CRL::RoutingGauge, add a new attribute "firstRoutingLayer"
to give the index (depth) of the first layer usable for routing.
(not Unusable and not BottomPowerSupply)
* New: In Anabatic::Session & Anabatic::NetBuilder, in order to build
the initial wiring, provides (Session) and use (NetBuilder) the
new functions:
- getBuildRoutingLayer(depth)
- getBuildContactLayer(depth)
Thoses functions takes into account (offset) the unusable layers
so depth 0 is the first usable routing layer, and so on.
* New: In Technology, in order to support symbolic technology on top
of a real technology using non-generic layer names, it comes in
handy to be able to define layer alias names. Generic *real*
layer names could be defined as alias over the technology
specific ones. Then, we can build the symbolic layers upon
the generic names (so *that* part of the init code can be
shared between techs).
Adds Technology::addLayerAlias()
The semantic of Technology::getLayer() changes a little, it
return the techno layer associtated to the name *or* the
aliased name.
* Bug: In Technology::_addPhysicalRule(), in case of a rule redefinition,
we were using it's name *after* the deletion of the rule object.
Nasty crash.
Improve the error message by giving the name of the conflicting
rule.
* In CRL/helpers.analogtechno, add an addDevice() function to load
analogic devices descriptors (copied from the old init system).
* In CRL/ApParser, if an exception is catched, tells in which file and
line it did occur.
* In Oroshi/dtr.Rules, add a translation step to get the rule names
from the technology. From generic names to actual technology
layer names.
Add some documentation.
* In Oroshi/stack.Stack, get the layers names through dtr.Rules to get
the layers names translated.
* Bug: In NetBuilder::construct(), the xG_xM1 topologies where wrongly
redirected towards xG_1M1, so only one M1 was connected, all others
left floating.
Now direct them towards xG_xM1_xM3.
* Bug: In NetBuilderHybridVH, activate topology management for 2G_1M1.
* Change: In Etesian::SubSlice::getUsedVTracks(), now take blockages
into account for used vertical tracks.
* Bug: In Etesian::SubSlice::avoidTrack(), right free interval for
shifting was wrongly computed, effectively allowing *any* shift.
This was creating cells overlap!
* New: In Hurricane::BasicLayer & Layer, establish a two way link
between the blockage layer and routing layer. Now we can access
the routing layer from the blockage.
* New: In NetBuilderHybridVH::_do_1G_xM1_1PinM1(), added configuration
to manage pins on the north/south sides for VH,2RL.
* Bug: In NetBuilderHybridVH::doRp_xG_xM1_xM3(), correct misplaced
vertical creation (buildind invalid topologies).
* New: EtesianEngine::toColoquinte(), display histograms of the cells
widths (in pitch) before and after bloating to get a better feeling
of the behavior.
* New: In EtesianEngine, add support for track avoidance. Portions of
tracks to avoid are specified by a Box, which should flat and on
the axis of the request track. This feature is used by the H-Tree
to clear the vertical tracks under the tree from any terminal.
* New: In Etesian::Area, Slice and SubSlice, add support for track
avoidance. Exported to the Python wrapper.
* New: SubSlice::getUsedVTracks() to get a set of tracks blocked by
the cell.
* New: SubSlice::trackAvoid(), shift left/rigth the cell under the
requested vertical track. Try only to move the cell under the
track and not it's neighbor, so it assume that there is sufficient
space left or right of the cell.
* Bug: In cumulus/plugins.block.configuration.BlockConf, the Cfg
parameters may be read too early from the Cfg space into the
various sub-conf objects (like FeedsConf). Delay the reading
of the parameters in a _postInit() functions.
Modify Block and CoreToChip to call _postInit().
* New: In cumulus/plugins.block.configuration.BlockConf._loadRoutingGauge,
allow the cell gauge name to differ from the routing gauge name.
* New: In cumulus/plugins.block.configuration.FeedsConf, allow to
select the default feed to be used with 'etesian.defaultFeed'
parameter.
* New: In cumulus/plugins.block.spares.BufferPool, allow to control
whether or not we want tie to either side of the pool.
(for latch up).
* New: In cumulus/plugins.block.HTree._connectLeaf(), add support
for track avoidance.
* Bug: In cumulus/plugins.block.HTree._connectLeaf(), the TL2 contact,
the one on the *top* auxiliary buffer seemed to have been badly
positioned until now (too low, not using tl2Y).
This is strange because it should have caused disconnections,
but I didn't see it in the wiring and the regressions tests didn't
flag anything wrong. Still a bit weird and worrying.
Robert Taylor
Jean-Paul Chaput