Commit Graph

7 Commits

Author SHA1 Message Date
Jean-Paul Chaput 8d4fdf3471 TrackCost clean support for symmetric and wide segments.
* New: In Katana::TrackCost, the TrackElement and it's optional
    symmetric are now kept as attribute of a TrackCost. The cost
    is completly computed inside the constructor.
      TrackCost now support any mix of symmetric event and wide
    segments.
      The cost is now computed by adding directly to the current
    one instead of creating secondaries that are merged afterwards.
    As a consequence, remove all copy construction and merge
    capabilities.
      All the various methods used to compute the cost are renamed
    "addOverlapcost()" in all the various related objects.
      As a reminder, the overal cost method call is as follow:
        1. TrackCost constructor on a TrackElement.
           2. Call TrackElement::addOverlapcost()
              3. For all Track under the TrackElement, call
                 Track::addOverlapCost()
                 4. For all other TrackElement intersecting with
                    the overlap interval call:
                    TrackElement::incOverlapCost()
                    5. The callback overlap function for segments
                       is called (defined in NegociateWidow).
      Don't confuse:
      - TrackElement::addOverlapCost(), which compute the cost of
          inserting the segment inside a track (or a set of).
      - TrackElement::incOverlapCost(), which compute the cost of
          overlaping with this already inserted segment. It is the
          other way around of the previous one.
* Change: In Katana::SegmentFsm, use a vector of pointer to TrackCost
    instead of an object to avoid copy construction.
2017-06-10 12:27:25 +02:00
Jean-Paul Chaput 1b7bd9de36 Happy new year 2016! 2016-01-21 00:41:19 +01:00
Jean-Paul Chaput 6ecdaf2539 More accurate routing guiding under a block corona.
* New: In Kite, in BuildPowerRails more accurate GCell density computation
    under the pad area, to limit the overloaded messages.
* New: In Cumulus, In BlockCorona, remove the vertical METAL3 blockages
    and replace them by horizontal blockages completly enclosing the
    corona big vias in all layers. This way the I/O wires that goes
    through the corona are guided to be straight and do not creates
    unsolvable doglegs due to the presence of big vias.
* Change: In Kite & Etesian, small typo: refactor the method
    "::wipeOutRouting()" into "::wipeoutRouting()" (indulge me, I'm a
    code maniac).
2015-06-06 18:22:48 +02:00
Jean-Paul Chaput 5dc60415e7 Happy new year 2015! 2015-03-17 16:56:55 +01:00
Jean-Paul Chaput 6d366a08bc Etesian integration with Chip & ClockTree plugins.
* New: In Hurricane, in DebugSession, add a new method to activate the
    trace inconditionally with a certain level.
* New: In Hurricane, in HyperNet, allow copy construction as there is
    no reason to disallow it and we need it now.
* New: In Hurricane, in Cell::flattenNets(), add a new option to prevent
    the flattening of the clock net(s). For more safety perform the
    DeepNet creation *outside* the Collection loop.
* Bug: In Hurricane, in Cell_HyperNetRootNetOccurrences, skip the
    DeepNets because they are the result of another flattening operation.
* New: In Isobar, in PyBasicLayer, export C++ method getBlockageLayer().
* New: In Isobar, in PyRoutingGauge, export C++ method getLayerPitch(),
    needed by Cumulus plugins.
* New: In Etesian, EtesianEngine::findYSpin() to look for the Y orientation
    if some cells are already placed. Typically the buffers of a clock
    tree.
      Pass the correct orienation to row_compatible_orientation().
      Do not try to add feeds in the ISPD05 benchmarks. For now the
    benchmarks are detected through their names (unreliable).
* Change: In Knik, in KnikEngine::initGlobalRouting(), allow the clock
    to be routed as an ordinary signal when the clock tree is not
    used.
* New: In Kite, in BuildPowerRails, management & detection for the
    pre-routed clock.
      In KiteEngine constructor, early initialization of the blockage
    net to avoid later troubles in BuildPowerRails.
* New: In Cumulus, in ChipPlugin, add support for Etesian plus new
    configuration parameter 'clockTree.placerEngine' to select between
    Mauka and Etesian.
* New: In Cumulus, in BlockCorona, add blockages in the vertical sides
    in the vertical layer to prevent the router to use the vertical
    tracks in under the prower lines (for example, blockage in M3
    with power line M5).
      In Cumulus, in ChipConf add attribute to access the blockage net.
* New: In Cumulus, when the clock tree is disabled, do not generate
    the last rail around the block (the clock rail).
* Bug: In Cumulus, in ChipConf use the clock pad to guess the clock
    signals and *not* the power pad.
      Add more meaningful error messages if a pad global signal is
    not found (implicit connexion by name).
* Bug: In Cumulus, in ClockTree, compute correctly the cells Y spin,
    that is *from the bottom of the cell AB* (not from 'zero').
2015-02-24 13:13:17 +01:00
Jean-Paul Chaput fb4a7457a1 First basic version of ClockTree & Chip plugins.
* New: In Cumulus, first versions of the ClockTree and Chip plugins.
    Clock Tree plugin:
    - It is strongly advised to use have 4 metal routing layers for the
      tree to work. Otherwise, problems can arise with the detailed
      routing (fully obstructed terminals).
    - H-Tree can only be build (for now) for design with a form factor
      between 0.5 an 2.
    - The tree is created at the block top-level and only the leafs are
      trans-hierarchically created on the instances/models. The new
      cell with a clock tree, along with all it's sub-models is created
      with a "_clocked" suffix.
    - Leaf cells are connected through a simple Minimum Steiner Tree.
    - Shorts are avoided by a systematic shift of the wires according
      to their kind. No wire must pre-exist. When used as a sub-module
      of "chip" the wires cannot be moved. When created on a block,
      the wires can be loaded in the detailed router as manual global
      router.
    Chip Plugin:
    - Perform the pad placement and corona creation. Replacement at
      last of the clunky code from Wu Yifei.
    - Relies on a Python configuration file '<design>_chip.py' with
      a "chip" dictionnary.
2014-08-15 19:05:27 +02:00
Jean-Paul Chaput 25e82fc701 Complete replacement of the Chip placement Python scripts.
Finally get rid of the demonic code from Wu Yifei...
* New: In Isobar, added encapsulation of Interval (don't know how have
    forgotten it for so long).
* Change: In Isobar, In PyLayer, new PyLink_LayerDerived() function to
    create/link the C++ object to the correct derived class and not the
    base one (PyLayer) which then prevent to use the specialized methods.
    Must replace PyLink_Layer() througout all the code.
* Change: In Isobar, in PyPoint the "setX()" & "setY()" methods where
    still capitalized.
* Change: In Isobar, in PyQuery, complete the exportation of the C++
    interface. remove the code belonging to a more "boost" way of
    building the Python interface (will do that in a far future).
* New: In CRL Core, In PyAllianceFramework, export isPad() method.
* Change: In Unicorn, in unicornInit.py, protect the loading of each
    single plugin by a "try" / "except" clause to the failing of one
    plugins do not stop the loading of the next one.
      Pass the same dictionnary argument to unicornHook() as for
    ScripMain(), this is more uniform this way.
* New: In Cumulus, complete replacement of the chip placement scripts
    from Wu Yifei (at last!). The clock-tree integration is still to
    be done.
________________________________________________________________________
2014-07-21 13:18:34 +02:00