Commit Graph

1980 Commits

Author SHA1 Message Date
Jean-Paul Chaput 39567add06 Annoying errors in init script under RHEL6 (bad devtoolset2 check). 2015-06-12 15:22:16 +02:00
Jean-Paul Chaput 5d3d7343b0 socInstaller.py has now all it's features. 2015-06-11 23:48:57 +02:00
Jean-Paul Chaput 6743072048 SoC super-builder socInstaller.py for network & nightly builds.
* New: In <bootstrap>, socInstaller.py, a script to perform standard
    SoC network installations and nighltly builds. Clone/update the
    git repositories (Coriolis & Chams), build binaries and docs
    in two passes, then send a mail report.
2015-06-11 18:51:10 +02:00
Jean-Paul Chaput 4bf5cf74b4 Policy CMP0022 for CMake. Forgotten library in Unicorn link. 2015-06-11 18:01:39 +02:00
Jean-Paul Chaput d151038de9 Typo in Coloquinte library name. 2015-06-10 18:38:10 +02:00
Jean-Paul Chaput e2fcfcb699 Rationalization of Cell's flags. Compilation warnings hunt.
* New: In Hurricane, dedicated class BaseFlags to wrap a set of flags.
    Similar to the Mask class, only with a slightly different semantic.
    Encapsulation of <unsigned int>.
      Also provide support for the Inspector, to have a human-readable
    display of the flags.
* Change: In Hurricane, in Cell, regroup all the flags under a Flags
    sub-class of Cell. No more mixing between booleans and bit flags.
    (first use of BaseClass).
* In Hurricane, CRL Core & Knik, many small corrections to suppress
    annoying warning messages at compile time.
      Most noticeably, Bison errors in VstParserGrammar generated by
    rules and token with mismatched return value type. This was not
    problematic because the badly defined return value where not used.
    But still...
2015-06-10 15:49:58 +02:00
Jean-Paul Chaput 701487247d Bug in VHDL portmap. Too strict checking in Kite & Etesian ::setViewer().
* Bug: In CRL Core, in VectorPortMap::VhdlPortMap(), if the connection
    was made to *non-contiguous* bits of an otherwise *contiguous* vector,
    it was using a span instead of the separate bits. Now check that
    bits are contiguous (delta: +1/-1) and the delta do not change of
    sign.
* Change: In Etesian & Kite, the Python interface function ::setViewer()
    was checking that the argument was indeed a CellViewer, but in text
    mode it is None. Now, silently ignore the argument if it cannot be
    converted into CellViewer.
2015-06-08 12:01:32 +02:00
Jean-Paul Chaput 51043df640 Merge "collections" branch from <github> (G. Gouvine).
* New: In Hurricane, in Collection add simple STL iterator support.
    So now the C++11 "for" instruction can be used instead of the
    in-house "forEach".
      Example:
         forEach ( Component*, icomponent, net->getComponents() ) {
           cout << (*icomponent) << endl;
         }
      Become:
         for ( Component icomponent : net->getComponents() ) {
           cout << icomponent << endl;
         }
2015-06-08 11:51:09 +02:00
Jean-Paul Chaput 2906d90b04 Re-activate the LEF/DEF symbolic exporter (for benchmarking).
* Change: In bootstrap, in FindLEFDEF.cmake, adds my personal path where
    the LEF/DEF libraries are to be found (~jpc/oa/lefdef/5.7-s038/).
* Change: In CRL Core, in LEF/DEF exporters, use the default routing
    gauge and cell gauge, instead of systematically requiring "sxlib".
      IMPORTANT: In order to build a *shared* library including the
    *static* LEF/DEF libraries, those libraries, even if static, must
    be build with the "-fPIC" flag (otherwise the compiler complains).
    I have done so on my 64 bit build of LEF/DEF, but it's a completly
    *local* patch. You may have to do it manually on your installations.
2015-06-07 14:12:00 +02:00
Jean-Paul Chaput 9ac199f11b Change in policy for duplicate libraries.
* Change: In CRL Core, replace duplicated libraries, even when performing
    a Append/Prepend operation. Also correct a bug in library name
    uniquification, event if it's no used. The policy in cas of duplicate
    libraries is not completly clear for me, still.
2015-06-07 11:05:01 +02:00
Jean-Paul Chaput 445104eaf7 Start to support high DPI screen (> 192dpi).
* New: In Hurricane, in Graphics, add a new static method ::isHighDpi()
    which returns true if the DPI is greater than 192. A "normal" screen
    is typically 96dpi, we sets the trigger at twice that value.
      Then in all the widgets with size settings, we uses that method to
    select the more appropriate size.
2015-06-06 18:41:28 +02:00
Jean-Paul Chaput 6ecdaf2539 More accurate routing guiding under a block corona.
* New: In Kite, in BuildPowerRails more accurate GCell density computation
    under the pad area, to limit the overloaded messages.
* New: In Cumulus, In BlockCorona, remove the vertical METAL3 blockages
    and replace them by horizontal blockages completly enclosing the
    corona big vias in all layers. This way the I/O wires that goes
    through the corona are guided to be straight and do not creates
    unsolvable doglegs due to the presence of big vias.
* Change: In Kite & Etesian, small typo: refactor the method
    "::wipeOutRouting()" into "::wipeoutRouting()" (indulge me, I'm a
    code maniac).
2015-06-06 18:22:48 +02:00
Gabriel Gouvine fd994e51fe Merged bug fixes and improvements
* Steiner tree topology
* Install path detection
* Additional Alliance layer
* Blif parser presented first
2015-06-02 10:36:21 +02:00
Gabriel Gouvine 47847d046e Merge branch 'Placement_verif' into collections
* Now verifies that the cell is not already placed
2015-06-02 10:33:37 +02:00
Gabriel Gouvine 63b1f5abb0 Basic STL-compliant collections
Ported etesian and kite to use them
2015-05-28 14:20:32 +02:00
Jean-Paul Chaput 20ac9080d6 Do not generate IEEE VHDL when driving vst files (silly me). 2015-05-21 14:55:38 +02:00
Gabriel Gouvine 56603ddc0d Etesian now verifies that the cell is not placed yet 2015-05-21 14:10:37 +02:00
Jean-Paul Chaput b1ca43fd57 Do not expand Clock Tree wires, may creates DRC violations. 2015-05-21 13:05:08 +02:00
Jean-Paul Chaput f8a72288aa Better handling of exceptions between C++ & Python. Misc. checks.
* Bug: In Hurricane, in PyHurricane.h the macro HCATCH was not catching
    standard STL exceptions. This was the source of the cryptic message:
        "Fatal Python error: Py_EndInterpreter: thread still has a frame"
    The Python interpreter was interrupted uncleanly bypassing it's own
    exceptions mechanism.
      In PyViewer, the Viewer *do not* inherit from a base class (in the
    Python export).
* New: In Hurricane, in DbU, compute maximum values (in double) for
    grid, lambda & physical (in meter) so now the DbU::toGrid(),
    DbU::toLambda() & DbU::toPhysical() methods can check for out of
    bound values, and throw an exception.
* Change: In Hurricane, ExceptionWidget::catchAllWrapper() now returns
    a boolean, set to <true> if an exception has been catched. Allow
    callers to interrupt themselves if a problem has occured.
* Bug: In Kite & Etesian, in the Python wrapper, send a Python exception
    if catchAllwrapper() did return true, instead of continuing...
* Change: In Kite & Etesian, adds a setViewer() method (exported in Python)
    to use the graphical ExceptionWidget when in graphic mode.
* Bug: In Cumulus, in PadsCorona.py the check for the core vs. chip size
    was not returning False when invalid.
* New: In CRL Core, in Vst driver, add a support IEEE VHDL. Inactive for
    now as I don't see clearly the policy for selecting it or not.
      Remove the code of the old Vst driver.
      In Blif parser, check for non-existent models (incomplete or
    corrupted Blif file). Found by G. Gouvine.
* New: Added extras file for IDE-like support under Emacs.
2015-05-20 14:03:59 +02:00
Jean-Paul Chaput 909f86b4fc Added support for IEEE VHDL in the Vst parser (std_logic).
* New: In CRL Core, in VstParser, support IEEE VHDL, with tokens
    <library> and <use>. If "use IEEE.std_logic_1164.ALL" is present
    the file will be considered to be IEEE compliant.
      To be precise, the parser now support any mix between Alliance
    and IEEE VHDL. So you can have both <std_logic> and <wor_bit>
    in the same file, but it is unclean to do that.
      The two extensions ".vhd" & ".vhdl" are supported.
      The drivers still always creates Alliance VHDL.
2015-05-10 17:16:00 +02:00
Jean-Paul Chaput 1b79ef75c9 Added a top level Makefile to encapsulate the ./bootsrap/ccb.py call. 2015-05-09 23:16:36 +02:00
Jean-Paul Chaput a2d4f01ca3 New Library Manager Widget. Access with Tools menu or CTRL+M.
* New: In CRL Core, created a LibraryManager widget. It provides a
    composite information based on what is present, for each
    Alliance library:
    1. - A Cell in memory, without Catalog::State.
    2. - A Catalog::State, with or whithout the Cell in memory.
    3. - The files of the Cell in the librariy's directory.
    4. - A file with a format referenced for one of the importers.
      File type recognition is based *only* on the file extension,
    so it may easily confused. Be careful about what you put in
    the library's directory.
      One of the big limitation is that it will not display Hurricane
    libraries that do not have the AllianceLibrary extension.
      This widget is put in a separate library <libmanager>, included
    in the default CRLCORE_LIBRARIES.
* Change: In CRL Core, in State (through the loader), now sets the
    InMemory flag (event if nobody uses it yet...). Display it in
    the state _getString().
      In AllianceFramework, new getAllianceLibraries() method.
      In CatalogExtension, make the static method "get()" publicly
    accessible, for sometimes we want the whole State.
* Bug: In vlsisapd, in Path, the pathcache was not rebuild when it
    should, leading to incorrect results.
* New: In vlsisapd, in Path, added a listdir() method to access the
    contents of a directory and a stat() method to poll the status
    of a file/directory.
      Rename the ".string()" method in ".toString()" to avoid
    tricky name resolution with std::string, refactor in all the
    other tools.
* Change: In Hurricane, in Controller, no longer oversize the fonts
    of the table's headers.
* New: In Unicorn, in UnicornGui, integrate LibraryManager.
2015-05-09 17:03:17 +02:00
Gabriel Gouvine 82873289f6 Improvements for Steiner trees
* Fixed a bug when calling vertical topology computation
* Now export a horizontal topology function for routers
2015-05-06 16:09:50 +02:00
Gabriel Gouvine 1cda835a48 Detection of the install path for 64 bits distros using /usr/lib 2015-05-03 21:10:42 +02:00
Gabriel Gouvine dc0485935d Better error messages
* Error messages are more explicit in Ap and Blif parsers
* Warns when not using tie cells
* New layer synonym in ApParser for easier format conversion
* Blif import is now on top
2015-05-02 22:10:42 +02:00
Jean-Paul Chaput 06e5e3060c Complete rewrite of the VHDL (Vst) driver. True handling of vectors.
* Bug: In Hurricane, in NetAlias, bad Record construction of the _next
    field.
* New: In CRL Core, in VstDriver complete replacement of the old Vst
    driver. Needed cleaner architecture to manage correctly files
    importeds through the Blif parser, which are Verilog like.
      It is build as an extension trough property and is not kept
    in sync with the Cell. So it's use should be transient only.
* Change: In CRL Core, in NamingScheme forgot to change '.' (dot)
    forbidden character into '_'.
* Change: In Cumulus, in the RSave plugins, remove the VHDL extensions
    after saving.
2015-05-02 18:39:35 +02:00
Jean-Paul Chaput 479429e12d Support for .gates and .mlatch in Blif. Ap parser beautifying. 2015-04-29 10:41:43 +02:00
Jean-Paul Chaput 693c05cf32 Added README and detection of 64 bits using /lib. 2015-04-25 18:27:04 +02:00
Jean-Paul Chaput 32c547bc02 Merge remote-tracking branch 'github/documentation' into devel 2015-04-25 17:26:35 +02:00
Jean-Paul Chaput 731d435a35 Merge the routing-driven version of Etesian (github/RoutingDriven) 2015-04-25 17:24:53 +02:00
Jean-Paul Chaput 770b1fbbbc Support for Uniquification. Rewrite of the Blif parser.
* New: In Hurricane, In NetAlias & Net, add an AliasList collection to
    iterate over all the aliases names (this *not* include the main
    net name).
* New: In Hurricane, In Cell, Instance & Net add support for cloning and
    uniquification (update documentation).
      All Cells that are uniquified from a given model are kept in an
    Uniquify relation. This relation allows to get all the clones and
    generate unique clone names by adding a "_uXX" suffix.
* Bug: In Hurricane, the Cell::_isFlattenLeaf attribute was not initialized
    in the constructor.
* Change: In CRL Core, in AllianceFramework::getCell(), no longer destroy
    a partially loaded Cell in case of parser failure, let the incomplete
    Cell be.
* New: In CRL Core, in ApParser, if all the instances are placed, sets the
    Cell::Placed flag.
* Change: In CRL Core, in BlifParser, complete rewrite of the parser.
    Not so good an idea afterwards...
* New: In Etesian, uniquify the design before placing.
* Change: In Kite, display the list of unrouted wired after all other
    statistics.
2015-04-25 16:52:18 +02:00
Gabriel Gouvine 233a2af3d3 Changes to the documentation + README file
* README file with basic instructions
* Updated the prerequisites
* More information for synthesis with Yosys
2015-04-24 14:48:56 +02:00
Gabriel Gouvine 4b628baa17 Added support for OpenMP in Coloquinte 2015-04-23 18:02:00 +02:00
Gabriel Gouvine bded70971e Taking into account the configuration flag + wipeout routing function 2015-04-23 16:14:06 +02:00
Gabriel Gouvine 524b27451e Wiping the routing is possible!! 2015-04-23 15:16:53 +02:00
Gabriel Gouvine 3f182f1cee Basic routing-driven placement 2015-04-21 14:54:24 +02:00
Gabriel Gouvine 6a6def8252 Cleanup to enable routing-driven placement 2015-04-20 15:29:40 +02:00
Gabriel Gouvine ef671cb944 Initial draft for routing-driven placement
* Uses density restrictions rather than cell inflation
* Will fail brutally if the congestion is too high; does not attempt to balance the densities
2015-04-20 14:14:41 +02:00
Gabriel Gouvine 6f0bc2ecb0 Split the placement routine
* Separate global and detailed placement
* Options provided by the main routine
2015-04-19 09:40:53 +02:00
Jean-Paul Chaput 4023481da3 Add a state to Cell to know if is placed and/or routed.
* New: In Hurricane, In Cell, add Placed and Routed flags to know the
    state of the Cell.
* Change: In CRL Core, In ApDriver, do not save the RoutingPads as
    external connectors if the design is *not* routed (create
    conflics on reload with the newly generated RoutingPads).
* Change: In Etesian, set the Placed flag on the Cell.
* Change: In Kite, set the Routed flag on the Cell.
* Change: In Cumulus, in RSavePluginAll, save the layout only if it
    has a bounding box.
2015-04-16 16:52:33 +02:00
Jean-Paul Chaput ef9936e87c Support for Net alias names. Blif parser enhancements.
* New: In Hurricane, In Net & Cell, support for Net aliases names.
    Use a structure based on a simple ring of NetAliasHook. The Net
    holds a global map, sorted by names of all the aliases of all Nets.
    Elements NetAliasesHook of the map are slaves of ring whose master
    is an attribute of the Net (it is *not* in the map, as the primary
    name of the Net).
      In case of merge, the aliases of both Nets are merged and the
    name of the merged one become an alias.
      The Cell::getNet() looks in both the Net map and the aliases to
    find a Net by name.
* Bug: In CRL Core, in coriolisInit.py, reoder the loading of the
    configuration files so the real technology is read as early as
    possible to set up the <gridsPerLambda> factor before any lambda
    is actually computed...
* Bug: In CRL Core, in AcmSigda, do not try to fed the file when it
    has failed to be opened. Throw a clean exception instead.
* New: In CRL Core, in Toolbox, add a NamingScheme object to convert
    a design into VHDL compliant names (mainly from Blif/Verilog).
    This is extensible in any case.
* New: In CRL Core, in BlifParser, slightly more informative warning
    messages. Align the loading progress information on the other
    parsers.
      Add a capability to select which component of the design will
    be returned, if there are more than one. Use the "." as separator.
    For exemple you can request "Processor.Alu", which will load
    the "Alu" component from the design in "Processor.blif".
      To be able to save a Blif loaded design, systematically convert
    all the name for VHDL compliance, as it is the format used by
    the Coriolis native files (vst).
      Export the Blif parser to the Python interface.
* New: In Kite, In NegociateWindow, add a counter of the number of
    remaining events. Gives an idea of the ETA...
* New: In Unicorn, in cgt.by, add an option to load a Blif design from
    the command line.
* New: In Cumulus, new RSave plugin to save both netlist & layout.
    Partly redundant with the previous one. Have to better organize
    that later.
2015-04-16 15:40:02 +02:00
Jean-Paul Chaput 2cbb072e6c Merge branch 'github/Blif', fast blif parser. 2015-04-13 18:55:06 +02:00
Jean-Paul Chaput db60fe0aa6 New coriolis launcher. Configuration files cleanup.
* Change: In CRL Core, simplify the loading sequence. The technology,
    both symbolic and real is now loaded directly from coriolisInit.py
    and not through the Alliance loader. This was a leftover from the
    time configuration was in XML. Remove others traces of XML loading.
      Remove SYMB_TECHNO_NAME, REAL_TECHNO_NAME & DISPLAY from the Alliance
    environement, as they was no longer used.
      Note that technology *still* need to be loader *after* Alliance
    framework has been initialized.
      Gauge information is moved from <alliance.conf> to <kite.conf>.
* Bug: In Coloquinte, in optimization_subproblems.cxx static variables
    must not be inlined. Generate a problem when linking in debug mode
    (seems the symbol gets optimised out).
* Bug: In Katabatic, in Grid::getGCell(), when the coordinate is *outside*
    the area, do not try to find a GCell, directly return NULL.
* New: In Unicorn, create a generic command launcher named "coriolis" which
    automatically take cares of all environement setup, then run a command
    by default, it's <cgt>, but it can be anything. For example: <zsh>.
2015-04-13 18:54:09 +02:00
Gabriel Gouvine 575b6c923a Performance improvements for the BLIF parser
Got rid of streams
2015-04-13 17:38:51 +02:00
Gabriel Gouvine d7f9e5cb87 Handling aliases of non-instantiated nets
For example $true and $false in Yosys
2015-04-13 16:49:06 +02:00
Gabriel Gouvine 7d5338c9be Support for aliases defined with .names construct 2015-04-13 14:13:03 +02:00
Gabriel Gouvine 4035a6cb46 Supports several models in a Blif file 2015-04-12 16:24:29 +02:00
Jean-Paul Chaput bacea5214c Adapt the rpm automated build system of bootstrap (pass 2)
* Change: coriolis2.spec.in, Makefile.package and Builder/ccb now support
    RHEL6, RHEL7 & Fedora.
* Change: In Bootstrap, added a flag to activate compilation with
    openmp.
2015-04-09 22:45:48 +02:00
Jean-Paul Chaput cdfdccb19d Import Coloquinte as a Coriolis tool (merge from github/coloquinte). 2015-04-08 17:13:50 +02:00
Jean-Paul Chaput 1625b16d4c Adapt the rpm automated build system of bootstrap (pass 2) 2015-04-08 17:13:24 +02:00