* New: In CRL Core, in helpers & alliance.conf, set and read a "PAD"
variable to define the pad model name extension ("px" for "sxlib
and "pxr" for vsxlib, this is provisional).
* New: In CRL Core, in plugin.conf, add parameters to define the name
of used for power & clock supply. We may remove the extention in
the future (to be more coherent with the previous modification).
* New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no
longer place the accessing contact *at the center* of the
RoutingPad. It works under sxlib because buffers & registers all
have same size terminals. But this is not true under vsxlib,
leading to misaligned contacts & wires. Now systematically place
on the slice midlle track (maybe with one pitch above or below).
This is still very weak as we do not check if the terminal
reach were the contact is being put. Has to be strenthened in
the future.
* New: In Cumulus, in chip.Configuration.ChipConf, read the new
clock & power pad parameters.
* Change: In Isobar (and all other Python wrappers), uses PyLong instead
of PyInt for DbU conversions. In PyHurricane argument converter,
automatically check for both PyLong and then PyInt.
* Change: In Cumulus, in chip.PadsCorona, more accurate error message
in case of discrepency in global net connections (i.e. no net
of the same name in instance model and instance model owner.
* Change: In Kite, in BuildPowerRails, when looking up at the pads
model name to find "pck_" or "pvddeck_", do not compare the
extension part. But we still use hard-coded stem pad names,
maybe we shouldn't.
* Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there
was a loop in the search of the best N/E initial RoutingPad.
* Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect
RoutingPads of fixed nets, they are already through the
BuildPowerRails stage (and it's causing scary overlap warning
messages).
* Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create
deep-plug when the core is flat (not sub-modules). All the new
nets are at core level.
* Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure
that the core is aligned on the GCell grid (i.e. the slice
grid of the overall chip).
* Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop
while looking for the bigger N-E RoutingPad. Forgot to decrement
the index...
* Bug: In ClockTree plugin, only the logical view of the clock buffer
was loaded, so no external components where found on the I/O nets.
The external components are loaded only when the *physical* view
is loaded. Didn't show on sxlib because the buffer was fulled
loaded *before* running the ClockTree.
* Bug: In PyHurricane, in the various LocatorNextMethod() macros,
sometimes an empty collection can be returned by Hurricane
(GenericCollection()), which has a NULL locator. So check
if the locator is *not* NULL before trying to access it...
* Change: In Chip, more accurate error messages related to the clock
detecttion.
* New: In ClockTree plugin, select the name of the buffer cell through
configuration (parameter: "clockTree.buffer"), and guess the I/O
name of this buffer automatically.
Put configuration parameters in plugin.conf and not mauka.conf.
Bug: strangely triggers a coredump in components collection
when used with <vsxlib>. Some debug printing still active until
that is solved.
* New: In Chip plugin, make the size and numbers of the block rails
configuration parameters (in plugin.conf).
* New: In Cumulus, first versions of the ClockTree and Chip plugins.
Clock Tree plugin:
- It is strongly advised to use have 4 metal routing layers for the
tree to work. Otherwise, problems can arise with the detailed
routing (fully obstructed terminals).
- H-Tree can only be build (for now) for design with a form factor
between 0.5 an 2.
- The tree is created at the block top-level and only the leafs are
trans-hierarchically created on the instances/models. The new
cell with a clock tree, along with all it's sub-models is created
with a "_clocked" suffix.
- Leaf cells are connected through a simple Minimum Steiner Tree.
- Shorts are avoided by a systematic shift of the wires according
to their kind. No wire must pre-exist. When used as a sub-module
of "chip" the wires cannot be moved. When created on a block,
the wires can be loaded in the detailed router as manual global
router.
Chip Plugin:
- Perform the pad placement and corona creation. Replacement at
last of the clunky code from Wu Yifei.
- Relies on a Python configuration file '<design>_chip.py' with
a "chip" dictionnary.
Finally get rid of the demonic code from Wu Yifei...
* New: In Isobar, added encapsulation of Interval (don't know how have
forgotten it for so long).
* Change: In Isobar, In PyLayer, new PyLink_LayerDerived() function to
create/link the C++ object to the correct derived class and not the
base one (PyLayer) which then prevent to use the specialized methods.
Must replace PyLink_Layer() througout all the code.
* Change: In Isobar, in PyPoint the "setX()" & "setY()" methods where
still capitalized.
* Change: In Isobar, in PyQuery, complete the exportation of the C++
interface. remove the code belonging to a more "boost" way of
building the Python interface (will do that in a far future).
* New: In CRL Core, In PyAllianceFramework, export isPad() method.
* Change: In Unicorn, in unicornInit.py, protect the loading of each
single plugin by a "try" / "except" clause to the failing of one
plugins do not stop the loading of the next one.
Pass the same dictionnary argument to unicornHook() as for
ScripMain(), this is more uniform this way.
* New: In Cumulus, complete replacement of the chip placement scripts
from Wu Yifei (at last!). The clock-tree integration is still to
be done.
________________________________________________________________________
Jean-Paul Chaput