Protections diodes may not be able to play their role if they are
separated from their cluster by upper level layers (METAL4/METAL5).
This seems not to diminish the total number of diodes.
* New: In Anabatic::NetData, add a set of non move up segments in
the object. To tag global wires that are part of a cluster.
* New: In Anabatic::AutoSegment, add support for a SegNoMoveUp
flag. This flag is propagated through _makeDogleg() .
Used in ::canMoveUp() and ::canPivotUp().
* New: In Anabatic::NetBuilder, add NetData to the attributes so
we can extract the NoMoveUp infomation given by the antenna
protect stage.
* New: In NetBuilderHV::_do_globalSegment(), lookup NoMoveUp
information from NetData to put it in AutoSegment.
* New: In AntennaProtect(Net*), flags the RoutingPad clusters wires
as non movable up.
* New: In AnabaticEngine::breatAt(GCell*), propagate the SegNoMoveUp
flags. Based on NetData.
In Anabatic::AntennaProtect, when we cannot insert enough diodes
under a wire cluster. Which makes it likely very long and over an
area where diodes cannot be inserted (chip border close to I/O pads
or over a macro-block). Request extra diode insertion on it's
connecting RoutingPad clusters.
* New: In Anabatic::DiodeCluster, add a "forced diode" counter for
extra diodes inertions. Only used in the DiodeRps derived class.
* New: In Anabatic::DiodeCluster, add support for a cluster to know
it's neighbors. Stored as indexes of the table being built in
Anabatic::antennaProtect(Net*).
* New: In Anabatic::antennaProtect(Net*), when builing the WireCluster,
also find it's neigbors. Store the index of the cluster a segment
belongs to in clusterSegments.
The H-Tree support is now allowed for any net, not only the clocks and
not only top-level nets. This allow to better management of the LS180
internal clock signal.
* New: In Cell::flattenNets(Instance*,set<string>,uint64_t) new overload
of the function to allow the user to select nets that will *not*
be flattened. This makes the NoClockFlatten flag effectively obsolete,
we keep it for backward compatibility.
The net names can be of non top level ones. In that case, they must
use the name an HyperNet will get (the Occurrence name). For example:
"instance1.instance2.deep_net_name".
* New: In PyCell, update the wrapper for the new parameter of flattenNets(),
new utility function pyListToStringSet() to translate a Python list into
a C++ set of names.
* New: In EtesianEngine, add support for a list of nets to be excluded
from the flattening procedure. Those excluded nets will also be
excludeds from the Coloquinte nets *and* HFNS synthesis, as they
are likely to be manageds by a H-Tree.
* Change: In AnabaticEngine::_loadGrByNet(), now also skip nets that are
flagged as manually detailed route.
* New: In AnabaticEngine::antennaProtect(), do not try to insert diodes
on nets that are already fixed or detaled route. This replace the
clock exclusion.
* New: In cumulus/plugins.{block,htree,chip}, replace the concept
of clock-tree by the more generic H-Tree. That is, we can ask the P&R
to create H-Tree on any net of the design, not only the ones matcheds
as clock. The net does not even need to be top-level.
This is to manage the PLL internal clock generated by the PLL in
the LS180 chip.
Start to change all reference to "clock" into "H-Tree".
* Bug: In cumulus/plugins.chip.powerplanes.Builder._connectHTree(),
there was an inversion of the H & V routing gauges to compute the
track into which put the H-Tree center to corona edge wiring.
This was causing tracks to be used twice, seen in the ao68000 test
bench.
* New: In Anabatic::DiodeWire, use "antennaDiodeMaxWL" to compute the number
of diodes to insert in a wire only cluster. Use boxes instead of segments
to define the area as segments can be splitted by the diodes inserteds
at the DiodeRps stage.
* New: In DiodeWire::createDiodes(), specific diode insertion method.
Try to instert first in long horizontal wires.
When a long *horizontal* wire connect to a cluster, an antenna effect
may be created *before* the METAL3 is deposited, if the cluster's diode
is not *directly* connected to the gate through *only* METAL2. So, we
add a "forced halo" where the long horizontal connecting wires will be
broken by a diode *near* the gate. This problem do not occur for long
connecting METAL3, as the diode will be connected by then. Note that
we are hard-coding the gauge routing direction in the algorithm.
With that modification, only one antenna effect remains in LibreSOC
LS180. May be corrected by post-treatement.
* New: In Anabatic::DiodeCluster::mergeForcedhalo() add specific secondary
areas where diode must be insterted in addition to the one of the
RroutingPad cluster. To "isolate" the cluster from long horizontal
wires.
Protecting clusters of sinks is not enough. There can be very long
wires that far exceed the protection capacity of one diode. Instead
of putting a bunch of diodes near the sinks, we choose to put them
regularly along the interconncting wires.
With this approach we are down to 7 antenna violations on LibreSOC
LS180 test chip.
This will get less good results on arlet6502 & ao6800 because of the
core being a long way from the I/O pads. Should create jumpers on thoses,
but it is for later.
First part of the antenna effect protection : diode insertions.
Anabatic::antennaProtect(Net*) and it's supporting infrastructure
has been rewritten & simplificated. Must be used in conjuction
with the "Flexlib" bloat model of Etesian. A cursory description
of the algorithm has been added in the source file.
* New: GCell::hasNet() to tell if net is going through a GCell,
either as a straigth wire or has a local GContact (turn,
branch, terminal).
* New: Etesian::BloatFlexib class (tagged "Flexlib") suited for
flexlib uses. It is derived from "nsxlib".
To have enough space to insert all the wanted diodes, we
enlarge "mx2_x2" & "mx3_x2" of resp. 1 and 2 pitches.
This is an empiric finding, Yosys seems very fond of thoses
gates and we often see them underneath area where no space
was available to put a diode... May need some more fine grained
analysis.
* Change: In EtesianEngine::globalPlace(), disable the call to
antennaProtect(). First reason is that, after all, Coloquinte
do not handle so well the resizing of the cells "on the fly",
it overspill the boundaries sometimes. Second reason is that
as we cannot know the routing tree at this stage, we will not
be able to choose the correct points for diode insertions.
We only have a Steiner tree wich may not be the same as a
density driven Dijkstra.
* Change: In Etesian::Area, the Occurrence to the Instances where
not stored in a uniform way. Some where starting from the
placed sub-block, some where starting from the top level
(corona), making their processing (and remembering it) tricky.
Now, they are all expressed from the top cell (corona).
The coordinate system is now systematically the one of the
top block (*not* the block).
Create various overloaded functions EtesianEngine::toCell()
and EtesianEngine::toBlock() to ease Occurrence & coordinate
translations.
* New: In Etesian::Slice::createDiodeUnder(), add a X position hint.
Search is done by going through the whole slice range and
minimizing the distance to the hint. If it starts to be too
slow, we may optimize.
* Bug: In EtesianEngine::toColoquinte(), the placement of the top
level external pins was not taken into account (this at last
explain their weird positioning).
* New: AnabaticEngine::antennaProtect(), new algorithm to avoid
antenna effect. This step must be done *after* global routing
and *before* detailed routing. This way we have access to the
real routing and can mend it (along with the netlist) to
insert diodes at the rigth points.
From the global routing we build clusters (DiodeCluster) of
RoutingPads connected through a set of wire whose total length
is below the antenna effect threshold. Long wires connecting the
clusters are also tagged because we need to put a diode between
them and the first RoutingPad of the cluster. This is to avoid
a long METAL2 wire connecting to the RoutingPad before the diode is
connected through METAL3 (in case of misalignment).
This protection is not even enough. For *very long* wires, we
needs to put *more* than one diode (this is to be implemented).
Jean-Paul Chaput