* New: In cumulus/plugins/sram_256x32.py, build the output mux using a
NAND2/NOR2 binary tree instead of mux2/mux3. Use more, but much
smaller cells. The reduction of wirelength (from Yosys) goes
from 4% to 15% for the non-folded variant.
Uses a specially placed tree to minimize wire length.
* New: In cumulus/plugins/sram.py, extend StdCellConf to convert names
accross library flavors (FlexLib_TSMC_C180, FlexLib_Sky130 and
generic SxLib).
The generator as been build in two parts:
1. A genereric sram.BaseSRAM class to provides support for all kind of
SRAM (grouping column tree, headers, folding).
2. The specific SRAM_256x32 (256 words of 32 bits) suited for the
ethmac.
The sram has been simulated with genpat+asimut and gives identical
results to the Yosys one (at gate level). No timing though.
Jean-Paul Chaput