Commit Graph

2918 Commits

Author SHA1 Message Date
Robert Taylor f604351fa2 Move into Corilois namespace 2023-01-19 16:04:17 +00:00
Robert Taylor 546dfa2f20 Add version and author to pyproject.toml 2023-01-19 16:04:17 +00:00
Robert Taylor c0054eb267 Fix errors when building clean 2023-01-19 16:04:17 +00:00
Robert Taylor 46acf17e47 install helpers at top level 2023-01-19 16:04:17 +00:00
Robert Taylor a0b307b3b4 Add bin files as scripts 2023-01-19 16:04:17 +00:00
Robert Taylor cd4f8560ca Fix Python linking issues 2023-01-19 16:04:17 +00:00
Robert Taylor 8dfd522b71 Give same import semantics for now, fix rpath issue 2023-01-19 16:04:17 +00:00
Robert Taylor d31c489e33 Add Coriolis dir that poetry needs, along with base __init__.py 2023-01-19 16:04:17 +00:00
Robert Taylor 80e83d42ed Poetry package build working for most of coriolis 2023-01-19 16:04:17 +00:00
Robert Taylor 57ac01b54a Move to packaging requiring no changes to CMake 2023-01-19 16:04:17 +00:00
Robert Taylor c277d9f121 Initial Poetry infrastructure 2023-01-19 16:04:17 +00:00
Robert Taylor c41b92e45f Move decprecated components out of the way, to avoice confusion 2023-01-19 16:04:17 +00:00
Jean-Paul Chaput f7b2a4f5bb The previous fix for low metal tech, must apply only for them in htree. 2023-01-19 14:54:00 +01:00
Jean-Paul Chaput 38cc00005d Fix missing VIA & bad offset in htree for low metal techs. 2023-01-19 13:57:35 +01:00
Jean-Paul Chaput 96fe367cc0 Fix overlap of non-used RoutinPads in VH,2RL styles.
* New: In KatanaEngine::digitalInit(), when using a "VH,2RL" style,
    protect all RoutingPads of each net, because unlike "2RL+" style,
    the standard cell RoutingPads are not in a "below" layer only
    used inside the cell, but on the V layer. So the area of the RP,
    even if not fully used to connect, must be protected.
* Change: In NegociateOverlapCost(), when computing cost from a fixed
    or blockage, do not set the infinite flag if it's the *same* net.
* New: In KatanaEngine::protectRoutingPads(), add a new "flags" argument
    to pass on whether we want to protect the the RP candidates or just
    the non-used ones.
* Change: In protectRoutingpad(), change the formula (again) to compute
    the berth to give to a fixed segment... Should really try to
    summarize all the case.
* Change: In TrackFixedSegment::getNet(), no longer return the blockage
    net if the real net is tagged as clock.
2023-01-18 23:42:38 +01:00
Jean-Paul Chaput 047bf14921 Wrong computation of the up/down dogleg layer for 2 layers gauges.
* Bug: In Anabatic::AutoHorizontal::_makeDogleg(), the up/down flag
    was incorrectly computed when the RoutingGauge RL where not the
    lower one. This was leading to making doglegs in non-routable
    layers (but present in the gauge for other purposes).
2023-01-18 23:42:17 +01:00
Jean-Paul Chaput 2116e181de Add a breakpoint *before* global routing loading in cumulus/block.py. 2023-01-18 23:20:28 +01:00
Jean-Paul Chaput c7330041fb Remove unmatched DebugSession::close() in RawGCellsUnder. 2023-01-18 15:49:51 +01:00
Jean-Paul Chaput 7598485a4f Allow the BigVia to stack the cuts in some cases. 2023-01-14 22:38:36 +01:00
Jean-Paul Chaput 9df5fc838c Support for non-stacked VIAs in Katana.
* New: In Katana::Configuration, added option:
    "cfg.katana.disableStackedVias" (default to false), so the router
    do not stack VIAs on top of each other.
* Bug: In NegociateWindow::loadRoutingPads(), create TrackMarkers using
    the right depth when the gauge starts with non-routable ones.
* New: In Track::addOverlapCost(), when disableStackedVias is active,
    uses the markers from the below terminals to tag the cost as
    "infinite", so the track *cannot* be used by the marker's net
    owner. Can be refined by checking that we are not at a segment's
    end but will do for now.
2023-01-14 22:35:57 +01:00
Jean-Paul Chaput 7d88b14334 Keep Sphinx variant documentation sources, just in case... 2023-01-14 12:45:08 +01:00
Jean-Paul Chaput 0a69e7d62d Correct broken links in Python Tutorial documentation. 2023-01-14 12:41:06 +01:00
Jean-Paul Chaput 181b2e1080 Re-enable and check the building of I/O ring with pad spacers.
* New: In cumulus/block.bigvia, add a getBoundingBox() method.

* New: In cumulus/block.configuration.GaugeConf.rpAccess(),
    add a vertical strap segment in case the RP is not high enough to
    accomodate the potential offset of the contact.
      In case of gauge with only two routing layers, if the RP
    is vertically accessed, do not put a VIA12 but just a METAL2
    contact (there will be *no* turn).

* Change: In cumulus/chip.CoreWire.drawWire(), the wire at *chip level*
    going to the pad was shrunk of 3 pitch when *not* in the preferred
    routing direction. Removing it as it creates gaps in some cases.
      This was likely needed for a specific kind of I/O pad so should
    be re-enabled on targeted cases in the future.

* Change: In cumulus/chip.corona.VerticalRail, manage in a smarter way
    the conflicts when a rail is accessed from both sides overlapping
    on an Y position. That is, from the supply I/O pads *and* from the
    *core* supply lines.
      Formerly, we just didn't connect the core power line, which was
    a mistake potentially leaving power rails unconnected (it it did
    occur on both sides).
      Also checks if the conflict really arise, that is, the power lines
    are both on top or bottom.

* Change: In cumulus/chip.pads.Side._placePad(), manage I/O pads with
    a bottom left corner of abutment box *not* at (0,0). Argh!

* Bug: In cumulus/chip.pads, create the filler pad instances in the
    chip, not in the corona.
2023-01-14 12:39:22 +01:00
Jean-Paul Chaput 0e17b91692 Add at least one pitch to each cell in BloatChannel profile.
* Change: In Etesian::BloatChannel, when two DFFs are side by side, if
    they are not separated by at least one pitch, the track avoid
    mechanism will not be able to work. Hence the minimal one pitch.
2023-01-14 12:09:43 +01:00
Jean-Paul Chaput 83ff59817a Export CellViewer::setPixelThreshold() to the Python interface. 2023-01-14 12:06:15 +01:00
Jean-Paul Chaput c86d074f06 Export Contact::setLayer() to the Python interface. 2023-01-14 12:05:51 +01:00
Jean-Paul Chaput 3e921ff07a More debug information in chip pad & corona generation.
* Change: In cumulus/plugins.chip.configuration, do not add an extra
    slice height to the minHCorona & minVCorona. Now seems a bit overkill
    on small chips.
2023-01-09 09:26:44 +01:00
Jean-Paul Chaput bdb0091043 Just a little indentation for my autistic self. 2023-01-09 09:21:56 +01:00
Jean-Paul Chaput e38e3f46f2 Route ring pad wires, even if there is no pad on that side. 2023-01-07 13:08:10 +01:00
Jean-Paul Chaput 0bc7b3203a Add DesignFlow to the doc generation. New snapshot of the doc. 2023-01-07 13:01:23 +01:00
Jean-Paul Chaput 30afe6036b Add management of unused layers in cumulus/plugins.block.configuration. 2023-01-07 12:57:23 +01:00
Jean-Paul Chaput d9ebeb4b96 Search path reordering in crlenv.py so the debug version can be found. 2023-01-07 12:53:11 +01:00
Jean-Paul Chaput d2b40d568b Extend routing gauge to support non-routing layers at the bottom.
* New: In CRL::RoutingLayerGauge, two new types of gauge are supported:
    - Unusable : just do nothing with it, but the layer is stacked.
    - BottomPowersupply : can be used for supply routing only, and
      is *below* the normal routing layers (instead of on top as
      usual).
    Both new types must be *below* the real routing layers.
* New: In CRL::RoutingGauge, add a new attribute "firstRoutingLayer"
    to give the index (depth) of the first layer usable for routing.
    (not Unusable and not BottomPowerSupply)
* New: In Anabatic::Session & Anabatic::NetBuilder, in order to build
    the initial wiring, provides (Session) and use (NetBuilder) the
    new functions:
      - getBuildRoutingLayer(depth)
      - getBuildContactLayer(depth)
      Thoses functions takes into account (offset) the unusable layers
    so depth 0 is the first usable routing layer, and so on.
2023-01-07 12:51:38 +01:00
Jean-Paul Chaput 2501688dd1 Add support for layers alias names. Bug in _addPhysicalrule().
* New: In Technology, in order to support symbolic technology on top
    of a real technology using non-generic layer names, it comes in
    handy to be able to define layer alias names. Generic *real*
    layer names could be defined as alias over the technology
    specific ones. Then, we can build the symbolic layers upon
    the generic names (so *that* part of the init code can be
    shared between techs).
       Adds Technology::addLayerAlias()
       The semantic of Technology::getLayer() changes a little, it
     return the techno layer associtated to the name *or* the
     aliased name.
* Bug: In Technology::_addPhysicalRule(), in case of a rule redefinition,
    we were using it's name *after* the deletion of the rule object.
    Nasty crash.
      Improve the error message by giving the name of the conflicting
    rule.
* In CRL/helpers.analogtechno, add an addDevice() function to load
    analogic devices descriptors (copied from the old init system).
* In CRL/ApParser, if an exception is catched, tells in which file and
    line it did occur.
* In Oroshi/dtr.Rules, add a translation step to get the rule names
    from the technology. From generic names to actual technology
    layer names.
       Add some documentation.
* In Oroshi/stack.Stack, get the layers names through dtr.Rules to get
    the layers names translated.
2023-01-05 16:58:49 +01:00
Jean-Paul Chaput da56189d2e allianceInstaller.sh also must support nightly builds. 2023-01-02 12:24:19 +01:00
Jean-Paul Chaput db54e685f7 Correct again for nightly build. 2023-01-02 12:06:03 +01:00
Jean-Paul Chaput 100342e640 Support for nightly build in booststrap/crlenv.py. 2023-01-02 11:47:45 +01:00
Jean-Paul Chaput e590400ebb Add DoIt base design flow support. In full replacement of Makefiles. 2022-12-31 15:01:37 +01:00
Jean-Paul Chaput ae01be3c53 Set the initial verbose levels to off. Smarter loadUserSettings(). 2022-12-31 14:50:46 +01:00
Jean-Paul Chaput 36eb9f9121 Export the Alliance library list in AllianceFramework (as a list). 2022-12-31 14:48:25 +01:00
Jean-Paul Chaput b8cd4264bd Bug in topology management switch in NetBuilder::construct().
* Bug: In NetBuilder::construct(), the xG_xM1 topologies where wrongly
    redirected towards xG_1M1, so only one M1 was connected, all others
    left floating.
      Now direct them towards xG_xM1_xM3.
* Bug: In NetBuilderHybridVH, activate topology management for 2G_1M1.
2022-12-16 20:02:11 +01:00
Jean-Paul Chaput b65e6f83ff More clean approach to the verbosity levels in overlay and io. 2022-12-16 17:17:30 +01:00
Jean-Paul Chaput c85ad530c4 Take into account blockages and right shift bug in track avoidance.
* Change: In Etesian::SubSlice::getUsedVTracks(), now take blockages
    into account for used vertical tracks.
* Bug: In Etesian::SubSlice::avoidTrack(), right free interval for
    shifting was wrongly computed, effectively allowing *any* shift.
    This was creating cells overlap!
* New: In Hurricane::BasicLayer & Layer, establish a two way link
    between the blockage layer and routing layer. Now we can access
    the routing layer from the blockage.
2022-12-16 17:17:05 +01:00
Jean-Paul Chaput ca41dbd5ef Support for avoidance of vertical tracks in low metal techs.
* New: In NetBuilderHybridVH::_do_1G_xM1_1PinM1(), added configuration
    to manage pins on the north/south sides for VH,2RL.
* Bug: In NetBuilderHybridVH::doRp_xG_xM1_xM3(), correct misplaced
    vertical creation (buildind invalid topologies).
* New: EtesianEngine::toColoquinte(), display histograms of the cells
    widths (in pitch) before and after bloating to get a better feeling
    of the behavior.
* New: In EtesianEngine, add support for track avoidance. Portions of
    tracks to avoid are specified by a Box, which should flat and on
    the axis of the request track. This feature is used by the H-Tree
    to clear the vertical tracks under the tree from any terminal.
* New: In Etesian::Area, Slice and SubSlice, add support for track
    avoidance. Exported to the Python wrapper.
* New: SubSlice::getUsedVTracks() to get a set of tracks blocked by
    the cell.
* New: SubSlice::trackAvoid(), shift left/rigth the cell under the
    requested vertical track. Try only to move the cell under the
    track and not it's neighbor, so it assume that there is sufficient
    space left or right of the cell.
* Bug: In cumulus/plugins.block.configuration.BlockConf, the Cfg
    parameters may be read too early from the Cfg space into the
    various sub-conf objects (like FeedsConf). Delay the reading
    of the parameters in a _postInit() functions.
      Modify Block and CoreToChip to call _postInit().
* New: In cumulus/plugins.block.configuration.BlockConf._loadRoutingGauge,
    allow the cell gauge name to differ from the routing gauge name.
* New: In cumulus/plugins.block.configuration.FeedsConf, allow to
    select the default feed to be used with 'etesian.defaultFeed'
    parameter.
* New: In cumulus/plugins.block.spares.BufferPool, allow to control
    whether or not we want tie to either side of the pool.
    (for latch up).
* New: In cumulus/plugins.block.HTree._connectLeaf(), add support
    for track avoidance.
* Bug: In cumulus/plugins.block.HTree._connectLeaf(), the TL2 contact,
   the one on the *top* auxiliary buffer seemed to have been badly
   positioned until now (too low, not using tl2Y).
     This is strange because it should have caused disconnections,
   but I didn't see it in the wiring and the regressions tests didn't
   flag anything wrong. Still a bit weird and worrying.
2022-12-13 16:02:23 +01:00
Jean-Paul Chaput 49bcdb3195 One more remains of the previous routing configuration. 2022-11-26 15:05:56 +01:00
Jean-Paul Chaput c131e7a948 Clean parameters for routing topologies. Improved 2RL- support.
Previously, the relevant NetBuilder and routing strategies where
directly guessed from the RoutingGauge traits. This is no longer
doable as the combinations increases. Now to configure both the
global and detailed router we need three "parameters" :

1. The routing gauge itself (tells which layers are in which
   directions) and how to make the VIAs.
2. The NetBuilder to use, they are identified by strings.
   Currently we support:
   * "HV,3RL+", for all SxLib derived standard cells.
   * "VH,2RL", for hybrid routing (over the cell, but terminals
     are also in the first RL).
   * "2RL-", for strict channel routing.
   * "VH,3RL+", an attempt for FreePDK 45, not optimized enough
     to be considered as usable.
3. The routing style, mostly affect the way the GCell grid will be
   built.
   * VH      : first RL is V.
   * HV      : first RL is H.
   * OTH     : Run in full over-the-cell mode (needs at least 3RL).
   * Channel : Run in *strict* channel routing mode (no routing over
               the standard cells).
   * Hybrid  : Create channels, but can use H tracks over the
               standard cells.

Thoses three parameters are partly overlapping and must be sets in
a consistent manner, otherwise strange results may occurs.

* New: CRL::RoutingGauge::getFirstRoutingGauge(), to get the lowest
    layer available for routing (not a PinOnly, not a PowerSupply).
* Change: In CRL::RoutingGauge::isHV() and isVH(), were previously
    always returning false when the gauge was 2RL only. Now, check
    on the first usable RL.
* Bug: In cumulus/plugins.block.configuration._loadRoutingGauge(),
    there was a bad computation of the deep RLs when the top layer
    was not defined. Occured for 2RL gauges only.
* Bug: In Anabatic::RpsInRow::slacken() (LayerAssign), forgotten curly braces
    in the test to skip METAL2 terminals.
* Change: In Etestian::BloatChannel::getDx(), adjust the bloating
    policy to converge on Arlet6502. Always ensure that there is
    a 50% ratio between terminal used V-tracks and free ones.
      If there is more than 80% of terminals, add one more track.
* Bug: In AnabaticEngine & KatanaEngine, KatanaEngine is a derived
    class of AnabaticEngine.  They uses Anabatic::Configuration
    and Katana::Configuration that also derives from each other.
    I though I had made one configuration attribute in the base
    class that was using the right Configuration. But no. I did
    have two configurations attributes, one in AnabaticEngine and
    one in KatanaEngine, the later "shadowing" the former. As a
    results, parameters modified in AnabaticEngine, *after* the
    initial creation of the tool *where never seen* at Katana
    level (due to it's own duplicate). What a mess.
      Now there is only one attribute in the *base* class Anabatic,
    which is created through a new virtual function _createConfiguration()
    called in _postCreate() which allocate the right Configuration
    according to the dynamic type of the tool (KatanaEngine).
      In KatanaEngine, access the configuration through the
    attribute (_configuration) and not the accessor (getConfiguration()).
* Bug: In KatanaEngine, no longer directly use the _configuration attribute
    (which is not accessible anyway) but the getConfiguration() accessor.
    The accessor perform a static_cast from the Super::getConfiguration()
    into Katana::Configuration.
      Complete cleanup of the various configuration accessors.
* New: AnabaticEngine::setupNetBuilder(), perform an early check
    of the requested NetBuilderStyle. The NetBuilderStyle is just a
    string that will be matched against the (hard-coded) supported
    NetBuilders. Then check the topological characteristics against
    the capabilities of the gauge (HV, VH and so on).
      Still a bit too hard-coded for now.
      This function has been split from AnabaticEngine::_loadGrByNet().
* Change: AnabaticEngine::isChannelStyle() renamed from isChannelMode().
* New: In Anabatic::Configuration, two new attributes to select the
    topology and routing style:
      - _netBuilderStyle to explicitely select the NetBuilder to use.
        It's a string, which is provided by each NetBuilder.
      - _routingStyle to define how the overall routing will work.
        It's a set of flags (StyleFlags):
	* VH      : first RL is V.
	* HV      : first RL is H.
	* OTH     : Run in full over-the-cell mode (needs at least 3RL).
	* Channel : Run in *strict* channel routing mode (no routing over
	            the standard cells).
	* Hybrid  : Create channels, but can use H tracks over the
	            standard cells.
* New: In anabatic/Constants, add StyleFlags to define how the router
    should operate (see above).
* Bug: In Anabatic::GCell, in CTOR, no reason to set up the HChannelGCell flag.
* Bug: In Anabatic::GCell::updateDensity(), when computing layers non contiguous
    saturation, do not systematically skip RL 0, but only if it's PinOnly.
* Change: In Anabatic::NetBuilder, rename isTwoMetal by isStrictChannel.
* Change: In Anabatic::NetBuilderHV, rename doRp_AccessNorthPin() in
    doRp_AccessNorthSouthPin(). More accurate.
* Bug: In NetBuilderHV::_do_1G_xM1_1PinM2(), the wires to connect the M1
    terminals where created *twice*. Uterly stupid, there where placed in
    overlap by the router!
* New: In AnabaticEngine, new accessors to the NetBuilderStyle and
    RoutingStyle, proxies towards Configuration.
* Bug: In Manipulator::relax(), if there are two doglegs to be done, but
    they are in the same GCell, only do one (the conflicting interval)
    is short.
* Change: In Katana::Session, rename isChannelMode() into isChannelStyle().
* Change: In TrackSegment::isUnbreakable() and isStrap(), return false
    when the base segment is a *weak global* (aligned with a global one).
* Change: In Katana::Row::createChannel(), correctly distinguish between
    *strict channel* style and *hybrid* style. Tag the GCells as std cells
    row or channels only in the former case.
2022-11-26 13:07:12 +01:00
Jean-Paul Chaput e262c7bd1a Merge branch 'fix-duplicate-case-filenames' into 'devel'
Remove old generated files that clash on case-insensitive file systems

See merge request vlsi-eda/coriolis!15
2022-11-15 23:06:13 +00:00
Robert Taylor 68a3695780 Remove old generated files that clash on case-insensitive file systems 2022-11-15 11:51:43 +00:00
Jean-Paul Chaput 2b870fc609 Remove obsolete dependency towards LibXml2 in CMakeLists.txt. 2022-11-07 17:36:49 +01:00
Jean-Paul Chaput ecda00e154 Adjustments in AutoSegment::canReduce() and TrackSegment::canRealign().
* Change: In AutoSegment::canReduce(), allow reduction, when in channel
    mode, for bottom connected jumpers at depth 1. Forbidden otherwise
    as it may cause problems with the terminals (in OTC).
* Change: In TrackSegment::canRealign(), allow realignement of reduced
    segments. What really needs to be checked is that it do not have
    perpandiculars in reduced state.
2022-11-03 10:36:44 +01:00