* New: In bootstrap/coriolisEnv.py, add the "etc" directory to the
PYTHONPATH as initialization are now Python modules.
* New: In Hurricane/analogic, first groundwork for the integration of
PIP/MIM/MOM multi-capacitors. Add C++ and Python interface for the
allocation matrix and the list of capacities values.
* Change: In Hurricane::RegularLayer, add a layer parameter to the
constructor so the association between the RegularLayer and it's
BasicLayer can readily be done.
* Change: In Hurricane::Layer, add a new getCut() accessor to get the
cut layer in ViaLayer.
* Change: In Hurricane::DataBase::get(), the Python wrapper should no
longer consider an error if the data-base has not been created yet.
Just return None.
* Bug: In Isobar::PyLayer::getEnclosure() wrapper, if the overall
enclosure is requested, pass the right parameter to the C++ function.
* Change: In AllianceFramework, make public _bindLibraries() and export
it to the Python interface.
* Change: In AllianceFramework::create(), do not longer call bindLibraries().
This now must be done explicitely and afterwards.
* Change: In AllianceFramework::createLibrary() and
Environement::addSYSTEM_LIBRARY(), minor bug corrections that I don't
recall.
* Change: In SearchPath::prepend(), set the selected index to zero and
return it.
* Change: In CRL::System CTOR, add "etc" to the PYTHONPATH as the
configuration files are now organized as Python modules.
* New: In PyCRL, export the CRL::System singleton, it's creation is no
longer triggered by the one of AllianceFramework.
* New: In CRL/etc/, convert most of the configuration files into the
Python module format. For now, keep the old ".conf", but that are no
longer used.
For the real technologies, we cannot keep the directory name as
"180" or "45" as it not allowed by Python syntax, so we create "node180"
or "node45" instead.
Most of the helpers and coriolisInit.py are no longer used now.
To be removed in future commits after being sure that everything
works...
* Bug: In AutoSegment::makeDogleg(AutoContact*), the layer of the contacts
where badly computed when one end of the original segment was attached
to a non-preferred direction segment (mostly on terminal contacts).
Now use the new AutoContact::updateLayer() method.
* Bug: In Dijkstra::load(), limit symetric search area only if the net
is a symmetric one !
* Change: In Katana/python/katanaInit.py, comply with the new initialisation
scheme.
* Change: In Unicorn/cgt.py, comply to the new inititalization scheme.
* Change: In cumulus various Python scripts remove the call to
helpers.staticInitialization() as they are not needed now (we run in
only *one* interpreter, so we correctly share all init).
In plugins/__init__.py, read the new NDA directory variable.
* Bug: In cumulus/plugins/Chip.doCoronafloorplan(), self.railsNb was not
correctly managed when there was no clock.
* Change: In cumulus/plugins/Configuration.coronaContactArray(), compute
the viaPitch from the technology instead of the hard-coded 4.0 lambdas.
In Configuration.loadConfiguration(), read the "ioring.py" from
the new user's settings module.
* Bug: In stratus.dpgen_ADSB2F, gives coordinates translated into DbU to
the XY functions.
In st_model.Save(), use the VstUseConcat flag to get correct VST files.
In st_net.hur_net(), when a net is POWER/GROUND or CLOCK also make it
global.
* Change: In Oroshi/python/WIP_Transistor.py, encapsulate the generator
inside a try/except block to get prettier error (and stop at the first).
* Change: In Hurricane::Error constructors disable the backtrace generation.
(*very* slow).
* Change: In Hurricane::Library::getHierarchicalname(), more compact
naming. Remove the name of the root library.
* New: In Hurricane::Net, new type "FUSED", for component with no net.
More efficient than having one net for each.
* Change: In CellViewer, BreakpointWidget, use Angry Birds icons.
* Change: In CellWidget::State, use the hierarchical name (cached) as key
to the state. This allow to load two cells with the same name but from
different libraries in the widget history.
* Change: In PyGraphics, export "isEnabled()" and "isHighDpi()" functions.
* Change: In CRL/etc/symbolic/cmos/plugin.conf, and
CRL/etc/common/plugin.conf use the physical dimensions converters.
* Change: In CRL/etc/symbolic/cmos/technology.conf, make the GDS layer
table coherent with the default Alliance cmos.rds.
* New: CRL/python/helpers/io.py, put ErrorMessage new implementation here,
along with a new ErrorWidget written in PyQt4. It seems finally that
PyQt4 can be used alongside Coriolis Qt widgets.
New ErrorMessage.catch() static function to manage all exceptions
in except clauses.
* Change: In CRL/python/helpers/, no longer use ErrorMessage.wrapPrint(),
directly print it.
Rewrite the utilities to display Python stack traces "textStacktrace()"
and "showStacktrace()".
* Change: In CRL::AllianceFramework, shorten the names of the libraries.
* Change: In CRL::ApParser & CRL::ApDriver, more accurate translation between
Alliance connectors (C record) and Hurricane::Pin objects. Pin are no
longer made square but thin and oriented in the connecting direction.
Use the new fused net for unnamed components.
* New: In CRL::GdsParser, implementation of SREF parsing, i.e. instances.
Due to the unordered nature of the GDS stream, instances creation are
delayed until the whole stream has been parsed and only then are they
created.
For the sake of reading back Alliance s2r GDS, we assume that any
TEXT following a boundary is the Net name the boundary (component)
belongs to.
Create abutment box for Cells, computed from the bounding box, so
the Hurricane QuadTree could work properly.
Make use of the fused net for unnamed components.
* New: In Cumulus/plugins/chip, complete rewrite of the I/O pad management.
Now we can mix real (foundry) pads and a symbolic core.
To cleanly support the de-coupling between the real part and the
symbolic one we introduce a new intermediary hierarchical level, the
corona. We have now:
Chip --> Pads + Corona --> Core.
At chip level (and if we are using real pads) the layout is fully
real (excepting the corona).
The Corona contains everything that is symbolic. It has symbolic
wires extending outward the abutment box to make contact with the
real wires coming from the pads.
In the pad ring we can use corners instances (or not), pad spacers
or directly draw wires between connectors ring pads.
Provide two flavors: placement only or full place & route.
WARNING: If routing in a second step, *do not route* the *Chip* but
the *Corona*.
* Change: In Cumulus/plugins/clocktree, give the modified Cell an
additional extension of "_cts" (Clock Tree Synthesis) instead of
"_clocked", to follow the common convention.
* New: In cumulus/plugins/S2R.py, encapsulate call to Alliance S2R and
reload the translated Cell in the editor.
* New: In cumulus/plugins/core2chip, provide an utility to automatically
create a chip from a core. To work this plugins must have a basic
understanding of the pad functionalities which may differs from
foundry to foundry. So a base class CoreToChip is created, then for
each supported pad foundry a derived class is added. Currently we
support AMS c35b4 and Alliance symbolic cmos.
* Bug: In Anabatic::Configuration, read the right configuration parameter
"anabatic.topRoutinglayer" (Katana), and not the one for Katabatic...
* Change: In Unicorn/cgt.py, process the plugins in alphabetical order
to ensure a reproductible ordering of the menus...
* Change: In Stratus, in dpgen_RAM, the cell height was fixed to 50l.
Now read the prech[0] to set up the cell height (useful for MOSIS
cells).
* New: In Stratus, in buildModel(), the stand alone generator caller
now support a className, a modelName and a set of parameters to
pass on to the model. This is very useful when the module name
(the file), the class name and the model name are not the same.
* In Hurricane, in Cell::flattenedNets(), if the cell has already been
flattened, do not issue warnings about duplictated flattened nets.
* In Hurricane, in Net, allow Net::setName() to switch the main name
for an alias without complaining about an already used name.
* In Cumulus, in RSavePlugin.py, when "views" is supplied in keywords
(kw) arguments, override the default instead of merging with it.
This is to allow scripts to save exactly what views they want.
* Bug: In CRL Core, in BlifParser, recognize clocks (Alliance patterns).
* Change: In Cumulus, in RSavePlugin, "kw" manage a new "views" to
specify which views must be saved. Physical by default, but sometimes
we need logical as well. If the design contains uniquified cells,
save the logical view.
In ClockTree, abort the clock tree building if the design has no
top level clock.
* Change: In Katabatic, in GCellTopology, adds 2G_5M1 configuration.
* Bug: Kite, in BuildPowerRails, if we are not in a chip the nets
composing the H-Tree must be protecteds be blockages.
* New: In Hurricane, in Cell & Instance, add the ability to merge the
QuadTree when *second level* instances of a Cell are placed in
the same space as the top Cell. This is the case of a deeply
hierarchical design made of only standard cells that are to
be placed in a "flat" manner.
The design is uniquified then the intermediate instances models,
which should be unique at that point have their QuadTree merged
through a call to Instance::slaveAbutmentBox(). That method will
make the model of the instance use the QuadTree of the Cell to
which the instance belong. The instance model no longer posseses
a dedicated QuadTree. As a corollary the abutment box of both
Cell are kept identical and the Instance has it's transformation
set to (0,0,ID).
Remark: when we talk about "QuadTree", we mean in fact the
QuadTree for the instances *and* the SliceMap (Layer+QuadTree).
Consequence in Query: when going through the resulting
"flattened" QuadTree we will find objects with an incomplete
Path du to the fact that we didn't have to explore their
Instance/Cell level to reach them. The shunted part of the
Path is stored in the Go master Cell in the _shuntedPath
attribute. This also affect the displayed depth of hierarchy,
but not too badly.
* New: In Hurricane, in Cell, new methods:
- Cell::updatePlacedFlag() : set the placement flags.
- Cell::isUnique() : one or less instance.
- Cell::isUniquified() : is the result of an uniquification.
- Cell::isUniquifyMaster() : is the reference cell of the
uniquification.
* Change: In Hurricane, in Cell::Uniquify(), uniquify a Cell only
if it is unplaced. We do not need to duplicate placed Cells
(see datapathes).
* Bug: In Hurricane, in NetAlias, bad Record construction of the _next
field.
* New: In CRL Core, in VstDriver complete replacement of the old Vst
driver. Needed cleaner architecture to manage correctly files
importeds through the Blif parser, which are Verilog like.
It is build as an extension trough property and is not kept
in sync with the Cell. So it's use should be transient only.
* Change: In CRL Core, in NamingScheme forgot to change '.' (dot)
forbidden character into '_'.
* Change: In Cumulus, in the RSave plugins, remove the VHDL extensions
after saving.
* New: In Hurricane, In Net & Cell, support for Net aliases names.
Use a structure based on a simple ring of NetAliasHook. The Net
holds a global map, sorted by names of all the aliases of all Nets.
Elements NetAliasesHook of the map are slaves of ring whose master
is an attribute of the Net (it is *not* in the map, as the primary
name of the Net).
In case of merge, the aliases of both Nets are merged and the
name of the merged one become an alias.
The Cell::getNet() looks in both the Net map and the aliases to
find a Net by name.
* Bug: In CRL Core, in coriolisInit.py, reoder the loading of the
configuration files so the real technology is read as early as
possible to set up the <gridsPerLambda> factor before any lambda
is actually computed...
* Bug: In CRL Core, in AcmSigda, do not try to fed the file when it
has failed to be opened. Throw a clean exception instead.
* New: In CRL Core, in Toolbox, add a NamingScheme object to convert
a design into VHDL compliant names (mainly from Blif/Verilog).
This is extensible in any case.
* New: In CRL Core, in BlifParser, slightly more informative warning
messages. Align the loading progress information on the other
parsers.
Add a capability to select which component of the design will
be returned, if there are more than one. Use the "." as separator.
For exemple you can request "Processor.Alu", which will load
the "Alu" component from the design in "Processor.blif".
To be able to save a Blif loaded design, systematically convert
all the name for VHDL compliance, as it is the format used by
the Coriolis native files (vst).
Export the Blif parser to the Python interface.
* New: In Kite, In NegociateWindow, add a counter of the number of
remaining events. Gives an idea of the ETA...
* New: In Unicorn, in cgt.by, add an option to load a Blif design from
the command line.
* New: In Cumulus, new RSave plugin to save both netlist & layout.
Partly redundant with the previous one. Have to better organize
that later.
* Change: In Hurricane, the NetRoutingProperty is moved into Hurricane
from Katabatic. Needed for Knik to be able to access thoses
informations.
* Change: In Hurricane, in RoutingPad::setOnBestComponent(), now in
case of identical area, select the component of lowest id.
This should not be needed if the component ordering was fully
deterministic as it should be (will investigate later).
This is to ensure that the choosen component is always the
same, especially between save/load of a global routing.
* Bug: In Katabatic, in AutoContactHTee::updateTopology(), invalidate
the segments only if the topology is valid (no NULL in the
cached segments).
* Bug: In Katabatic, in GCellTopology::construct(), throw an error
if the topology is bad instead of trying to continue (and core
dump later... ).
* Bug: In Kite, in BuildPowerRails, distinguish the name of the master
net in the pad (for vddi, vssi, vdde, vsse, ck, cki & cko) and the
name of the net in the *chip* netlist. Must use the later to make
comparison as they may differs.
* Change: In Knik, in save/load solution, exclude nets that are not
globally routed by Knik. That is which NetRoutingProperty is not
*Automatic*.
* Bug: In Cumulus, in chip.BlockPower take account of the layer
width extention to sligthy shrink the connector thus avoiding a
notch with standart cell in some cases.
* Change: In Cumulus, in chip.ClockTree disable the use of fixed Steiner
trees for the leaf clocks, as it seems overconstrained for the
router. First move was to lower them in M2/M3 (instead of M3/M4)
but that was not sufficent.
* New: In Cumulus, RSavePlugin for recursively saving a physical
hierarchy.
* New: In documentation, first embryo for RDS file. Should have been
in Alliance git, but I prefer to keep newest doc in Coriolis.
Jean-Paul Chaput