* New: In cumulus/plugins.blocks.iospecs.IoSpecs, new class to manage
I/O pads placement. Support for reading the JSON pinmux format
(courtesy of LKCL & StackOverflow).
* Change: In cumulus/plugins.block.bigvia.BigVia, center the VIA cut
matrix. Issue a BIG warning when no one cut could be drawn
(temporarily disabled until I fix the corona).
* Change: In EtesianEngine, V-Pitch and H-Pitch are now initialized
from the Cell gauge "slice step". It may still be best if the
METAL2 routing grid is still a fractional ratio of the cell height.
* Change: In Hurricane::Contact::Contact(), check width & hieight of
the contact against the minimal size, if below, bellow a warning
and increase the dimension.
May too paranoid when used on turn in same metal (no cut).
Integrate new features and bug fixes so the Arlet 6502 benchs successfully
passes real DRC with reference industrial tools. Short summary:
* Manage minimum area for VIAs in Katana::Tracks.
* Allow different wire width for wires perpandicular to the prefered
routing direction.
* StackedVIAs used in the clock tree no longer assume an uniform
routing grid (same offset & pitch all the way up).
* Some hard-coded patches in PowerRails for FlexLib.
* New: In CRL/symbolic/cmos/kite.py & cmos45/kite.py, update the
RoutingLayerGauges by adding the new PWireWidth parameter.
Always zero in case of symbolic layout (too fine tuning).
* New: In CRL::RoutingGauge, add accessor to PWireWidth parameter.
Modify the clone method.
* New: In CRL::RoutingLayerGauge, add new parameter "PWireWidth"
to give the width of a wire when it not drawn in the prefered
routing direction. If it is set to zero, the normal width is
used.
* New: In CRL::PyRoutingGauge, export the updated constructor
interface. It is *not* backward compatible, one must add the
PWireWidth parameter in the various kite.py configuration
files (in etc/).
* Change: In AnabaticEngine::_gutAnabatic(), disable the minimum
area detection mechanism, replaced by a more complete one in
Katana::Track. Left commented out for now, but will be removed
in the future.
* Change: In Anabatic::AutoContact::updateLayer(), now systematically
calls setLayerAndWidth() to potentially resize the VIAs. This is
needed in real mode as VIAs are *not* macro-generated but have
their real final size.
* Change: In Anabatic::AutoContact::setLayerAndWidth(), select the
width and height of the contact using the gauge wire width *and*
perpandicular *wire width*.
* Change: In Anabatic::AutoSegment::_initialize(), the "VIA to same cap"
to PWireWidth/2, this will be the size of the VIA in the
non-preferred direction at the end cap (non-square in real mode).
* Change: In Anabatic::AutoSegment::getExtensionCap(), makes different
cases for symbolic and real. Use raw length in real, add half the
wire width in symbolic.
Add a flag to get the extension cap *only*, not increased of
half the minimal spacing.
* Change: In Anabatic::AutoSegment::bloatStackedStrap(), enhanced,
but finally unused...
* New: In Anabatic::AutoSegment::create(), use the PWireWidth when
the segment is not in the preferred routing direction (and of
minimal width).
* New: In Anabatic::Configuration, add new getPWirewidth(),
DPHorizontalWidth() and DPVerticalWidth() accessors.
* Change: In AnabaticEngine::setupPreRouteds(), skip components in
in "cut" material. We are only interested in objects containing
some metal (happens in real mode when VIAs cuts are really there).
* New: In Katana::PowerRailsPlanes::Rail::doLayout(), add an hard-coded
patch that artificially enlarge the *wide wire* so the spacing for
wide wire is enforced. For now, two pitches on each side for
"FlexLib" gauge.
* New: In Katana::Track, add support to find and correct small wire
chunks so they respect the minimum area rules.
Two helper functions:
* ::hasSameLayerTurn(), to find if a a TrackElement as non-zero length
perpandicular is same layer connected to it.
* ::toFoundryGrid(), to ensure that all coordinates will be on the
foundry grid (may move in a more shared location).
* ::expandToMinArea(), try to expand, *in the routing direction*
the too small wire so it respect the minimal area. Check for the
free space in the track.
Track::minExpandArea() go through all the TrackElements in the track
to look for too small ones and correct them.
* Change: In Katana::RoutingPlane, add an accessor to get the tracks.
* New: In KatanaEngine::finalizeLayout(), add a post-treatment to find
for minimal area violations.
* Change: In cumulus/plugins.block.configuration.GaugeConf, add a
routingBb attribute that will serve as a common reference to all
the functions calculation track positions. We must not have two
different reference for the core and the corona. The reference
is always the corona when we working on a complete chip.
* New: In cumulus/plugins.block.configuration.GaugeConf.getTrack(),
Simplified and more reliable way of getting tracks positions.
Use the routingBb.
* New: In cumulus/plugins.block.configuration.GaugeConf.rpAccess(),
Make use of getTrack() to get every metal strap on the right
X/Y position.
* New: In cumulus/plugins.block.configuration.GaugeConf.expandMinArea(),
As those wires are left alone by the router, it is our responsability
to abide by the minimal area rule here. Hence the code duplication
from the router (bad).
Mainly wires made for the clock tree, I mean.
* Bug: In cumulus/plugins.chip.configuration.ChipConf.setupICore(),
the core instance must be placed on the GCell grid, defined by the
slice height (X *and* Y).
* Bug: In cumulus/plugins.chip.corona.Builder(), forgot to use bigvia
for the corners of the inner ring.
* Bug: In cumulus/plugins.chip.pads.corona._createCoreWire(), hard-coded
patch for LibreSOCIO, the power/ground connectors toward the core
are too wide and can create DRC errors when put side by side.
Shrink them by the minimal distance.
* Bug: In Anabatic::AutoSegment::reduce(), no longer reduce *again*
an already reduced segment.
This bug was seen through a side effect, it was causing the
"reduced perpandicular" counter to be incremented too much and
so it cannot get back to zero, blocking the layer reduction
(AutoSegment::reduceDoglegLayer()) and some bad VIAs where left
over.
More debug information in reduce & raise functions.
* Change: In Katana::Session::_revalidate(), process to be raised
segments *before* segments that can be reduceds.
* New: In Hurricane::Layer, add support for a minimal area (given in
microns). Exported in the Python interface.
* New: In Anabatic::AutoSegment::bloatStackedStrap(), method to
enlarge too small vertically stacked VIAs. For now just create
a square ensuring the minimal area. Potentially cause DRC error in
some cases so needs to be refined.
* New: In Anabatic::_gutAnabatic(), check for too little stacked VIAs
and display a report.
* New: In cumulus/plugins/chip.corona.HorizontalRail & VerticalRail,
use the new BigVia instead of StackVia to generate a matrix of
cut when in real mode. Stick to the one massive VIA when in
symbolic.
* New: In cumulus/plugins/block.bigvia.BigVia to generate matrixes
of cut VIA.
* Bug: In CRL::GdsDriver::hasLayout(), a Cell was saved in the GDSII
stream only if it has a layout, but the check was not accurate
enough. In the Arlet6502, the whole core was missing.
Now check for the abscence of Plugs (not unfinished Nets) and
PLACED/FIXED instances.
* Change: In documentation/build.py, more PEP8 & Python 3 future compliance.
Correct copy of the tools HTML docs on my laptop, to have a full
offline copy of the doc.
* New: In documentation/contents/pages/check-toolkit, duplicate the doc
from alliance-check-toolkit README. Seems it has been inadvertently
removed at some point (?). Have to be careful to maintain in synch
with the toolkit.
* Change: <tool>/doc/*/SoC.css, use Roboto fonts when availables.
* Update: Commit the whole pre-generated docs (Doxygen, Pelican).
* Bug: In CRL/GdsStream::toGdsDbu(), when converting a physical number,
in double to a number of GDSII dbu in int32_t, we must not use the
direct cast int32_t(v) because v can be 2.9999999999 which got
simply truncated into 2 while we want 3. So now use the rounding
function std::lrint() and configure it round to the *nearest*
integer.
Note that we don't check that the long returned can correctly
fit into int32_t.
* New: In cumulus/plugins.block.configuration, added class ConstantsConf
to store information and create instances of "zero" and "one" cells.
Added attribute in BlockConf class.
* Change: In cumulus/plugins.block.configuration, moved the cell cloning
and saving from block.spares.Spares to configuration.BlockConf as
it is a service that can be used by other modules than just spares.
Other modules may modificate the netlists also, like in XXXX.
* Change: In cumulus/plugins.chip.configuration, in various methods,
manage both cases when the layer is symbolic or real (difference
in accessing the underlying BasicLayers).
* Change: In cumulus/plugins.chip.configuration, less clutered display
of lambda length in trace mode (and use of 'L' as 'l' was too close
to '1').
* Bug: In cumulus/plugins.chip.corona.VerticalSide.addBlockages(),
as the clock are now on the *inner* rail(s), blockage must be on
the *outer* rails (power lines).
* New: In cumulus/plugins.chip.pads.Corner, add support for 45 degree
corners (cfg setting "chip.use45corners").
* New: In cumulus/plugins.chip.pads.Side.check(), correct computation
of the side's length. Was using the ioPadStep instead of the pad
cell width!
* Change: In cumulus/plugins.chip.pads.Corona._padAnalysis(), LibreSOCIO
pads uses Verticals for their ring wires (common sense would want
them *Horizontal*). So they must be included in the physical pin
detection, but in turn this cause havoc in pxlib... So create a
filtering according to the library name. This is *not* robust
but will do for now.
* New: In cumulus/plugins.chip.pad.core2chip.CoreToChip, rename
self.state into self.conf for clarity.
New method newEnableForNet(), to create "enable" nets on the
fly for emulated In/Out pads.
As it can edit the netlist (new "enable" nets) call the
BlockConf.rsave() method instead of direct saving through
AllianceFramework.
Raise NotImplementederror instead of ErrorMessage.
* New: In cumulus/plugins.chip.pad.core2chip.IoPad.createPad(),
on emulated In/Out I/O pad like for LibreSOC, generate on the fly
the right enable signal.
If an enable signal is given, it will be used (backward
compatible with the previous behavior).
* New: In cumulus/plugins.chip.pad.core2chip, support for real
LibreSOCIO pads in libresocio.py module.
* New: In cumulus/plugins/core2chip/, support for the FlexLib I/O cells
symbolic abstracts ("niolib"). More flexible way of specifying the
number and positions of the various power pads, both I/O power and
core power.
For niolib (FlexLib I/O abstract), support for multiple clocks,
that is, clock become ordinary pad (with signals typed as CLOCK).
* New: In cumulus/plugins/chip/, added support for niolib and final
integration of multiple clocks (only for niolib).
* Change: In CellWidget::drawGrid(), for the "super-grid", now use
lines instead of small crosses. The super-grid is set to 10 point
of the snap grid in all cases (symbolic, real, foundry grid).
* New: Export CellWidget::setDbuMode() to CellViewer, and into it's
Python wrapper.
* Bug: In CellWidget::setCell(), keep the dbuMode when loading a new
cell instead of reverting to default.
Note: The previous strategy was not fully coherent in chip mode.
Everything added, net and components must be added at
corona level and not separated between corona and core.
* New: In cumulus/plugins/block.configuration, new FeedsConf object
to handle the feeds and provide a filling area helper.
* New: In cumulus/plugins/block.spares.removeUnusedbuffers() to
remove unused buffers in the pools and replace them by feedthrough.
* Change: In cumulus/plugins.block.spares, unify coordinate/slice
computation. If we are in chip mode, the coordinates are
expressed in the corona *but* aligned on the slices of the
*core* model.
* Change: In cumulus/plugins.block.Block.rsave(), add the '_r' suffix
to the routed cells.
* Change: In cumulus/plugins.clocktree.ClockTree, when in chip mode
create everything at corona level. Also forgot to set type of
clock subnet as clock.
Note: To implement this in a more flexible way we should introduce a
concept of Instance/Cell "placeholder" to reserve space
transhierarchically.
* Change: In EtesianEngine::toColoquinte(), when placing only one block
in a cell, the cell itself can contains other fixed instances
that are over the placement area. Create dummy fixed instances
to reserve the taken space.
In EtesianEngine::AddFeeds(), do not put feed cells over the
cell area occuped by the sibling instances cells.
* Cleanup: In KatanaEngine::setupPowerRails(): small cleanup.
* Change: In CRL::vstDriver(), remove all Vhdl properties after running.
The properties are not updated if the cell (Entity) change, so the
next time it is called, an incomplete or incoherent state was saved
(for example, incomplete "port map"). Removing all properties is
less efficient but works.
* Cleanup: In CRL/helpers/overlay, remove forgotten debug message.
* Change: In Cumulus/plugins/block/spares, check that "block.spareSide"
is not below 7*sliceHeight and issue a warning instead of a later
divide by zero...
* Change: In CRL/etc/common/etesian.py, use double parameters
instead of percentages to simplify. For space margin and form
factor. This need the rewrite of coriolis2/settings.py in
alliance-check-toolkit.
* Bug: In CRL/helpers/overlay.CachedParameter.cacheRead(), values where
not read *from* the Configuration DB, due to a forgotten "self.".
In CRL/helpers/overlay.CfgCache.__setattr__(), value was simply
never set! Only interval and set of values were manageds!
In CRL/helpers/overlay.CfgCache.__getattr__(), must distinguish
between two access cases, when were are truly accessing a
CachedParameter, return it's *value*. Otherwise, it is a
recursive CfgCache, then return the object.
Jean-Paul Chaput
Staf Verhaegen