* Change: In Etesian::Slice::fillHole(), instead of cramming the home
with tix_x0 only, put one tie at both ends and fill the rest
with fill_x0. This should help the vendor density filler to
equalze.
* New: In Etesian::Configuration, add the parameter:
"etesian.tieName" (for tix_x0) as it now separate from the simple
filler cells.
* In Etesian::BloatFlexLib::getDx(), expand the "mx2_x2" of one more
pitch (2 instead of 1). The P&R was unable to allocate a critical
diode under a slice that was littered with those cells in LS180.
The H-Tree support is now allowed for any net, not only the clocks and
not only top-level nets. This allow to better management of the LS180
internal clock signal.
* New: In Cell::flattenNets(Instance*,set<string>,uint64_t) new overload
of the function to allow the user to select nets that will *not*
be flattened. This makes the NoClockFlatten flag effectively obsolete,
we keep it for backward compatibility.
The net names can be of non top level ones. In that case, they must
use the name an HyperNet will get (the Occurrence name). For example:
"instance1.instance2.deep_net_name".
* New: In PyCell, update the wrapper for the new parameter of flattenNets(),
new utility function pyListToStringSet() to translate a Python list into
a C++ set of names.
* New: In EtesianEngine, add support for a list of nets to be excluded
from the flattening procedure. Those excluded nets will also be
excludeds from the Coloquinte nets *and* HFNS synthesis, as they
are likely to be manageds by a H-Tree.
* Change: In AnabaticEngine::_loadGrByNet(), now also skip nets that are
flagged as manually detailed route.
* New: In AnabaticEngine::antennaProtect(), do not try to insert diodes
on nets that are already fixed or detaled route. This replace the
clock exclusion.
* New: In cumulus/plugins.{block,htree,chip}, replace the concept
of clock-tree by the more generic H-Tree. That is, we can ask the P&R
to create H-Tree on any net of the design, not only the ones matcheds
as clock. The net does not even need to be top-level.
This is to manage the PLL internal clock generated by the PLL in
the LS180 chip.
Start to change all reference to "clock" into "H-Tree".
* Bug: In cumulus/plugins.chip.powerplanes.Builder._connectHTree(),
there was an inversion of the H & V routing gauges to compute the
track into which put the H-Tree center to corona edge wiring.
This was causing tracks to be used twice, seen in the ao68000 test
bench.
Split "antennaMaxWL" into :
* "etesian.antennaGateMaxWL" : max length *without* any diode.
* "etesian.antennaDiodeMaxWL" : max length that *one* diode can support.
* In Etesian::Slice::createDiodeUnder(), delete the Instance *after*
removing the tile referring it. This was working, unless we
active the debug mode which tries to print the Tile's instance.
* In EtesianEngine::place(), no longer call toHurricane() at the
end of the placement. Must now be done as a separate step.
Exported to Python interface.
This fix is related to the spare buffer removal memory
corruption
First part of the antenna effect protection : diode insertions.
Anabatic::antennaProtect(Net*) and it's supporting infrastructure
has been rewritten & simplificated. Must be used in conjuction
with the "Flexlib" bloat model of Etesian. A cursory description
of the algorithm has been added in the source file.
* New: GCell::hasNet() to tell if net is going through a GCell,
either as a straigth wire or has a local GContact (turn,
branch, terminal).
* New: Etesian::BloatFlexib class (tagged "Flexlib") suited for
flexlib uses. It is derived from "nsxlib".
To have enough space to insert all the wanted diodes, we
enlarge "mx2_x2" & "mx3_x2" of resp. 1 and 2 pitches.
This is an empiric finding, Yosys seems very fond of thoses
gates and we often see them underneath area where no space
was available to put a diode... May need some more fine grained
analysis.
* Bug: In Etesian::HFNS::Cluster, all the created nets were systematically
created in the IN direction, which is obviously wrong for the driver.
Now Slice::raddTransPlug() accept a third argument stating if we are
creating a driver or a sink. Direction of the net is now combining
and can be IN, OUT or sometimes INOUT.
The VHDL files where reflecting that problem and made GHDL choke.
* Change: In Etesian::HFNS::Cluster, prefix the instance name by "cmpt_"
so it doesn't clash with the signal name in VHDL.
* Bug: In Etesian::Placement::Slice::fillHole(), do not use the xmin
previous bound, but pitch it (by excess). Insert ties *only* if
they completely fit in the free space.
This bug was showing *between* two SRAMs side-by-side, a column
of tie was inserted...
* New: In AutoSegment::getExtensionCap(), when a routing layer has a
minimal area defined, compute the minimal wire length (given it's
width). Then, for segments identified as "MiddleStack" (local
with turns at each end towards opposite layers), if their length
is below minimal, return a longer extention cap.
This may be optimized because with this, the segment extension
is symmetric on both side while it could be made assymetric.
* Bug: In EtesianEngine::toHurricane(), when looping over the AB of all the
FIXED instances occurrences, we where excluding contained AB instead of
merging them...
* New: In EtesianEngine::flattenPower(), this is a duplication of the
KatanaEngine::PowerRails. The new paradigm is that when a Cell
is placed by etesian it's AbstractedSupply flag is set and the
creation of the abstract is taken care of at this point.
Should provide some speedup when Katana process it.
Note that we still need to keep PowerRails at Katana stage for
design that are loaded already placed (no Etesian run).
* New: In EtesianEngine::setPlaceArea(), as the slice spin is imposed
on us by Coloquinte, the bottom slice of the place area *must*
be on a ID oriented slice, that is an even one, relative to the
fully placed area.
* Bug: In EtesianEngine, remove the slice spin detection. The spin
is imposed on us by Coloquinte which always place the bottom
row in ID orientation.
Code should be completly removed in the future, along with
the obsolete AddFeeds (replaced by Placement).
* New: In EtesianEngine, add a "placedArea" attribute to restrict the
placement area to a part only of the whole abutement box. This a
way to exclude some area containing *big* hard block.
The placer terribly slow down when tring to "push aside" cells
from the area taken by the block.
This will be also used to restrict the clock tree covered area.
It is far from optimal but will do for now.
NOTE: The placeArea must be expressed in the coordinate system of
the sub-block to be placed, if one has been defined.
* Change: In EtesianEngine::globalPlace(), disable the call to
antennaProtect(). First reason is that, after all, Coloquinte
do not handle so well the resizing of the cells "on the fly",
it overspill the boundaries sometimes. Second reason is that
as we cannot know the routing tree at this stage, we will not
be able to choose the correct points for diode insertions.
We only have a Steiner tree wich may not be the same as a
density driven Dijkstra.
* Change: In Etesian::Area, the Occurrence to the Instances where
not stored in a uniform way. Some where starting from the
placed sub-block, some where starting from the top level
(corona), making their processing (and remembering it) tricky.
Now, they are all expressed from the top cell (corona).
The coordinate system is now systematically the one of the
top block (*not* the block).
Create various overloaded functions EtesianEngine::toCell()
and EtesianEngine::toBlock() to ease Occurrence & coordinate
translations.
* New: In Etesian::Slice::createDiodeUnder(), add a X position hint.
Search is done by going through the whole slice range and
minimizing the distance to the hint. If it starts to be too
slow, we may optimize.
* Bug: In EtesianEngine::toColoquinte(), the placement of the top
level external pins was not taken into account (this at last
explain their weird positioning).
* New: AnabaticEngine::antennaProtect(), new algorithm to avoid
antenna effect. This step must be done *after* global routing
and *before* detailed routing. This way we have access to the
real routing and can mend it (along with the netlist) to
insert diodes at the rigth points.
From the global routing we build clusters (DiodeCluster) of
RoutingPads connected through a set of wire whose total length
is below the antenna effect threshold. Long wires connecting the
clusters are also tagged because we need to put a diode between
them and the first RoutingPad of the cluster. This is to avoid
a long METAL2 wire connecting to the RoutingPad before the diode is
connected through METAL3 (in case of misalignment).
This protection is not even enough. For *very long* wires, we
needs to put *more* than one diode (this is to be implemented).
* New: In Etesian::Configuration add new parameters for antenna
effect management:
* "etesian.diodeName" : the name of the diode cell.
* "etesian.antennaMaxwl" : maximum length above which antenna
effect can occur. Must be the maximum for all the normal
routing layers.
* "etesian.antennaInsertThreshold" : during the placement steps,
threshold for linear disruption at which we will look for
the RSMT and insert diodes.
* New: In EtesianEngine::antennaProtect(), at a designated point
in the placement iteratives step, when the spreading starts to
be significant enough estimate the RSMT length and add a diode
if need be. The diode will be put side by side with the driver
cell. This is done by enlarging the driver cell of the diode
width.
* New: In EtesianEngine::_updatePlacement(), in the final stage,
modify the netlist to connect the diode. The diode will be
put on the side of the cell closest to the driver. This may
alow to make the connexion directly in METAL1 in the future.
* Change: In etesian/Placement.cpp, make the whole placement
structure a persistent attribute of the EtesianEngine so
it can be used afterwards.
Add a post-placement diode insertion feature. Finally
unused as they are added on the fly during placement.
In the Area, add data about the diode tie in the TieLut.
* Change: Add EtesianEnginea::clearColoquinte(), to keep the
post-placement structure while purging the Coloquinte one.
* Change: In cumulus/plugins.block.block, keep the Etesian engine
until the whole P&R is done, so we potentially can exploit
the post-placement datas.
* Bug: In cumulus/plugins.chip.power.GoCb(), for the METAL1 power
and ground wires coming from the standard cell, it was assumed
they where made of Horizontal segments, this is not the case
in FlexLib... So force to consider the plane as Horizontal when
we are processing that plane.
Better solution should be to use Horizontals...
* New: In Etesian/Placement::Area, added support to take into account
bulk inside cells. Currently only hard-wired configuration for
FlexLib is available. Should add a front-end to analyse the
cells of the library to lookup for bulk ties in the future.
* New: In Etesian::Configuration, added "etesian.lacthUpDistance" to
control tie cells insertion (for polarization contacts).
* New: Etesian/Placement as a complete replacement for FeedCells.
Rebuild the complete slicing structure of the placement to
serve as a building block for post-placement changes under
Coriolis. Currently used to regularly insert body ties.
This is not optimal as we displace cells in each slice in
a non-coordinated manner.
* New: In cumulus/plugins/block.configuration.FeedsConf, register
the "etesian.latchUpDistance" parameter. Provides the tie width.
* New: In cumulus/plugins.block.spares, add ties around the buffer
pool block and "cap ties" at both end of each slice.
* Change: In EtesianEngine, V-Pitch and H-Pitch are now initialized
from the Cell gauge "slice step". It may still be best if the
METAL2 routing grid is still a fractional ratio of the cell height.
Note: To implement this in a more flexible way we should introduce a
concept of Instance/Cell "placeholder" to reserve space
transhierarchically.
* Change: In EtesianEngine::toColoquinte(), when placing only one block
in a cell, the cell itself can contains other fixed instances
that are over the placement area. Create dummy fixed instances
to reserve the taken space.
In EtesianEngine::AddFeeds(), do not put feed cells over the
cell area occuped by the sibling instances cells.
* Cleanup: In KatanaEngine::setupPowerRails(): small cleanup.
* New: Added multiple clock support in H-Tree generation in alpha/block.
* New: In CRL/etc/<NODE>/<TECH>/plugins.py, added three new parameters
for block plugin config:
"block.spareSide" : The size of the minimum side of a buffered area.
(quad-tree leaf).
"spare.buffer" : The model of the cell buffer to be used.
"spare.maxSinks" : max number of sinks on a buffer before issuing
a warning (non-blocking).
* Bug: In Etesian::BloatCell::getAb(), never apply the bloat profile to
fixed cells. In case of buffers from the spare maxtrix it was leading
Coloquinte to detect an overlap of fixed cells, which it do not
support (rightly so).
* Bug: In Etesian::toColoquinte(), inadvertently stopped taking into
account fixed instances... Compute correctly the number of
instances to place (all instances minus fixed ones..).
* New: In EtesianEngine::toColoquinte(), fixed blocks must not be
accounted as instances to be placed.
When, there is no instances to place, just issue an error message
and return.
* New: In EtesianEngine::setDefaultAb(), add computation of AB when
using fixed width (fixed height) was already available.
Add attribute management for the fixed width along with a
Python export.
* Bug: In EtesianEngine::place(), reset the placement *only* if we are
*not* placing a sub-block *and* the top cell abutment box is empty.
* Bug: In EtesianEngine::place(), set the instance placement status of
all intermediate instances to PLACED, so the AP driver will save
them (we were having partially saved layout when using hierarchical
designs).
* Bug: In EtesianEngine::resetPlacement(), reset the PLACED flag and
the abutment box on the top cell or sub-block to be placed.
* Change: In CRL::LefParser::_macroCbk(), create a Catalog entry for the
newly read MACRO (that is Cell) and sets the Logical, Physical,
InMemory and TerminalNetlist flags.
* Bug: In CRL::LefParser::_siteCbk(), check for NULL cell gauge.
* New: In CRL::AllianceFramework, add setCellGauge(), to set the default
cell gauge. Exported to Python.
* Change: In CRL/etc/common/technology.py, create variables for VIA
layers, so we can modify their properties afterwards.
* New: In CRL/etc/node45/freepdk45, port the configuration files to the
new Python "importable" format.
Note: in kite.py, all the gauges (Routing & Cells) must be named
"LEF.CoreSite" to please my LEF parser, so it can match the gauge
name with the SITE name for standard cells.
* Bug: In Anabatic::NetBuilderVH::_do_2G(), forgotten to be reimplemented
from the base class. Simply redirect to _do_xG().
* Change: In Katana::PowerRailsPlanes::PowerRailsplanes(), create plane
from the layers in the RoutingGauge and their associated blockages
instead of sweeping through all the basic layers.
Allow to distinguish bewteen "METAL" (symbolic) and "metal" (real).
* Bug: In CRL::VstParserGrammar & VstParserScanner, when loading the
instances models, we where loading both logical & physical views.
This was causing cases of reentrency of the parser, with reset
of the lexer static dictionary, leading to memory corruption.
Now the identifiers are stored in the YaccState of each
parsed cell and we only recursively call for the logical view.
* Change: In CRL::ApParser::_parseInstance(), recursively load the
physical views as they are no longer loaded by the Vst parser.
* Change: In CRL::AllianceFramework::getCell(), sets the
TerminalNetlist flag from the state (mode 'C' in CATAL) onto
the cell.
* Change: In EtesianEngine::loadLeafcelllayouts(), new functions to
load the layouts of the leaf cells if only the netlist has been
loaded.
In the Cell/Instance hierarchy, the "terminal" and "leaf cell" concepts
where not clearly defined and partially overlapping. Now, "Terminal" is
the refer to the physical hierarchy (layout) and "TerminalNetlist" to
the logical hierarchy (netlist). The logical hierarchy can be less deep
than the physical one thanks to a Cell dedicated cell flags. Collections
related to the physical hierarchy keep their old names, the one related
to the logical hierarchy are renamed from "Leaf" to "TerminalNetlist".
The name "Leaf" was too ambiguous (leaf for *what* hierarchy).
* Change: In Hurricane::Device, set the "TerminalNetlist" flag once and
for all. No need set it in all the derived classes again.
* New: In Hurricane::MultiCapacitor, added new parameter "dummy" to
create dummies around the capacity matrix.
* Change: In Hurricane::Cell, remove "Leaf" related methods, replace
them by "TerminalNetlist" one, especially Collections. Now we have
two clear sets of Collections to walkthough the layout or the
netlist.
Change the "Terminal" flag into "TerminalNetlist".
* Change: In Hurricane::CellCollections, rename "Leaf" into
"TerminalNetlist" collections and apply the new semantic to the
locators.
* Change: In Hurricane::DataBase, Leaf to TerminalInstance renaming.
* Change: In Hurricane::DeepNet, Leaf to TerminalInstance renaming.
* Change: In Hurricane::HyperNet, Leaf to TerminalInstance renaming.
* Change: In Hurricane::Instance, Leaf to TerminalInstance renaming.
* Change: In Hurricane::Viewer::HierarchyInformations, Leaf to
TerminalInstance renaming.
* Change: In CRL::AllianceFramework, Leaf to TerminalInstance renaming.
* Change: In CRL::Catalog, Leaf to TerminalInstance renaming.
* Change: In CRL::ApParser, Leaf to TerminalInstance renaming.
* Change: In EtesianEngine::AddFeeds, Leaf to TerminalInstance renaming.
* Bug: In EtesianEngine::resetPlacement, move there the loop over
non terminal netlist instances to flag fully placed sub-blocks
as terminal for the netlist. Only then remove the feed cells
from unplaced instances. Previously, the feed cells where stripped
even from already placed instances.
* Change: In Katana, Leaf to TerminalInstance renaming.
* Bug: In Bora::PyDSlicingNode, allow the range parameter to be the
Python None object when we do not want to pass one but need to
have it as positional parameter.
* Change: In Cumulus/clocktree/ClockTree.py, Leaf to TerminalInstance
renaming.
* New: In Hurricane::Cell::isLeaf(), a leaf cell was defined as one
without instances. Now it can be software defined with the
"FlattenLeaf" state. If it is flagged "flatten leaf" is will be
considered as a leaf by the trans-hierarchical walkthrough.
This flag is also set for Cells in the Alliance CATAL.
* New: In Hurricane::Cell_LeafInstanceOccurrences::progress(), add a
test to prune leaf cells.
* Bug: In Hurricane::getComponentOccurrences(), when calling the
locator constructor, the "withLeafCells" argument was forgotten
and was getting the value of "doExtraction" (wich, fortunately,
was the same).
* Change: In Hurricane::HypreNet_LeafPlugOccurrences::progress(),
prune the leaf cells instead of the terminal ones.
* Change: In Hurricane::HypreNet_ComponentOccurrences::progress(),
prune the leaf cells instead of the terminal ones.
* New: In Hurricane::Cell, add a "useFlattenLeaf" mode to take into
account or ignore the "FlattenLeaf" flag when doing trans-
hierarchical walkthrough.
Not sure if it shouldn't be systematic.
* New: In Etesian::toColoquinte() and other, activate the "FlattenLeaf"
mode for all walkthough. So we can stop at already placed sub-blocks.
* Bug: In Etesian::toColoquinte(), when placed sub-block where present,
the number of instances was under estimated, so the instance array
was oversized and the end went unitialized. So we were getting all
kind of strange behavior from Coloquinte...
Now throw an exception if the number of instances differs from
the computed size.
* Bug: In Etesian::toColoquinte(), as for the instance array, now
correctly compute the size with the ecluded nets (supplies, clocks).
* Bug: In Etesian::resetPlacement(), event if the Cell is unplaced,
go through the instance list to remove the potential feed cells.
The netlist is written back after placement *with* the feed
cells added. So, when loading again, they where cluttering the
netlist and giving feed redefintions warning. They also generated
erratic behaviors.
* New: In Anabatic::NetBuilderHV, added configurations for:
* 1G_1M1_1PinM3
* 1G_xM1_1PinM2
* 2G_xM1_1PinM2
* doRp_AccessNorthPin
* New: In Anabatic::NetBuilderHV, added Pin management in SingleGCell.
* Bug: In Anabatic::NetBuilderHV::_do_xG_1PinM3(), the North/South
global routing configuration was forgotten (only East/West).
* Bug: In Katana::TrackFixedSegment, the blockage net was a static
variable initialized at the first run. So we were getting stuck
with the blockage net of the first cell to be routed. Of course,
it did show only when Katana was run multiple times in the same
process.
* New: In CRL/etc/node600/phenitec, ported configuration of Phenitec 0.6um
Compliant with DataBase reset.
* New: In CRL/python/helpers, added function "unloadUserSettings()" to
unload Python modules prior to a full reset.
Added "resetCoriolis()" to perform full DataBase reset.
* Change: In CRL::AllianceFramework, make it a derived class of DBo so
the destroy() is now provided.
* Bug: In CRL::AllianceFramework::getCell(), do not attempt any load if
the library list is empty. Should never occur except in case of a
botched databse reset.
* New: In CRL::AllianceFramework, new method "saveCATAL()" to write back
the catalog of a library and "saveCells()" to write back the cells.
Note: only cells actually loaded in memory will be write back.
* New: In CRL::Catalog, add method "saveToFile()" to write back the CATAL
of a library.
* Change: In CRL::ParserDriver, replace "const string&" by "string"
(improved string support of the GNU STL).
* Change: In CRL::ParserSlot, use string instead of Name.
* Change: In CRL::ApParser, make _layerInformation an ordinary attribute
instead of a static one. This allow for it's correct resetting
across databas resets.
* Change: In CRL::VstParserGrammar, reinitialize Vst::framework at each
parser call. Needed to support database reset.
* New: In Hurricane::DBo, add an object counter to be sure that when
we perform a reset, no remaining DBo is allocated. This is different
of the object id which is ever increasing.
Note that, at reset, we check against "1" remaining element as at
this point only Database is still allocated.
Add a new "resetId()" method. MUST NEVER BE CALLED except by
DataBase::_preDestroy().
* New: In Hurricane::Database, new clear() method to remove the Cells
of all the libraries in reverse hierarchical depth order.
Make use of the new CellsSort class.
* Change: In Hurricane::DataBase::_preDestroy(), call "clear()" and
DBo::resetId().
* Change: In Hurricane::Breakpoint, change the default callback to be
a static function. So we can restore it later.
* Bug: In Hurricane::Instance::_preDestroy(), there was yet another
loop of deletion over a collection for the shared pathes.
Replace it by the repetitive deletion of the first element.
* Bug: In Hurricane::Net::_preDestroy(), RoutingPads must be destroyed
prior to any other component.
* New: In Hurricane::ColorScale, add a "qtFree()" method for freeing
the Qt Brush, Pen & Color.
* New: In Hurricane::DrawingStyle, add a "qtFree()" method for freeing
the Qt Brush, Pen & Color.
* New: In Hurricane::Graphics, add a "disable()" method to call the
various "qtFree()" of the sub-objects.
* Change: In bootstrap/FindBoostrap.cmake, remove the -fsanitize=address
as it requires the "san" librarie which may be difficult to install.
* Change: In CRL/symbolic/cmos45/kite.py, decrease the METAL3 pitch from
10l to 8l. This is for testing with 4 routing metal only technology
like AMS c35b4 symbolic.
* Change: In Katana/BloatProfile, add static bloat option, that is, only
cell bloated in the first pass will be bloated again in subsequent
ones.
Add a "katana.bloatOverloadAdd" parameter to more easily control the
amount added to the computed overload.
* Change: In Oroshi, start integration of multi capacitors as generator.
Translate generator parameter into CapacitorStack ones. Add code for
routing unit capacitor.
* Change: In Hurricane::Viewer::ExceptionWidget & CRL/python/helpers/io.py,
downscale icons for non-HiDPI screen.
* Change: In CRL/etc/common/display.py, change the display threshold of
METAL1 layer so it do not appear at high scaling.
* New: In Etesian, activate the "setFixedAbHeight()" feature and export it
to Python. Allows to increase the space margin at constant height.
To be used by the P&R conductor.
* Change: In Unicorn/cgt.py, when running a script, insert the current
working directory at head of the sys.path, not at the end. So installed
modules do not shadow local one.
* New: In Anabatic::Edge, new accessor "getRawcapacity()" to know the full
capacity of the edge, that is, the real maximum number of tracks that
can go through the associated side.
* Change: In Katana/BloatProfile/Slice::tagsOverloaded(), bloating policy
change, now bloat all the instances under the GCell, not only the first
one.
* Change: In KatanaEngine::runGlobalRouter(), restore the search halo growth
policy to expanding of 3 GCells every 3 iterations.
New metrics displayed, the edge wire length length overload.
* Change: In cumulus/plugins/ConductorPlugin.py, now accepts the following
configuration parameters:
- "anabatic.globalIterationsEstimate", maximum number of global
iterations during the bloating computation passes.
- "conductor.useFixedAbHeight", tells wether the additionnal blank
space must be added so the aspect ratio is kept or the height is
kept (and the block become wider).
Disable the display of "rubber" to unclutter a little the view.
This commit contains two set of features that should have been commited
separately.
1. Compliance with clang 5.0.1, tested with the RedHat collection
llvm-toolset-7. This allow Coriolis to be compiled under Darwin (MacOS)
with Xcode & macports. The bootstrap install system has been modificated
accordingly.
2. The basic support for routing density driven placement. Related
features are:
* Bloat property. Each Occurrence of an Instance can be individually
bloated. This property not attached to any tool to allow the placer and
router to share it as wanted. Nevertheless, it is defined in Etesian.
* BloatProfile in Katana, add individual Bloat properties to Instances
occurrences based on the East & North overflowed edges of each GCell.
* Support in ToolEngine for a "pass number" of a tool. This pass number
is mainly used to make "per pass" measurements. The MeasureSet system
is improved accordingly to support multiple values of a same measure.
* Embryo of "P&R Conductor" to perform the place & route loop until the
design is successfully placed. May be the first brick of a Silicon
Compiler.
* Change: In boostrap/FindBoostrap.cmake, in setup_boost(), added tag to
the python component for macport (ex: python27).
* Change: In boostrap/build.conf, put etesian before anabatic for
instance occurrence BloatProperty dependency.
Added option support for the "llvm-toolset-7" collection to build
against clang 5.0.1.
* Bug: In Hurricane::getRecord( const pair<T,U>& ), the getSlot<> templates
for first & second arguments must be called with <const T> and <const U>
as the pair itself is const (and not simply <T> & <U>).
* Change: In Hurricane::getSlot() temlate, only use "string" arguments and
not const string&, simpler for template argument deduction.
* Bug: In Hurricane::AnalogCellExtension, the StandardPrivateProperty<>
template has a static member "_name". Clang did show that the template
for this static number has to be put inside the namespace where the
template *is defined* (i.e. Hurricane) instead of the namespace where
it is instanciated (i.e. Analog).
* Bug: In Isobar, Matrix_FromListOfList(), PyInt_AsPlacementStatus() must
be put outside the C linkage back in the Isobar C++ namespace (clang).
* Bug: In Hurricane::DBo::~DBo, and derived add a throw() specification
(clang).
* Bug: In Hurricane::RegularLayer::getEnclosure() & setEnclosure(), change
signature so it matches the one of the base class (clang).
* Bug: In Hurricane::CellPrinter, use double brackets for initializer list
(clang).
* Change: In Hurricane::Breakpoint, reverse the meaning of the error level.
Only error level *lesser or equal* than the stop level will be enabled.
* Bug: In CRL/python/helpers/__init__.loadUserSettings(), must put the
current working directory in the sys.path as in certain configuration
it may not be included.
* Bug: In CRL::ApDriver, DumpSegments(), no longer generate segments when
encountering a RoutingPad on a top-level Pin Occurrence. The segment
was generated in the wrong direction, creating DRC violations on the
"mips_core_flat" example.
* Change: In CRL::Measures, partial re-design of the measurements management.
Now, each kind of measure can accept multiple values put in a vector.
The index is intented to match a tool run number.
* Change: In CRL::Histogram, add support for multiple sets of datas,
indexeds with tool run number.
* Change: In CRL::ToolEngine, add support for multiple pass number, add
addMeasure<> templates for the various data-types.
* Change: In CRL::gdsDriver & CRL::gdsParser(), comment out unused GDS record
name constants.
* New: Etesian::BloatProperty, property to attach to Instance occurrences
that contains the extra number of pitch to add to the cell width.
* Bug: In AutoSegment::CompareByDepthLength, the segment length comparison
was wrong, it was always returning true, which broke the "strick weak
ordering" of the comparison.
This was producing a core-dump in GCell::updateDensity() when sorting
a vector<>. The end() iterator was being dereferenced, leading to the
problem.
* Bug: In Katana::DataSymmetric::checkPairing(), the test for segments
whose axis is perpandicular to the symmetry axis was wrong
("!=" instead of "-").
* New: In Katana/GlobalRoute, new ::selectSegments(), selectOverloadedgcells()
and selectBloatedInstances() to automatically select segments from
overloaded edges, overloaded GCells and bloated cells.
* Change: In KatanaEngine, return a more detailed success state, distinguish
between global and detailed.
Add support for multiple routing iterations.
* New: In cumulus/python/plugins/ConductorPlugin.py, embryo of routing
driven placement.
* Bug: In EtesianEngine, it was using the vertical track pitch from the
routing gauge, but it may differ from the cell pitch. For example in
"cmos350" the cell step is 10 lambdas while the vertical routing
pitch may be only 8 lambdas.
This bug shows because now we try to use the non-PinOnly routing
gauge for the reference routing gauge.
* Change: In Hurricane::Isobar/PyHurricane.h, make the hash function use
the DBo id whenever possible instead of the object pointer, fall back
to it for standalone objects (Box like one). The DirectHashMethod()
macro generate a C style function (linkage) which call a template
function "getPyHash<>()" that uses a SFINAE mechanism to select
the right variant.
Create two comparison macros DirectCmpByPtrMethod() and
DirectCmpByValueMethod() to customize the comparison for objects that
have C++ operator==(). So now two boxes with the same contents will
be seen equal by Python. For DBo objects we keep the previous
comparison by C++ pointer.
* Bug: In Katana::SegmentFsm CTOR, when computing costs for METAL2 in
non-preferred direction attached to METAL1 terminals, do not try to
align on a METAL3 track, as there may be not. Especially when the
METAL3 pitch is not multiple of the METAL1 one.
Compute at least one cost (with the same axis as the vertical METAL1
terminal).
* Change: In Etesian::BloatCells, adjust the "90%" bloat profile for a
METAL3 pitch of 8 lambdas (sligh decrease).
* Bug: In cumulus/plugins/ChipPLace.py, import chip.Chip, not only chip.
* New: In Etesian::BloatCells, new profile for hihgly saturated designs named
"90%", as it add, on average, 90% of free space. This has been made for
the "ao68000" of Staf Verhaegen and may needs some refinement as it is a
bit brutal.
This commit degrades the run success rate of ARMv2a to 87% (40 iters).
* New: In CRLcore/etc/.../kite.conf, add configuration parameters:
katana.termSatReservedlocal
katana.termSatthreshold
for the new edge capacity computation system.
* New: In CRLcore/etc/symbolic/phenitec06/, add support for N. Shimizu
small I/O pads (supplied in phlib80). Tune various parameters of
Anabatic/Katana to increase routing success.
* Change: In CRLcore/alliance/ap/ApParser, make Pin external components,
so RoutingPad will be build upon in global routing.
Do not complain when a I/O pad has a physical instance that did
not exists in the netlist. Just create it (appeared in phlib80).
When no netlist instance exists in a pad, the pad Cell is still
considered as terminal.
* New: In Etesian::BloatCells, new profile named "3metals" better suited
for two routing metals technologies (i.e. Phenitec).
* New: In Anabatic::RawGCellsUnder, new CTOR which take only source &
target points instead of a segment. Needed to manage wide segment for
which the axis to consider is not that of the segment (one axis for
each track it intersect).
* New: In Anabatic::GCell, add a RoutingPad count attribute, for Edge
reservation computation.
* New: In AnabaticEngine::computeEdgeCapacities(), instead of decreasing
all edges of a fixed amount (hTrackReservedLocal), guess the GCell
cluttering from the number of RoutingPads that it contains.
For non-saturated GCells, the four edges are decreased by the number
of RoutingPads. We use the maximum from the two neigboring GCells.
The hTrackReservedLocal parameter is now used only as a *maximum*
that the edge reservation can reach.
If a GCell is saturated (more than 8 RoutingPads, the saturation is
propagated horizontally to 2 neigboring GCells).
* Change: In AutoContactTerminal::getNativeConstraintBox(), use a more
flexible gauge name matching for terminal vertical extensions correction.
Namely, match all "msxlib*" kind of gauges.
* Change: In AutoSegment::setAxis(), add the ability to force the axis
position, even if it is a non-canonical segment. Maybe needed in the
initialisation steo, before the first canonisation is performed.
* New: In NetBuilder, added new methods _do_1G_1PinM1() and _do_2G_1PinM1(),
to manage coronas for Phenitec designs.
To avoid various side effects from segments being too close from
the north / east side of the routing area, make those segments fixeds.
* Change: In KatanaEngine::annotateGlobalGraph(), the management of wide
wires was wrong. The axis to use to find the underlying GCells is the
one of the track, not of the segment. This was creating bad edge
capacity computation under the power ring of a block and subsequently
routing failures.
* New: In Kanata::Manipulator, added method reprocessParallels(), not used
though, but keep it anyway, might be of use later...
* New: In Kanata::Manipulator, added method avoidBlockage() for terminal
METAL2 in non-preferred direction, restrict the terminal and turn
constraint box at the current position of the perpandicular, so it
doesn't create a deadlock in METAL2.
* Change: In SegmentFsm::conflictSolveByPlaceds(), if we cannot break
using the whole overlap, try the first atomic overlap.
* New: In SegmentFsm::_slackenStrap(), manage conflict between a non-prefered
segment and a blockage, this when to call avoidBlockage()...
* New: In Katana::Configuration, management of the new edge computation
parameters:
katana.termSatReservedlocal
katana.termSatthreshold
* New: In Cumulus/plugins/Core2Chip, support for Phenitec I/O pads.
Jean-Paul Chaput
Gabriel Gouvine