* Bug: In Cumulus/plugins/core2chip/CoreToChip.py, when creating the ioNet
objects, when a signal is an enable we must not set the external chip
net (the name for the PAD terminal) as it may be set later if it is
also used as an individual pad.
* Change: In Hurricane::SharedName, replace the incremental Id by a hash key.
This is to ensure better deterministic properties. Between use cases,
additional strings may have to be allocated, shitfing the ids. Even if
hash can be duplicated, we should be able to ensure that the absolute
order in map table should be preserved. Supplemental strings are inserted
in a way that keep the previous order.
* Change: In CRL/etc/symbolic/cmos/kite.conf, add "katabatic.routingGauge"
default parameter value ("sxlib").
* Change: In CRL/etc/common/technology.conf, define minimal spacing for
symbolic layers too (added for METAL4 only for now).
* Change: In CRL::Histogram, extend support to dynamically sized histograms.
Add a text pretty print with table and pseudo-curve.
* Change: In Cumulus/plugins/ClockTreePlugin, create blockage under the
block corona corners so the global router do not draw wire under them.
This was creating deadlock for the detailed router.
When the abutment has to be computed, directly use Etesian to do it
instead of duplicating the computation in the Python plugin.
* New: In Etesian, as Coloquinte seems reluctant to evenly spread the
standard cells, we trick it by making them bigger during the placement
stage. Furthermore, we do not not uniformely increase the size of the
cells but create a "bloating profile" based on cell size, cell name
or it's density of terminals. Currently only two profiles are defined,
"disabled" which does nothing and "nsxlib" targeted on 4 metal layer
technologies (aka AMS 350nm, c35b4).
* Bug: In Knik::MatrixVertex, load the default routing gauge using the
configuration parameter "katabatic.routingGauge" as the default one
may not be the first registered one.
* New: In AnabaticEngine::setupNetDatas(), build a dynamic historgram of
the nets terminal numbers.
* Bug: In Anabatic::AutoContact::Invalidate(), always invalidate the
contact cache when topology is invalidated. In case of multiple
invalidations, if the first did not invalidate the cache, later one
that may need it where not allowed to do so. The end result was correct
nonetheless, but it did generate annoying error messages.
* Bug: In Anabatic::AutoContactTurn::updateTopology(), bad computation
of the contact's depth when delta == 2.
* Bug: In Anabatic::Gcell::getCapacity(), was always returning the west
edge capacity, even for the westermost GCell, should be the east
edge in that case.
* New: In Anabatic::AutoSegment, introduce a new measure "distance to
terminal". This is the minimal number of segments separating the
current one from the nearest RoutingPad. This replace the previous
"strong terminal" and "weak terminal" flags.
This distance is used by Katana to sort the events, we route the
segments *from* the RoutingPads *outward*. The idea being that if we
cannot event connect to the RoutingPad, there is no points continuing
as thoses segments are the more constraineds. This gives an order close
to the simple ascending metals but with better results.
* New: In Anabatic::AutoSegment, introduce a new flag "Unbreakable", disable
dogleg making on those segments. mainly intended for local segments
directly connecteds to RoutingPads (distance == 0).
* New: In Anabatic::AutoSegment, more aggressive reducing of segments.
Now the only case where a segment cannot be reduced is when it is
one horizontal branch in a HTee or a vertical on a VTee. Check if,
when not accounted the source & target VIAs are still connex, if so,
allow reducing.
* New: In Anabatic::AutoContact, new state flags CntVDogleg & CntHDogleg
mainly to prevent making doglegs twice on a turn contact. This is to
limit over-fragmentation. If one dogleg doesn't solve the problem,
making a second one will make things worse only...
* Bug: In Anabatic::Configuration::selectRpcomponent(), we were choosing
the component with the *smallest* span instead of the *bigger* one.
* New: In Anabatic::GCell, introduce a new flag "GoStraight" to tell that
no turn go be made inside those GCells. Mainly used underneath a block
corona.
* New: In AnabaticEngine::layerAssign(), new GCellRps & RpsInRow to manage
GCells with too many terminals. Slacken at least one RoutingPad access
when there is more than 8 RoutingPad in the GCell (slacken or change
a vertical METAL2 (non-preferred) into a METAL3).
* Change: In Anabatic::NetBuilderHV, allow the use of terminal connection
in non-preferred direction. That is, vertical METAL2 directly connected
to the RoutingPad (then a horizontal METAL2). This alllows for short
dogleg without clutering the METAL3 layer (critical for AMS c35b4).
Done in NetBuilderHV::doRp_Access(), with a new UseNonPref flag.
Perform some other tweaking on METAL1 access topologies, to also
minimize METAL3 use.
* New: In AnabaticEngine::computeNetConstraints(), also compute the
distance to RoutingPad for segments. Set the Unbreakable flag, based
on the distance and segment length (local, short global or long global).
New local function "propagateDistanceFromRp()".
* Change: In AnabaticEngine.h, the sorting class for NetData, SparsityOrder,
is modificated so net with a degree superior to 10 are sorted first,
whatever their sparsity. This is to work in tandem with GlobalRouting.
* New: In Katana::TrackSegmentNonPref, introduce a class to manage segment
in non-preferred routing direction. Mostly intended for small METAL2
vertical directly connected to RoutingPad. Modifications to manage
this new variant all through Katana.
* Change: In Katana::GlobalRoute, DigitalDistance honor the GoStraight flag
of the GCell. Do not make bend inside thoses GCells.
* Change: In KatanaEngine::runGlobalRouter(), high degree nets (>= 10) are
routed first and whitout the global routing estimation. There should be
few of them so they wont create saturations and we want them as straight
as possible. Detour are for long be-points.
Set the saerch halo to one GCell in the initial routing stage (before
ripup).
* Bug: In KatanaEngine & NegociateWindow, call _computeCagedconstraints()
inside NegociateWindow::run(), as segments are inserted into tracks
only at that point so we cannot make the computation earlier.
* Change: In Katana::Manipulator::repackPerpandiculars(), add a flag to
select whether to replace the perpandiculars *after* or *before* the
current segment.
* Change: In Katana::NegociateWindow::NegociateOverlapCost(), when the
segment is fully enclosed inside a global, the longest overlap cost
is set to the shortest global hoverhang (before or after).
When the cost is for a global, set an infinite cost if the overlapping
segment has a RP distance less or equal to 1 (this is an access segment).
* Bug: In Katana::PowerRailsPlane::Rail::doLayout(), correct computation of
the segments extension cap.
* New: In Katana::QueryPowerRails::addToPowerRail(), add support for Pad.
* Change: In Katana/PreProcess::protectCagedTerminals(), apply the contraints
to any turn connected to the first segment of the RoutingPad so the
perpandicular constraints got propagated to the perpandicular segment...
* Change: In RoutingEvent, cache the "distance to RP" value.
* Change: In RoutingEvent::Key::compare(), sort *first* on distance to
RoutingPad, then layer depth. If both distance to RoutingPad is null,
then sort on segment length.
* Change: In RoutingEvent::_processRepair(), try a repack perpandicular with
perpandiculars first (then with perpandicular last, then give up).
* Change: In SegmentFsm::bindToTrack() and moveToTrack(), set an axis hint
when creating the insertion event.
* Change: In SegmentFsm::_slackenStrap(), add a step through slacken between
minimize and maximum slack (wihch directly end up in unimplemented).
* Change: In Session::_addInsertEvent(), add an axis parameter needed when
the axis of the segment is not the one of the track (case of wide
segments or non-preferred direction).
* Bug: In Track::_preDestroy(), bad management of the TrackElement reference
count. Destroy the segment only when reaching zero...
* Bug: In Track::expandFreeIneterval(), forgotten to manage case when there
is a set of overlaping segments at the "end" of the track, the
EndIsTrackMax was not set.
* Change: In TrackCost::Compare, increase the cost when an overlaping
segment is at it's ripup limit. We should try *not* to rip it up if
we can. Add a dedicated flag "AtRipupLimit".
* Change: In TrackElement, add proxies for isUnbreakable(), new function
updateTrackSpan().
* New: In TrackFixedSegment CTOR, when a supply wire of METAL2 or above is
found, make the underlying GCells "GoStraight".
* New: In TrackElement::canDogleg(GCell*), check for already done perpandicular
dogleg on source/target (reject if so).
* Change: In Hurricane::Error constructors disable the backtrace generation.
(*very* slow).
* Change: In Hurricane::Library::getHierarchicalname(), more compact
naming. Remove the name of the root library.
* New: In Hurricane::Net, new type "FUSED", for component with no net.
More efficient than having one net for each.
* Change: In CellViewer, BreakpointWidget, use Angry Birds icons.
* Change: In CellWidget::State, use the hierarchical name (cached) as key
to the state. This allow to load two cells with the same name but from
different libraries in the widget history.
* Change: In PyGraphics, export "isEnabled()" and "isHighDpi()" functions.
* Change: In CRL/etc/symbolic/cmos/plugin.conf, and
CRL/etc/common/plugin.conf use the physical dimensions converters.
* Change: In CRL/etc/symbolic/cmos/technology.conf, make the GDS layer
table coherent with the default Alliance cmos.rds.
* New: CRL/python/helpers/io.py, put ErrorMessage new implementation here,
along with a new ErrorWidget written in PyQt4. It seems finally that
PyQt4 can be used alongside Coriolis Qt widgets.
New ErrorMessage.catch() static function to manage all exceptions
in except clauses.
* Change: In CRL/python/helpers/, no longer use ErrorMessage.wrapPrint(),
directly print it.
Rewrite the utilities to display Python stack traces "textStacktrace()"
and "showStacktrace()".
* Change: In CRL::AllianceFramework, shorten the names of the libraries.
* Change: In CRL::ApParser & CRL::ApDriver, more accurate translation between
Alliance connectors (C record) and Hurricane::Pin objects. Pin are no
longer made square but thin and oriented in the connecting direction.
Use the new fused net for unnamed components.
* New: In CRL::GdsParser, implementation of SREF parsing, i.e. instances.
Due to the unordered nature of the GDS stream, instances creation are
delayed until the whole stream has been parsed and only then are they
created.
For the sake of reading back Alliance s2r GDS, we assume that any
TEXT following a boundary is the Net name the boundary (component)
belongs to.
Create abutment box for Cells, computed from the bounding box, so
the Hurricane QuadTree could work properly.
Make use of the fused net for unnamed components.
* New: In Cumulus/plugins/chip, complete rewrite of the I/O pad management.
Now we can mix real (foundry) pads and a symbolic core.
To cleanly support the de-coupling between the real part and the
symbolic one we introduce a new intermediary hierarchical level, the
corona. We have now:
Chip --> Pads + Corona --> Core.
At chip level (and if we are using real pads) the layout is fully
real (excepting the corona).
The Corona contains everything that is symbolic. It has symbolic
wires extending outward the abutment box to make contact with the
real wires coming from the pads.
In the pad ring we can use corners instances (or not), pad spacers
or directly draw wires between connectors ring pads.
Provide two flavors: placement only or full place & route.
WARNING: If routing in a second step, *do not route* the *Chip* but
the *Corona*.
* Change: In Cumulus/plugins/clocktree, give the modified Cell an
additional extension of "_cts" (Clock Tree Synthesis) instead of
"_clocked", to follow the common convention.
* New: In cumulus/plugins/S2R.py, encapsulate call to Alliance S2R and
reload the translated Cell in the editor.
* New: In cumulus/plugins/core2chip, provide an utility to automatically
create a chip from a core. To work this plugins must have a basic
understanding of the pad functionalities which may differs from
foundry to foundry. So a base class CoreToChip is created, then for
each supported pad foundry a derived class is added. Currently we
support AMS c35b4 and Alliance symbolic cmos.
* Bug: In Anabatic::Configuration, read the right configuration parameter
"anabatic.topRoutinglayer" (Katana), and not the one for Katabatic...
* Change: In Unicorn/cgt.py, process the plugins in alphabetical order
to ensure a reproductible ordering of the menus...
* Bug: In CRL/etc/symbolic/cmos/plugins.conf, rails dimensions are no
longer expressed directly in lambda. Must be created using helper.l().
* Change: In CRL::ApParser, slightly more smart management of Pin width.
Must normalize Pin behavior between Alliance & Hurricane as in
Alliance they have only one dimension.
* Change: In CRL::LefImport, if a net name end with "!", assume it's a
global one. Have to check this naming convention.
* Change: In Anabatic::NetBuilderHV::_do_1G_1PinM3() & _do_1G_1PinM2()
now implemented. Needed for the corona routing support.
* Change: In AnabaticEngine::setupPreRouted(), exclude segments outside
the abutment box.
* Change: In KatanaEngine::PowerRails, remove the I/O pad support as now
we route only inside the Corona. So only one vdd/vss/ck are supported.
* New: In cumulus/plugins/ChipPlugin.py, complete rewrite of the chip
support:
* Uncouple pad I/O ring whith real cells (foundry) from a symbolic
core. A new intermediate level "corona" is introduced to handle
the real/symbolic transition.
* Ability to explicitly setup position of the pads on the chip side
in case of uneven distribution.
* Enable clock tree to be build with 3 metal only (M2 to M4) instead
of (M2 to M5).
* New: In Hurricane::Isobar::PySegment, added wrapper for getOppositeAnchor().
* Bug: CRL::PyRoutingLayerGauge, Python wrapper of getTrackPosition() was
in fact returning getTrackNumer().
* Bug: In Katana::PowerRailsPlanes::Rail::doLayout(), add the half minimum
distance to the blockage segments extensions. Was causing too near
VIAs is cmos45.
* Change: In cumulus/plugins/ClockTree, correctly manage routing gauge when
the lower pitches (M2/M3) is different from the upper one (M4/M5).
But we still can only do sxlib compliant gauges because we do not
handle a switch in preferred routing directions.
* Bug: In Cumulus & Stratus, now that creation of Hurricane objects must be
enclosed in UpdateSession, has to adds them into Python code.
* Bug: In Anabatic & Katana, in the global routing stage suspend the timed
bewteen ripup steps instead of resetting it.
* Bug: In CRL Core, in BlifParser, recognize clocks (Alliance patterns).
* Change: In Cumulus, in RSavePlugin, "kw" manage a new "views" to
specify which views must be saved. Physical by default, but sometimes
we need logical as well. If the design contains uniquified cells,
save the logical view.
In ClockTree, abort the clock tree building if the design has no
top level clock.
* Change: In Katabatic, in GCellTopology, adds 2G_5M1 configuration.
* Bug: Kite, in BuildPowerRails, if we are not in a chip the nets
composing the H-Tree must be protecteds be blockages.
* Change: In Cumulus, in Configuration.py, in the horizontal & vertical
wire creation adds new flags ExpandWidth to draw wires one lambda
bigger than the minimal width (see ClockTree.py patch).
* Change: In Cumulus, In ClockTree.py, use non default width to draw
wires of the H branch of the clock tree. This is to prevent them
to be recognized as "manual global routing", which they are not
and not event topologically compatible.
* Bug: In Kite, in BuildPowerRails, change the way clocks are detected
when working on a single block (not a whole chip). Now look only
in clock which are external and do not filter out already routed
ones.
* Change: In KiteEngine, in createGlobalGraph(), systematically call
flattenNets() so nets that are added after the first flattening
in the placer are also flattened. The flattenNets() Cell method
takes care of not flattening twice a net.
* New: In Hurricane, in DebugSession, add a new method to activate the
trace inconditionally with a certain level.
* New: In Hurricane, in HyperNet, allow copy construction as there is
no reason to disallow it and we need it now.
* New: In Hurricane, in Cell::flattenNets(), add a new option to prevent
the flattening of the clock net(s). For more safety perform the
DeepNet creation *outside* the Collection loop.
* Bug: In Hurricane, in Cell_HyperNetRootNetOccurrences, skip the
DeepNets because they are the result of another flattening operation.
* New: In Isobar, in PyBasicLayer, export C++ method getBlockageLayer().
* New: In Isobar, in PyRoutingGauge, export C++ method getLayerPitch(),
needed by Cumulus plugins.
* New: In Etesian, EtesianEngine::findYSpin() to look for the Y orientation
if some cells are already placed. Typically the buffers of a clock
tree.
Pass the correct orienation to row_compatible_orientation().
Do not try to add feeds in the ISPD05 benchmarks. For now the
benchmarks are detected through their names (unreliable).
* Change: In Knik, in KnikEngine::initGlobalRouting(), allow the clock
to be routed as an ordinary signal when the clock tree is not
used.
* New: In Kite, in BuildPowerRails, management & detection for the
pre-routed clock.
In KiteEngine constructor, early initialization of the blockage
net to avoid later troubles in BuildPowerRails.
* New: In Cumulus, in ChipPlugin, add support for Etesian plus new
configuration parameter 'clockTree.placerEngine' to select between
Mauka and Etesian.
* New: In Cumulus, in BlockCorona, add blockages in the vertical sides
in the vertical layer to prevent the router to use the vertical
tracks in under the prower lines (for example, blockage in M3
with power line M5).
In Cumulus, in ChipConf add attribute to access the blockage net.
* New: In Cumulus, when the clock tree is disabled, do not generate
the last rail around the block (the clock rail).
* Bug: In Cumulus, in ChipConf use the clock pad to guess the clock
signals and *not* the power pad.
Add more meaningful error messages if a pad global signal is
not found (implicit connexion by name).
* Bug: In Cumulus, in ClockTree, compute correctly the cells Y spin,
that is *from the bottom of the cell AB* (not from 'zero').
* Bug: In Cumulus, in ClockTree.py, do not use "tie_x0" which is 2 pitch
wide to fill the free space left by clock-tree removed (unused)
buffers. If the buffer size width is odd (in pitch), it will left
a gap in the WELL. That was the cause of DRC notch errors.
Instead use "rowend_x0" which is one pitch wide.
Should use the same mechanism as in Mauka InsertFeed.
* Change: In Hurricane, the NetRoutingProperty is moved into Hurricane
from Katabatic. Needed for Knik to be able to access thoses
informations.
* Change: In Hurricane, in RoutingPad::setOnBestComponent(), now in
case of identical area, select the component of lowest id.
This should not be needed if the component ordering was fully
deterministic as it should be (will investigate later).
This is to ensure that the choosen component is always the
same, especially between save/load of a global routing.
* Bug: In Katabatic, in AutoContactHTee::updateTopology(), invalidate
the segments only if the topology is valid (no NULL in the
cached segments).
* Bug: In Katabatic, in GCellTopology::construct(), throw an error
if the topology is bad instead of trying to continue (and core
dump later... ).
* Bug: In Kite, in BuildPowerRails, distinguish the name of the master
net in the pad (for vddi, vssi, vdde, vsse, ck, cki & cko) and the
name of the net in the *chip* netlist. Must use the later to make
comparison as they may differs.
* Change: In Knik, in save/load solution, exclude nets that are not
globally routed by Knik. That is which NetRoutingProperty is not
*Automatic*.
* Bug: In Cumulus, in chip.BlockPower take account of the layer
width extention to sligthy shrink the connector thus avoiding a
notch with standart cell in some cases.
* Change: In Cumulus, in chip.ClockTree disable the use of fixed Steiner
trees for the leaf clocks, as it seems overconstrained for the
router. First move was to lower them in M2/M3 (instead of M3/M4)
but that was not sufficent.
* New: In Cumulus, RSavePlugin for recursively saving a physical
hierarchy.
* New: In documentation, first embryo for RDS file. Should have been
in Alliance git, but I prefer to keep newest doc in Coriolis.
* New: In CRL Core, in helpers & alliance.conf, set and read a "PAD"
variable to define the pad model name extension ("px" for "sxlib
and "pxr" for vsxlib, this is provisional).
* New: In CRL Core, in plugin.conf, add parameters to define the name
of used for power & clock supply. We may remove the extention in
the future (to be more coherent with the previous modification).
* New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no
longer place the accessing contact *at the center* of the
RoutingPad. It works under sxlib because buffers & registers all
have same size terminals. But this is not true under vsxlib,
leading to misaligned contacts & wires. Now systematically place
on the slice midlle track (maybe with one pitch above or below).
This is still very weak as we do not check if the terminal
reach were the contact is being put. Has to be strenthened in
the future.
* New: In Cumulus, in chip.Configuration.ChipConf, read the new
clock & power pad parameters.
* Change: In Isobar (and all other Python wrappers), uses PyLong instead
of PyInt for DbU conversions. In PyHurricane argument converter,
automatically check for both PyLong and then PyInt.
* Change: In Cumulus, in chip.PadsCorona, more accurate error message
in case of discrepency in global net connections (i.e. no net
of the same name in instance model and instance model owner.
* Change: In Kite, in BuildPowerRails, when looking up at the pads
model name to find "pck_" or "pvddeck_", do not compare the
extension part. But we still use hard-coded stem pad names,
maybe we shouldn't.
* Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there
was a loop in the search of the best N/E initial RoutingPad.
* Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect
RoutingPads of fixed nets, they are already through the
BuildPowerRails stage (and it's causing scary overlap warning
messages).
* Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create
deep-plug when the core is flat (not sub-modules). All the new
nets are at core level.
* Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure
that the core is aligned on the GCell grid (i.e. the slice
grid of the overall chip).
* Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop
while looking for the bigger N-E RoutingPad. Forgot to decrement
the index...
* Bug: In ClockTree plugin, only the logical view of the clock buffer
was loaded, so no external components where found on the I/O nets.
The external components are loaded only when the *physical* view
is loaded. Didn't show on sxlib because the buffer was fulled
loaded *before* running the ClockTree.
* Bug: In PyHurricane, in the various LocatorNextMethod() macros,
sometimes an empty collection can be returned by Hurricane
(GenericCollection()), which has a NULL locator. So check
if the locator is *not* NULL before trying to access it...
* Change: In Chip, more accurate error messages related to the clock
detecttion.
* New: In ClockTree plugin, select the name of the buffer cell through
configuration (parameter: "clockTree.buffer"), and guess the I/O
name of this buffer automatically.
Put configuration parameters in plugin.conf and not mauka.conf.
Bug: strangely triggers a coredump in components collection
when used with <vsxlib>. Some debug printing still active until
that is solved.
* New: In Chip plugin, make the size and numbers of the block rails
configuration parameters (in plugin.conf).
* New: In Cumulus, first versions of the ClockTree and Chip plugins.
Clock Tree plugin:
- It is strongly advised to use have 4 metal routing layers for the
tree to work. Otherwise, problems can arise with the detailed
routing (fully obstructed terminals).
- H-Tree can only be build (for now) for design with a form factor
between 0.5 an 2.
- The tree is created at the block top-level and only the leafs are
trans-hierarchically created on the instances/models. The new
cell with a clock tree, along with all it's sub-models is created
with a "_clocked" suffix.
- Leaf cells are connected through a simple Minimum Steiner Tree.
- Shorts are avoided by a systematic shift of the wires according
to their kind. No wire must pre-exist. When used as a sub-module
of "chip" the wires cannot be moved. When created on a block,
the wires can be loaded in the detailed router as manual global
router.
Chip Plugin:
- Perform the pad placement and corona creation. Replacement at
last of the clunky code from Wu Yifei.
- Relies on a Python configuration file '<design>_chip.py' with
a "chip" dictionnary.
Jean-Paul Chaput