In order to accurately find the rectangles (Components) causing a short
circuit, we need to aggregate the equipotentials as soon as we starts
to merge the tiles. Because tiles being a union set, the tree compression
forbid to know which tile overlap which one afterwards. So the equipotentials
are created early on the fly. We also add an accounting of all the net's
components (Plug excluded) to know if it is fully included in the
equipotential. If not, we have an open.
This is an impacting change from the previous version in which we build
the equipotentials *after* aggregating the tiles only. The added cost
comes from the number of equipotential merging that we have to perform
when we merge tiles. Almost two times slower. May need to have a deep
look on how to optimize it later (efficient merge or keeping the order
tiles where merged).
* Change: In Occurrence::getCompactString(), when the path is void,
still display a double colon (::) instead of just one so we know
for sure that the it is void.
* In cumulus.designflow.technos.setupCMOS(): export back the guessed
ALLIANCE_TOP *before* importing technos.symbolic.cmos so it is
used for the CELLS_TOP. This avoid defaulting to /soc/alliance
which does exists only on LIP6 computers...
Note about the managment of VIA & cuts: Components using a layer which
is a ViaLayer, that is one containing more than one BasicLayer,
multiple tiles are created in QueryTiles::goCallback().
Components that have a single BasicLayer of "cut" material will
also have their multiples tiles created in QueryTiles::goCallback().
Rectilinear components will have their multiples tiles created
in Tile::create(). Tile::create() return not all the tiles but the
one used as root (for the union find).
* New: In SweepLine::_buildCutConnexMap(), when using a "cut" layer
in a standalone way, and not as part of a ViaLayer, we do not
automatically know to which layer above & below they are connected.
We build a table for each cut layer, based on the ViaLayer,
to know all tops & belows layers they connect (this is cumulative,
in the case of "cut" towards the substrate).
Then in Tile::create(), we not only create the tile for the "cut"
but also in thoses connected layers (and link them in the union
find).
* New: In Tile::create(), when we encounter a Rectilinear, break it
into rectangles and make as many tiles. All tiles linked to the
same root in the union find.
* Bug: In Hurricane::Rectilinear, ambiguous specification of the set
of points defining the shape. I did suppose that the start and and
point where not the same the last edge being between them.
But if FlexLib, it uses the GDSII inspired convention where the
first and last point must be the same, to indicate a closed contour.
This difference was not causing any difference with the drawing,
but it was a problem for getAsRectangle(). This was creating a
"false" extra vertical edge leading to a bigger rectangle.
And this, in turn, was making "false" intersections in the
tiling/sweepline of the extractor.
Add a more thorough checking of the points vector.
* New: Rectilinear::asRectangles(), decompose the Rectilinear into a
set of non-overlapping rectangles sliced vertically.
This not a mathematical minimum set. But should be speedier.
Done using a sweepline processing the vertical edges.
Specially suited for use in the extractor which basically
manage only rectangles.
Simple algorithm described in pp. 9-11 of Extractor notebook.
Tests done with unitests/python/test_rectilinear.py, the
Rectilinear here should cover all the sweepline cases.
Definition: A buried net is a net that has no components at the top
Cell level. Typically example is a wire internal to a standard cell.
Those nets, while part of the complete design (flat) are not part
of the top netlist, and we may want not to see it.
A buried net is slighly different from a deep net. While a deepnet
is also not reaching the top level cell, we created it at top level
to be processed by the router (virtual flatten).
Gabriel Gouvine
Jean-Paul Chaput