* Change: In Hurricane::SharedPath, the hash for the shared pathes, which
serves for Map<> storing, were computed "on the fly" at each
::getHash() call, and were involving recursive calls of all the
hashes along the components of the shared path. This is terribly
slow especially in a design with a deep hierarchy (typical case
LS180).
Now, at the cost of one supplemenental unsigned long in each
SharedPath, it is only computed once in the constructor, and is
no longer recursive (only access the *first* tail, if any).
As a consequence, the re-display computation delay becomes
bearable. But also speed up any transhierarchical walkthough.
* Change: In Etesianengine::toHurricane(), no longer call interTies().
This *should* no longer be needed as almost all standard cells
(SxLib & FlexLib) already contains polarisation contacts.
So do not need to disturb the placement.
Secondly, in presence of a H-Tree, when there is not enough
space to insert a sufficient number of tie cell, the lefmost one
in the sub-row is shifted to left, overlaping the H-Tree buffer
cells. This is a bug (even signaled by a warning). But as this
part is disabled, I won't correct it soon...
* Change: In Cumulus/plugins.block.Block, for standalone block,
the external Pin where created non-square, the "perpandicular"
side made a half wire width. But in case the wire width was an
odd number of physical grid, it was leading to offgrid screaming
in the GDS driver.
Now, just make them square...
* Bug: In CRL::GdsDriver::GdsStream::operator<<(Cell*), when looking for
layer names ending with ".pin", must also check that the string is
at least 4 characters long.
The CMake version set was so old that obsolete policies were being
enabled and breaking FindPython. 2.8 should still be old enough not to
cause problems for any current users.
Signed-off-by: Myrtle Shah <gatecat@chipflow.io>
This field has been deprecated in Python 3 and no longer exists at all
in Python 3.9, causing a build error.
Signed-off-by: Myrtle Shah <gatecat@chipflow.io>
* Bug: In KatanaEngine::annotateGlobalGraph(), the minimum track reservation
was not applied correctly. Instead of adding the *difference* between
the minimum and the current reservation, the minimum was simply added.
Leading to too high reservation. And loss of control about what we
were doing on the edges capacities...
Really stupid.
large enough instead of creating one big via along the horizontal
cell power lines, we create one big VIA at each end. To avoid to
create too massive obstructions.
But the thresold was too high for cmos45, leading to short with
the clock tree trunk.
* Change: In bootstrap/coriolisEnv.py, when all tries to locate the
installation root in predefined locations, try the directory the
script is installed in.
This allows for a user to use an installation made in another
user's account.
* Bug: In Anabatic::_desaturate(), the set of invalidated GCells was never
cleared between iterations of desaturated GCells. This was not a
memory leak per se because, in the end, the set was freed. But it did
induce a gigantic bloating in memory. This finally explain the strange
slow down in that stage.
Detected in ls180+cmos45.
* Change: In Anabatic::GCell, add a flag for each depth to avoid
desaturating twice the same GCell (maybe not needed now that the
bug is corrected, but it ensure a no-looping).
* Bug: In cumulus/plugins.block.configuration.GaugeConf.expandMinArea(),
The minimal length of the segment intermediate wires where computed
for the minimal area using an integer division ( // ), which is
stupid for less than 1.0 values. They are real quantities at this
point...
This was making the DRC of ls180 failing.
Jean-Paul Chaput
Myrtle Shah
Las Safin