Commit Graph

206 Commits

Author SHA1 Message Date
Jean-Paul Chaput e6c809a12a Correct loading of clock buffer in ClockTree plugin.
* Bug: In ClockTree plugin, only the logical view of the clock buffer
    was loaded, so no external components where found on the I/O nets.
    The external components are loaded only when the *physical* view
    is loaded. Didn't show on sxlib because the buffer was fulled
    loaded *before* running the ClockTree.
* Bug: In PyHurricane, in the various LocatorNextMethod() macros,
    sometimes an empty collection can be returned by Hurricane
    (GenericCollection()), which has a NULL locator. So check
    if the locator is *not* NULL before trying to access it...
* Change: In Chip, more accurate error messages related to the clock
    detecttion.
2014-09-03 10:37:11 +02:00
Jean-Paul Chaput ae4d938553 Buffer cell configuration in ClockTree. More config parameters in Chip.
* New: In ClockTree plugin, select the name of the buffer cell through
    configuration (parameter: "clockTree.buffer"), and guess the I/O
    name of this buffer automatically.
      Put configuration parameters in plugin.conf and not mauka.conf.
      Bug: strangely triggers a coredump in components collection
    when used with <vsxlib>. Some debug printing still active until
    that is solved.
* New: In Chip plugin, make the size and numbers of the block rails
    configuration parameters (in plugin.conf).
2014-09-02 11:17:47 +02:00
Jean-Paul Chaput 51a3236962 Add management of fixed wires to Kite (for chip ClockTree)
* Change: In Hurricane, in Plug::setNet(), more informative error messages.
* Change: In Hurricane, In Segment, more informative error messages.
* Change: In Hurricane, In DeepNet, accessor for the Net occurrence.
* Bug: In Katabatic, in AutoSegment::create(), error message uses correct
    variables (vertical was using horizontal)...
* Change: In Kite, in BuildPowerRails, already existing wiring in instances
    is copied up as blockage. Uses blockage layer instead of true layer
    (it was a bug).
* Change: In Kite, in BuildPreRouted, consider as manual global routing
    nets with only default wiring (default size wire & contacts).
    Non-default routing is flagged as fixed (with the NetRoutingState
    property).
2014-08-15 19:26:49 +02:00
Jean-Paul Chaput fb4a7457a1 First basic version of ClockTree & Chip plugins.
* New: In Cumulus, first versions of the ClockTree and Chip plugins.
    Clock Tree plugin:
    - It is strongly advised to use have 4 metal routing layers for the
      tree to work. Otherwise, problems can arise with the detailed
      routing (fully obstructed terminals).
    - H-Tree can only be build (for now) for design with a form factor
      between 0.5 an 2.
    - The tree is created at the block top-level and only the leafs are
      trans-hierarchically created on the instances/models. The new
      cell with a clock tree, along with all it's sub-models is created
      with a "_clocked" suffix.
    - Leaf cells are connected through a simple Minimum Steiner Tree.
    - Shorts are avoided by a systematic shift of the wires according
      to their kind. No wire must pre-exist. When used as a sub-module
      of "chip" the wires cannot be moved. When created on a block,
      the wires can be loaded in the detailed router as manual global
      router.
    Chip Plugin:
    - Perform the pad placement and corona creation. Replacement at
      last of the clunky code from Wu Yifei.
    - Relies on a Python configuration file '<design>_chip.py' with
      a "chip" dictionnary.
2014-08-15 19:05:27 +02:00
Jean-Paul Chaput 25e82fc701 Complete replacement of the Chip placement Python scripts.
Finally get rid of the demonic code from Wu Yifei...
* New: In Isobar, added encapsulation of Interval (don't know how have
    forgotten it for so long).
* Change: In Isobar, In PyLayer, new PyLink_LayerDerived() function to
    create/link the C++ object to the correct derived class and not the
    base one (PyLayer) which then prevent to use the specialized methods.
    Must replace PyLink_Layer() througout all the code.
* Change: In Isobar, in PyPoint the "setX()" & "setY()" methods where
    still capitalized.
* Change: In Isobar, in PyQuery, complete the exportation of the C++
    interface. remove the code belonging to a more "boost" way of
    building the Python interface (will do that in a far future).
* New: In CRL Core, In PyAllianceFramework, export isPad() method.
* Change: In Unicorn, in unicornInit.py, protect the loading of each
    single plugin by a "try" / "except" clause to the failing of one
    plugins do not stop the loading of the next one.
      Pass the same dictionnary argument to unicornHook() as for
    ScripMain(), this is more uniform this way.
* New: In Cumulus, complete replacement of the chip placement scripts
    from Wu Yifei (at last!). The clock-tree integration is still to
    be done.
________________________________________________________________________
2014-07-21 13:18:34 +02:00
Jean-Paul Chaput d0d045b55b Starting to implement support for Windows/Cygwin.
* New: In all to CMakeLists.txt, disable the warning about deprecated
   WIN32 under cygwin.
* New: In boostrap, in ccb.py, coriolisEnv.py and builder/Configuration.py
   add recognition in uname for the values returned under Windows/Cygwin.
* New: In Documenation, in UsersGuide.rst add some informations about
   Cygwin and a section for the devel branch.
2014-07-13 13:14:49 +02:00