* Bug: In CRL Core, in Vst driver, remove VhdlEntity (from Cell) and
BitProperty/Bit (from Net) with the property remove and not the
destroy() method. The BitProperty removal was completly forgotten
leading to the use of removed Signals when doing multiple saves
(hence core-dump).
* Change: In CRL Core, in Vst driver, never save as Signals the DeepNets
as they are created by a virtual flatten and do not connect any
instances at top level. Note that they will exists in the physical
file if routing layout has been created.
* Bug: In Hurricane, in NetAlias, bad Record construction of the _next
field.
* New: In CRL Core, in VstDriver complete replacement of the old Vst
driver. Needed cleaner architecture to manage correctly files
importeds through the Blif parser, which are Verilog like.
It is build as an extension trough property and is not kept
in sync with the Cell. So it's use should be transient only.
* Change: In CRL Core, in NamingScheme forgot to change '.' (dot)
forbidden character into '_'.
* Change: In Cumulus, in the RSave plugins, remove the VHDL extensions
after saving.
* New: In Hurricane, In Net & Cell, support for Net aliases names.
Use a structure based on a simple ring of NetAliasHook. The Net
holds a global map, sorted by names of all the aliases of all Nets.
Elements NetAliasesHook of the map are slaves of ring whose master
is an attribute of the Net (it is *not* in the map, as the primary
name of the Net).
In case of merge, the aliases of both Nets are merged and the
name of the merged one become an alias.
The Cell::getNet() looks in both the Net map and the aliases to
find a Net by name.
* Bug: In CRL Core, in coriolisInit.py, reoder the loading of the
configuration files so the real technology is read as early as
possible to set up the <gridsPerLambda> factor before any lambda
is actually computed...
* Bug: In CRL Core, in AcmSigda, do not try to fed the file when it
has failed to be opened. Throw a clean exception instead.
* New: In CRL Core, in Toolbox, add a NamingScheme object to convert
a design into VHDL compliant names (mainly from Blif/Verilog).
This is extensible in any case.
* New: In CRL Core, in BlifParser, slightly more informative warning
messages. Align the loading progress information on the other
parsers.
Add a capability to select which component of the design will
be returned, if there are more than one. Use the "." as separator.
For exemple you can request "Processor.Alu", which will load
the "Alu" component from the design in "Processor.blif".
To be able to save a Blif loaded design, systematically convert
all the name for VHDL compliance, as it is the format used by
the Coriolis native files (vst).
Export the Blif parser to the Python interface.
* New: In Kite, In NegociateWindow, add a counter of the number of
remaining events. Gives an idea of the ETA...
* New: In Unicorn, in cgt.by, add an option to load a Blif design from
the command line.
* New: In Cumulus, new RSave plugin to save both netlist & layout.
Partly redundant with the previous one. Have to better organize
that later.
Cleanup:
* Cleanup: In <vlsisapd/src/bookshelf>, remove unused file Bookshelf.cpp
(may have been a parser once upon a time).
* Cleanup: In <hurricane>, in Cell::flattenNets() use flags instead of
booleans to be more readable. Allow occurrence placement checking.
* New: In <crlcore> add Python wrapper for the Ispd05 loader.
* New: In <unicorn> add option for direct loading of ISPD05 designs.
* Bug: In <hurricane/src/viewer>, RecordModel must emit
layoutAboutToBeChanged() before changing the record contents (and
layoutChanged() afterwards).
- A complete sweep of cleanup to suppress allmost all compiler warnings.
* ./crlcore:
- New: Extented Python support for all objects needed to configure Coriolis.
- New: Configuration files and load helpers completly written in Python.
An XML emulation mode is still avalaible.
- New: UsersGuide, as a replacement for README, written in ReST.
- New: Start of Doxygen documentation (mostly for documenting the initialisation
objects & methods).
- Change: New problem identified with the Python modules: each module seems
to be built as a complete binary, so all the static C++ initializers are
allocated in each module. In particular the C++ tree inheritance is built
for *each* module so we cannot longer uses the typeid() comparisons
across modules... It was used by boost::program_options to perform is
casts with boost::any and was starting throwing exceptions because of
bad casts. program_option was first initialized in "configuration"
first included by PyViewer then in PyCRL (see Utilities.cpp).
A first solution is to re-order the import of Python modules in
stratus1/st_model so that CRL is imported first.
The second is to not not link "configuration" with boost::program_option
as only the binary vlsisapd-conf-editor needs it.
That is a serious problem of which we must be aware and can cause further
strange behaviors.
Debug code used to diagnostic has been kept commented in the sources a
it may be needed again :-(
This behavior do not affect our singletons because they are part of
dynamic libraries that seems to be correctly shared between the various
Python modules.
* ./crlcore:
- In PyCRL, module method "getAllianceFramework()" moved as static object
method "get()" of AllianceFramework. Object AllianceFramework added
to module CRL.
- Bug: target_link_libraries() must be put back for OSX Snow Leopard
(doesn't seems to affect Leopard). As I do not have an OSX under
my hand it's untested and is likely to fail at that point.
* ./crlcore:
- New: PyCatalog & PyCatalogState python wrappers, mainly to have constants
values for stratus1 parsers/drivers.
Jean-Paul Chaput