* Change: In Etesian::BloatChannel, when two DFFs are side by side, if
they are not separated by at least one pitch, the track avoid
mechanism will not be able to work. Hence the minimal one pitch.
* Change: In Etesian::SubSlice::getUsedVTracks(), now take blockages
into account for used vertical tracks.
* Bug: In Etesian::SubSlice::avoidTrack(), right free interval for
shifting was wrongly computed, effectively allowing *any* shift.
This was creating cells overlap!
* New: In Hurricane::BasicLayer & Layer, establish a two way link
between the blockage layer and routing layer. Now we can access
the routing layer from the blockage.
* New: In NetBuilderHybridVH::_do_1G_xM1_1PinM1(), added configuration
to manage pins on the north/south sides for VH,2RL.
* Bug: In NetBuilderHybridVH::doRp_xG_xM1_xM3(), correct misplaced
vertical creation (buildind invalid topologies).
* New: EtesianEngine::toColoquinte(), display histograms of the cells
widths (in pitch) before and after bloating to get a better feeling
of the behavior.
* New: In EtesianEngine, add support for track avoidance. Portions of
tracks to avoid are specified by a Box, which should flat and on
the axis of the request track. This feature is used by the H-Tree
to clear the vertical tracks under the tree from any terminal.
* New: In Etesian::Area, Slice and SubSlice, add support for track
avoidance. Exported to the Python wrapper.
* New: SubSlice::getUsedVTracks() to get a set of tracks blocked by
the cell.
* New: SubSlice::trackAvoid(), shift left/rigth the cell under the
requested vertical track. Try only to move the cell under the
track and not it's neighbor, so it assume that there is sufficient
space left or right of the cell.
* Bug: In cumulus/plugins.block.configuration.BlockConf, the Cfg
parameters may be read too early from the Cfg space into the
various sub-conf objects (like FeedsConf). Delay the reading
of the parameters in a _postInit() functions.
Modify Block and CoreToChip to call _postInit().
* New: In cumulus/plugins.block.configuration.BlockConf._loadRoutingGauge,
allow the cell gauge name to differ from the routing gauge name.
* New: In cumulus/plugins.block.configuration.FeedsConf, allow to
select the default feed to be used with 'etesian.defaultFeed'
parameter.
* New: In cumulus/plugins.block.spares.BufferPool, allow to control
whether or not we want tie to either side of the pool.
(for latch up).
* New: In cumulus/plugins.block.HTree._connectLeaf(), add support
for track avoidance.
* Bug: In cumulus/plugins.block.HTree._connectLeaf(), the TL2 contact,
the one on the *top* auxiliary buffer seemed to have been badly
positioned until now (too low, not using tl2Y).
This is strange because it should have caused disconnections,
but I didn't see it in the wiring and the regressions tests didn't
flag anything wrong. Still a bit weird and worrying.
Previously, the relevant NetBuilder and routing strategies where
directly guessed from the RoutingGauge traits. This is no longer
doable as the combinations increases. Now to configure both the
global and detailed router we need three "parameters" :
1. The routing gauge itself (tells which layers are in which
directions) and how to make the VIAs.
2. The NetBuilder to use, they are identified by strings.
Currently we support:
* "HV,3RL+", for all SxLib derived standard cells.
* "VH,2RL", for hybrid routing (over the cell, but terminals
are also in the first RL).
* "2RL-", for strict channel routing.
* "VH,3RL+", an attempt for FreePDK 45, not optimized enough
to be considered as usable.
3. The routing style, mostly affect the way the GCell grid will be
built.
* VH : first RL is V.
* HV : first RL is H.
* OTH : Run in full over-the-cell mode (needs at least 3RL).
* Channel : Run in *strict* channel routing mode (no routing over
the standard cells).
* Hybrid : Create channels, but can use H tracks over the
standard cells.
Thoses three parameters are partly overlapping and must be sets in
a consistent manner, otherwise strange results may occurs.
* New: CRL::RoutingGauge::getFirstRoutingGauge(), to get the lowest
layer available for routing (not a PinOnly, not a PowerSupply).
* Change: In CRL::RoutingGauge::isHV() and isVH(), were previously
always returning false when the gauge was 2RL only. Now, check
on the first usable RL.
* Bug: In cumulus/plugins.block.configuration._loadRoutingGauge(),
there was a bad computation of the deep RLs when the top layer
was not defined. Occured for 2RL gauges only.
* Bug: In Anabatic::RpsInRow::slacken() (LayerAssign), forgotten curly braces
in the test to skip METAL2 terminals.
* Change: In Etestian::BloatChannel::getDx(), adjust the bloating
policy to converge on Arlet6502. Always ensure that there is
a 50% ratio between terminal used V-tracks and free ones.
If there is more than 80% of terminals, add one more track.
* Bug: In AnabaticEngine & KatanaEngine, KatanaEngine is a derived
class of AnabaticEngine. They uses Anabatic::Configuration
and Katana::Configuration that also derives from each other.
I though I had made one configuration attribute in the base
class that was using the right Configuration. But no. I did
have two configurations attributes, one in AnabaticEngine and
one in KatanaEngine, the later "shadowing" the former. As a
results, parameters modified in AnabaticEngine, *after* the
initial creation of the tool *where never seen* at Katana
level (due to it's own duplicate). What a mess.
Now there is only one attribute in the *base* class Anabatic,
which is created through a new virtual function _createConfiguration()
called in _postCreate() which allocate the right Configuration
according to the dynamic type of the tool (KatanaEngine).
In KatanaEngine, access the configuration through the
attribute (_configuration) and not the accessor (getConfiguration()).
* Bug: In KatanaEngine, no longer directly use the _configuration attribute
(which is not accessible anyway) but the getConfiguration() accessor.
The accessor perform a static_cast from the Super::getConfiguration()
into Katana::Configuration.
Complete cleanup of the various configuration accessors.
* New: AnabaticEngine::setupNetBuilder(), perform an early check
of the requested NetBuilderStyle. The NetBuilderStyle is just a
string that will be matched against the (hard-coded) supported
NetBuilders. Then check the topological characteristics against
the capabilities of the gauge (HV, VH and so on).
Still a bit too hard-coded for now.
This function has been split from AnabaticEngine::_loadGrByNet().
* Change: AnabaticEngine::isChannelStyle() renamed from isChannelMode().
* New: In Anabatic::Configuration, two new attributes to select the
topology and routing style:
- _netBuilderStyle to explicitely select the NetBuilder to use.
It's a string, which is provided by each NetBuilder.
- _routingStyle to define how the overall routing will work.
It's a set of flags (StyleFlags):
* VH : first RL is V.
* HV : first RL is H.
* OTH : Run in full over-the-cell mode (needs at least 3RL).
* Channel : Run in *strict* channel routing mode (no routing over
the standard cells).
* Hybrid : Create channels, but can use H tracks over the
standard cells.
* New: In anabatic/Constants, add StyleFlags to define how the router
should operate (see above).
* Bug: In Anabatic::GCell, in CTOR, no reason to set up the HChannelGCell flag.
* Bug: In Anabatic::GCell::updateDensity(), when computing layers non contiguous
saturation, do not systematically skip RL 0, but only if it's PinOnly.
* Change: In Anabatic::NetBuilder, rename isTwoMetal by isStrictChannel.
* Change: In Anabatic::NetBuilderHV, rename doRp_AccessNorthPin() in
doRp_AccessNorthSouthPin(). More accurate.
* Bug: In NetBuilderHV::_do_1G_xM1_1PinM2(), the wires to connect the M1
terminals where created *twice*. Uterly stupid, there where placed in
overlap by the router!
* New: In AnabaticEngine, new accessors to the NetBuilderStyle and
RoutingStyle, proxies towards Configuration.
* Bug: In Manipulator::relax(), if there are two doglegs to be done, but
they are in the same GCell, only do one (the conflicting interval)
is short.
* Change: In Katana::Session, rename isChannelMode() into isChannelStyle().
* Change: In TrackSegment::isUnbreakable() and isStrap(), return false
when the base segment is a *weak global* (aligned with a global one).
* Change: In Katana::Row::createChannel(), correctly distinguish between
*strict channel* style and *hybrid* style. Tag the GCells as std cells
row or channels only in the former case.
* New: In Hurricane::RoutingPad, added support if the supporting component
is a Pad. The source/target positions are computed according to the
most likely direction.
Change the _getEntityAsComponent() function into an inline template
_getEntityAs<T>().
Change the flags from an enum to static const uint32_t.
* Change: In Anabatic::Configuration, use _getEntityAs<T>.
* Change: In Anabatic::Dijkstra, use _getEntityAs<T>.
* Change: In Anabatic::NetBuilder, use _getEntityAs<T>.
* Change: In Katabatic::LoadGrByNet, use _getEntityAs<T>.
* Change: In Katana::ProtectRoutingPads, use _getEntityAs<T>.
* Change: In Bora::AnalogDistance, use _getEntityAs<T>.
* Change: In Etesian::EtesianEngine, use _getEntityAs<T>.
* Update: In CRL/node600/phenitec/kite.py, update the routing gauge to
the new format. So now we can use again SxLib-2M (channel routing
SxLib for two metal technologies).
* Change: In CRL::BlifParser, if a master cell is not found in the
AllianceFramework, then try in the Blif supplied libraries.
This is used to load the zero, one and tie cells.
Add a Blif::getCell() static function to look into the Blif
supplied libraries.
* Change: In CRL::LefImport, sometimes there can be discrepencies between
the LEF ROUTING layers and the Coriolis routing gauge. Now ignore
routing layers that are *not* presents in the Coriolis gauge.
* Change: In AnabaticEngine, moved routingMode attribute from KatanaEngine,
as some setup operations needs it.
* Change: In AutoSegment::canReduce(), allow fixed segments to be reduced
if they are "jumpers" (turn+turn and top+top or bot+bot).
This case arise on the edge of routing channels for fixed wires
to connect terminals.
* Change: In AutoSegment::getTopologicalinfos(), compute differently the
(leftBound,rightBound) interval when in channel mode.
In over-the-cell mode, this interval is the one of the whole
GCells under the wire. In channel mode, for fixed wires (that is,
verticals connecteds to cells) this interval is reduced to half
the GCell height, on the connected side of said channel.
This allows Manipulator::_insertToTrack() to issue disantangling
requests (push left/push right) for fixed segments that are face
to face in the channel.
* Change: In Anabatic::Configuration CTOR, allow the cellGauge to have a
different name from the routingGauge. Now if the cell gauge that
should match the routing gauge is not found, fallback to the
name set in "anabatic.cellGauge" parameter.
Case occur when we try to match with CORE sites from LEF files.
* Change: In Etesian::Configuration CTOR, same change as in the
Anabatic configuration.
* Change: In Anabatic::GCell::updateDensity(), never set the GoStraight
flag in channel mode. This flag makes sense when there is at least
4 routing layers (so we have 2 contiguous free of blockages).
* Bug: In Anabatic::Session::_getNearestGridpoint(), sometimes the nearest on
grid point is outside the constraint box. Now force the point
to remains inside constraints even if offgrid.
* Change: In Katana::DataNegociate::update(), perpandiculars that are
either reduced or in non-preferred routing direction should not
trigger a bug message.
* Change: In KatanaEngine::_check(), do not check for fixed, horizontal
non-prefs AutoSegments in channel mode (avoid false bug display).
* Bug: In Manipulator::_forceToTrack(), slighty shrink (-1) the interval
to free. The intersection function of intervals returns true when
the two intervals *exactly* touches (1.vMax == 2.vMin). But in
this specific case, they are not *overlapping* and no action
should be taken...
* Bug: In Manipulator::_insertInTrack(), do not reject the track when
we are overlapping a fixed vertical segment in channel mode.
(Hmm, maybe already corrected by the previous one).
* Change: In Katana::NegociateOverlapCost(), in channel mode, do
not put two overlaping vertical fixed segments into infinite cost.
This happens when two cell connected verticals are face to face in
a channel. We want them negociated the track (by shrinking their
length) instead of excluding it right away.
* Change: In NegociateWindow::createTrackSegment(), in channel mode,
do not attempt to create a track segment over a fixed and reduced
AutoSegment.
Do not attempt to put a non-preferred AutoSegment on a Track
either.
* Bug: In RoutingEvent::revalidate(), the number of availables tracks
was badly computed when in the pure constraint case, when there
was only one it was reporting zero.
* Change: In TrackElements::TrackElements_Perpandicular::Locator,
do not issue a bug when an non-pref or reduced AutoSegment do not
have an associated TrackElement.
* Change: In TrackSegmentCost::update(), do not issue a bug when a
perpandicular is reduded or non-pref and do not have a TrackElement.
* Change: In EtesianEngine::toColoquinte(), not only compute the ratio
of DFF versus the total number of gates, but also the ratio in
term of area. As the DFF are usually very big cells compare to
combinatorial one, the direct gate ratio could be misleading as
to the "weight" of those cell in the design.
This was the reason why we, sometimes got "UNCONNECTED" errors in the
VHDL PORT MAP statements. This was the remnants of the originally
connected driver.
* Bug: In Etesian::BufferTree, as the root driver is disconnected from
all the sinks, but the top tree buffer, we may end up with
unconnected signal on instances that were using it.
So now, call BufferTree::rcleaupNet() to remove the Net in
the Cell that where used to "transmit" the original driver.
* Bug: In Etesian::BufferTree, no longer use a _isDeepNet attribute
guessed from the occurrences pathes of the RoutingPad, but
trust the Net::isDeepNet() method.
* Change: In EtesianEngine::_postCreate(), issue a warning if the list of
feeds is empy (configuration: "cfg.etesian.feedNames").
* New: Add a FeedCeels::getFeedByWidth() method to get feeds by their
width in DbU::Unit and not only pitches.
* Change: In Placement::Slice::fillHole(), invert the tie filling and
feeds filling stage. Now we first try to fill the row hole with
feeds, using the widest first, and if they are not configured or
too wide, use the tie.
As the tie *should* also be integrated in the feed list, we may
suppress altogether the fallback tie filling step. Keep it for now.
* Change: In Placement::slice::createDiodeUnder(), the inserted diode
*may* be smaller than the feed it replace. So, in this case, add
a complementary feed to fill the gap.
NOTE 1: Out of lazyness, we add only *one* complementary filler
cell. So there *must* be one of a width wich correspond
exactly to the difference between the original feed and
the diode. Otherwise, gap will remains.
NOTE 2: With wider feed cells, they may cross the GCell border.
But we must insert the diode under the GCell, otherwise
the global routing will be defective. So, for now, reject
feeds that cross the boundary. Must be done more smartly
by inserting the diode over the left or right side of
the feed.
* Bug: In CRL::MeasureSet::toStringHeaders(), check and issue a warning
if a measure label ends with a "." (dot).
* Change: In CRL::ToolEngine::getMeasure(), return the data measure
by pointer instead of by reference (easier to manipulate afterwards).
* New: In EtesianEngine::place(), add the placement runtime (under label
"placeT") to the measure set.
* New: In KatanaEngine::dumpMeasures(), add the Etesian runtime to the
set of measures.
* Bug: In all CMakeLists.txt, it seems I was doing a worng use of
target_link_library(). No longer add dependencies to the C++ base
library but instead either to the Python associated module or
to the final binaries. This was inderectly causing the linking
problem related to Python (which was a misdirection).
* Bug: Typo in FindLibexecinfo.cmake, do not use FindLib[E]xecinfo.
* Change: In CRL/ccore/CMakeLists.txt, activate SKIP_AUTOMOC on
bison/flex generated files.
* Bug: In viewer/PyHApplication, do not delete the C++ object in
the Python destroy method.
* Change: In Etesianengine::toHurricane(), no longer call interTies().
This *should* no longer be needed as almost all standard cells
(SxLib & FlexLib) already contains polarisation contacts.
So do not need to disturb the placement.
Secondly, in presence of a H-Tree, when there is not enough
space to insert a sufficient number of tie cell, the lefmost one
in the sub-row is shifted to left, overlaping the H-Tree buffer
cells. This is a bug (even signaled by a warning). But as this
part is disabled, I won't correct it soon...
* New: Python/C++ API level:
* Write a new C++/template wrapper to get rid of boost::python
* The int & long Python type are now merged. So a C/C++ level,
it became "PyLong_X" (remove "PyInt_X") and at Python code
level, it became "int" (remove "long").
* Change: VLSISAPD finally defunct.
* Configuration is now integrated as a Hurricane component,
makes use of the new C++/template wrapper.
* vlsisapd is now defunct. Keep it in the source for now as
some remaining non essential code may have to be ported in
the future.
* Note: Python code (copy of the migration howto):
* New print function syntax print().
* Changed "dict.has_key(k)" for "k" in dict.
* Changed "except Exception, e" for "except Exception as e".
* The division "/" is now the floating point division, even if
both operand are integers. So 3/2 now gives 1.5 and no longer 1.
The integer division is now "//" : 1 = 3//2. So have to carefully
review the code to update. Most of the time we want to use "//".
We must never change to float for long that, in fact, represents
DbU (exposed as Python int type).
* execfile() must be replaced by exec(open("file").read()).
* iter().__next__() becomes iter(x).__next__().
* __getslice__() has been removed, integrated to __getitem__().
* The formating used for str(type(o)) has changed, so In Stratus,
have to update them ("<class 'MyClass'>" instead of "MyClass").
* the "types" module no longer supply values for default types
like str (types.StringType) or list (types.StringType).
Must use "isinstance()" where they were occuring.
* Remove the 'L' to indicate "long integer" (like "12L"), now
all Python integer are long.
* Change in bootstrap:
* Ported Coriolis builder (ccb) to Python3.
* Ported Coriolis socInstaller.py to Python3.
* Note: In PyQt4+Python3, QVariant no longer exists. Use None or
directly convert using the python syntax: bool(x), int(x), ...
By default, it is a string (str).
* Note: PyQt4 bindings & Python3 under SL7.
* In order to compile user's must upgrade to my own rebuild of
PyQt 4 & 5 bindings 4.19.21-1.el7.soc.
* Bug: In cumulus/plugins.block.htree.HTree.splitNet(), set the root
buffer of the H-Tree to the original signal (mainly: top clock).
Strangely, it was only done when working in full chip mode.
* Change: In Etesian::Slice::fillHole(), instead of cramming the home
with tix_x0 only, put one tie at both ends and fill the rest
with fill_x0. This should help the vendor density filler to
equalze.
* New: In Etesian::Configuration, add the parameter:
"etesian.tieName" (for tix_x0) as it now separate from the simple
filler cells.
* In Etesian::BloatFlexLib::getDx(), expand the "mx2_x2" of one more
pitch (2 instead of 1). The P&R was unable to allocate a critical
diode under a slice that was littered with those cells in LS180.
The H-Tree support is now allowed for any net, not only the clocks and
not only top-level nets. This allow to better management of the LS180
internal clock signal.
* New: In Cell::flattenNets(Instance*,set<string>,uint64_t) new overload
of the function to allow the user to select nets that will *not*
be flattened. This makes the NoClockFlatten flag effectively obsolete,
we keep it for backward compatibility.
The net names can be of non top level ones. In that case, they must
use the name an HyperNet will get (the Occurrence name). For example:
"instance1.instance2.deep_net_name".
* New: In PyCell, update the wrapper for the new parameter of flattenNets(),
new utility function pyListToStringSet() to translate a Python list into
a C++ set of names.
* New: In EtesianEngine, add support for a list of nets to be excluded
from the flattening procedure. Those excluded nets will also be
excludeds from the Coloquinte nets *and* HFNS synthesis, as they
are likely to be manageds by a H-Tree.
* Change: In AnabaticEngine::_loadGrByNet(), now also skip nets that are
flagged as manually detailed route.
* New: In AnabaticEngine::antennaProtect(), do not try to insert diodes
on nets that are already fixed or detaled route. This replace the
clock exclusion.
* New: In cumulus/plugins.{block,htree,chip}, replace the concept
of clock-tree by the more generic H-Tree. That is, we can ask the P&R
to create H-Tree on any net of the design, not only the ones matcheds
as clock. The net does not even need to be top-level.
This is to manage the PLL internal clock generated by the PLL in
the LS180 chip.
Start to change all reference to "clock" into "H-Tree".
* Bug: In cumulus/plugins.chip.powerplanes.Builder._connectHTree(),
there was an inversion of the H & V routing gauges to compute the
track into which put the H-Tree center to corona edge wiring.
This was causing tracks to be used twice, seen in the ao68000 test
bench.
Split "antennaMaxWL" into :
* "etesian.antennaGateMaxWL" : max length *without* any diode.
* "etesian.antennaDiodeMaxWL" : max length that *one* diode can support.
* In Etesian::Slice::createDiodeUnder(), delete the Instance *after*
removing the tile referring it. This was working, unless we
active the debug mode which tries to print the Tile's instance.
* In EtesianEngine::place(), no longer call toHurricane() at the
end of the placement. Must now be done as a separate step.
Exported to Python interface.
This fix is related to the spare buffer removal memory
corruption
First part of the antenna effect protection : diode insertions.
Anabatic::antennaProtect(Net*) and it's supporting infrastructure
has been rewritten & simplificated. Must be used in conjuction
with the "Flexlib" bloat model of Etesian. A cursory description
of the algorithm has been added in the source file.
* New: GCell::hasNet() to tell if net is going through a GCell,
either as a straigth wire or has a local GContact (turn,
branch, terminal).
* New: Etesian::BloatFlexib class (tagged "Flexlib") suited for
flexlib uses. It is derived from "nsxlib".
To have enough space to insert all the wanted diodes, we
enlarge "mx2_x2" & "mx3_x2" of resp. 1 and 2 pitches.
This is an empiric finding, Yosys seems very fond of thoses
gates and we often see them underneath area where no space
was available to put a diode... May need some more fine grained
analysis.
* Bug: In Etesian::HFNS::Cluster, all the created nets were systematically
created in the IN direction, which is obviously wrong for the driver.
Now Slice::raddTransPlug() accept a third argument stating if we are
creating a driver or a sink. Direction of the net is now combining
and can be IN, OUT or sometimes INOUT.
The VHDL files where reflecting that problem and made GHDL choke.
* Change: In Etesian::HFNS::Cluster, prefix the instance name by "cmpt_"
so it doesn't clash with the signal name in VHDL.
* Bug: In Etesian::Placement::Slice::fillHole(), do not use the xmin
previous bound, but pitch it (by excess). Insert ties *only* if
they completely fit in the free space.
This bug was showing *between* two SRAMs side-by-side, a column
of tie was inserted...
Gabriel Gouvine
Jean-Paul Chaput
Robert Taylor
Las Safin