diff --git a/crlcore/etc/CMakeLists.txt b/crlcore/etc/CMakeLists.txt index c59c77c5..5e98a678 100644 --- a/crlcore/etc/CMakeLists.txt +++ b/crlcore/etc/CMakeLists.txt @@ -3,6 +3,8 @@ install ( DIRECTORY common DESTINATION ${SYS_CONF_DIR}/coriolis2 ) install ( DIRECTORY cmos DESTINATION ${SYS_CONF_DIR}/coriolis2 ) install ( DIRECTORY vsc200 DESTINATION ${SYS_CONF_DIR}/coriolis2 ) + install ( DIRECTORY scmos_deep_018 DESTINATION ${SYS_CONF_DIR}/coriolis2 ) + install ( DIRECTORY scn6m_deep DESTINATION ${SYS_CONF_DIR}/coriolis2 ) install ( DIRECTORY hcmos9 DESTINATION ${SYS_CONF_DIR}/coriolis2 ) install ( FILES environment.alliance.xml DESTINATION ${SYS_CONF_DIR}/coriolis2 ) diff --git a/crlcore/etc/scmos_deep_018/alliance.conf b/crlcore/etc/scmos_deep_018/alliance.conf new file mode 100644 index 00000000..ddf44a0c --- /dev/null +++ b/crlcore/etc/scmos_deep_018/alliance.conf @@ -0,0 +1,56 @@ +# -*- Mode:Python; explicit-buffer-name: "alliance.conf" -*- + +from helpers.Alliance import AddMode +from helpers.Alliance import Gauge + + +allianceTop = '/soc/alliance' +cellsTop = allianceTop+'/cells/' + + +allianceConfig = \ + ( ( 'SYMB_TECHNO_NAME' , helpers.symbolicTechno ) + , ( 'REAL_TECHNO_NAME' , helpers.realTechno ) + , ( 'SYMBOLIC_TECHNOLOGY', helpers.symbolicDir+'/technology.conf' ) + , ( 'REAL_TECHNOLOGY' , helpers.realDir +'/technology.conf' ) + , ( 'DISPLAY' , helpers.sysConfDir +'/display.xml' ) + , ( 'CATALOG' , 'CATAL') + , ( 'WORKING_LIBRARY' , '.') + , ( 'SYSTEM_LIBRARY' , ( (cellsTop+'vsxlib' , Environment.Append) + , ) ) + , ( 'SCALE_X' , 100) + , ( 'IN_LO' , 'vst') + , ( 'IN_PH' , 'ap') + , ( 'OUT_LO' , 'vst') + , ( 'OUT_PH' , 'ap') + , ( 'POWER' , 'vdd') + , ( 'GROUND' , 'vss') + , ( 'CLOCK' , '^ck.*') + , ( 'BLOCKAGE' , '^blockage[Nn]et*') + ) + + +# Format of routingGaugesTable (dictionary): +# A list of entry of the form: +# ( METAL_NAME, (Direction, Type, depth, density, offset, pitch, wire_width, via_width) ) + +routingGaugesTable = {} + +routingGaugesTable['vsxlib'] = \ + ( ( 'METAL1', ( Gauge.Vertical , Gauge.PinOnly, 0, 0.0, 0, 10, 3, 3 ) ) + , ( 'METAL2', ( Gauge.Horizontal, Gauge.Default, 1, 0.0, 0, 10, 3, 3 ) ) + , ( 'METAL3', ( Gauge.Vertical , Gauge.Default, 2, 0.0, 0, 10, 3, 3 ) ) + , ( 'METAL4', ( Gauge.Horizontal, Gauge.Default, 3, 0.0, 0, 10, 3, 3 ) ) + , ( 'METAL5', ( Gauge.Vertical , Gauge.Default, 4, 0.0, 0, 10, 4, 4 ) ) + #, ( 'METAL6', ( Gauge.Horizontal, Gauge.Default, 5, 0.0, 0, 10, 4, 2 ) ) + #, ( 'METAL7', ( Gauge.Vertical , Gauge.Default, 6, 0.0, 0, 10, 4, 2 ) ) + ) + + +# Format of cellGaugesTable (dictionary): +# A list of entry of the form: +# ( METAL_PIN, xy_common_pitch, slice_height, slice_step ) + +cellGaugesTable = {} +cellGaugesTable['vsxlib'] = ('metal2', 10, 100, 10) + diff --git a/crlcore/etc/scmos_deep_018/display.conf b/crlcore/etc/scmos_deep_018/display.conf new file mode 100644 index 00000000..a9e4bc45 --- /dev/null +++ b/crlcore/etc/scmos_deep_018/display.conf @@ -0,0 +1,9 @@ +# -*- Mode:Python; explicit-buffer-name: "display.conf" -*- + +import helpers + +# Provides standard settings for: +# - +# - + +execfile( helpers.sysConfDir+'/common/display.conf' ) diff --git a/crlcore/etc/scmos_deep_018/hMetis.conf b/crlcore/etc/scmos_deep_018/hMetis.conf new file mode 100644 index 00000000..c25d7eee --- /dev/null +++ b/crlcore/etc/scmos_deep_018/hMetis.conf @@ -0,0 +1,5 @@ +# -*- Mode:Python; explicit-buffer-name: "hMetis.conf" -*- + +import helpers + +execfile( helpers.sysConfDir+'/common/hMetis.conf' ) diff --git a/crlcore/etc/scmos_deep_018/kite.conf b/crlcore/etc/scmos_deep_018/kite.conf new file mode 100644 index 00000000..751e6b53 --- /dev/null +++ b/crlcore/etc/scmos_deep_018/kite.conf @@ -0,0 +1,23 @@ +# -*- Mode:Python; explicit-buffer-name: "kite.conf" -*- + +import helpers + +# Contains the layout (shared by all technologies). +execfile( helpers.sysConfDir+'/common/kite.conf' ) + + +parametersTable = \ + ( ("katabatic.globalLengthThreshold",TypeInt ,1450 ) # Katabatic parameters. + , ("katabatic.saturateRatio" ,TypePercentage,80 ) + , ("katabatic.saturateRp" ,TypeInt ,8 ) + , ('katabatic.topRoutingLayer' ,TypeString , 'METAL5') + # Kite parameters. + , ("kite.hTracksReservedLocal" ,TypeInt ,4 , { 'min':0, 'max':18 } ) + , ("kite.vTracksReservedLocal" ,TypeInt ,3 , { 'min':0, 'max':18 } ) + , ("kite.eventsLimit" ,TypeInt ,4000002 ) + , ("kite.ripupCost" ,TypeInt ,3 , { 'min':0 } ) + , ("kite.strapRipupLimit" ,TypeInt ,16 , { 'min':1 } ) + , ("kite.localRipupLimit" ,TypeInt ,9 , { 'min':1 } ) + , ("kite.globalRipupLimit" ,TypeInt ,5 , { 'min':1 } ) + , ("kite.longGlobalRipupLimit" ,TypeInt ,5 , { 'min':1 } ) + ) diff --git a/crlcore/etc/scmos_deep_018/mauka.conf b/crlcore/etc/scmos_deep_018/mauka.conf new file mode 100644 index 00000000..f594fc4f --- /dev/null +++ b/crlcore/etc/scmos_deep_018/mauka.conf @@ -0,0 +1,5 @@ +# -*- Mode:Python; explicit-buffer-name: "mauka.conf" -*- + +import helpers + +execfile( helpers.sysConfDir+'/common/mauka.conf' ) diff --git a/crlcore/etc/scmos_deep_018/misc.conf b/crlcore/etc/scmos_deep_018/misc.conf new file mode 100644 index 00000000..20255cf3 --- /dev/null +++ b/crlcore/etc/scmos_deep_018/misc.conf @@ -0,0 +1,9 @@ +# -*- Mode:Python; explicit-buffer-name: "misc.conf" -*- + +import helpers + +# Provides standard settings for: +# # - +# # - +# +execfile( helpers.sysConfDir+'/common/misc.conf' ) diff --git a/crlcore/etc/scmos_deep_018/nimbus.conf b/crlcore/etc/scmos_deep_018/nimbus.conf new file mode 100644 index 00000000..1f0a04b0 --- /dev/null +++ b/crlcore/etc/scmos_deep_018/nimbus.conf @@ -0,0 +1,5 @@ +# -*- Mode:Python; explicit-buffer-name: "nimbus.conf" -*- + +import helpers + +execfile( helpers.sysConfDir+'/common/nimbus.conf' ) diff --git a/crlcore/etc/scmos_deep_018/patterns.conf b/crlcore/etc/scmos_deep_018/patterns.conf new file mode 100644 index 00000000..cd7ecff5 --- /dev/null +++ b/crlcore/etc/scmos_deep_018/patterns.conf @@ -0,0 +1,5 @@ +# -*- Mode:Python; explicit-buffer-name: "patterns.conf" -*- + +import helpers + +execfile( helpers.sysConfDir+'/common/patterns.conf' ) diff --git a/crlcore/etc/scmos_deep_018/plugins.conf b/crlcore/etc/scmos_deep_018/plugins.conf new file mode 100644 index 00000000..5f1a7244 --- /dev/null +++ b/crlcore/etc/scmos_deep_018/plugins.conf @@ -0,0 +1,19 @@ +# -*- Mode:Python; explicit-buffer-name: "plugins.conf" -*- + +import helpers + +# Contains the layout (shared by all technologies). +#execfile( helpers.sysConfDir+'/common/plugins.conf' ) + + +# WARNING: Those values have not been adjusted yet for this technologies. +# Must be done. +# +# Parameters for chip plugin. +parametersTable = \ + ( ("chip.block.rails.count" ,TypeInt ,4 ) + , ("chip.block.rails.hWidth" ,TypeInt ,12 ) + , ("chip.block.rails.vWidth" ,TypeInt ,12 ) + , ("chip.block.rails.hSpacing" ,TypeInt ,6 ) + , ("chip.block.rails.vSpacing" ,TypeInt ,6 ) + ) diff --git a/crlcore/etc/scmos_deep_018/stratus1.conf b/crlcore/etc/scmos_deep_018/stratus1.conf new file mode 100644 index 00000000..338bc34c --- /dev/null +++ b/crlcore/etc/scmos_deep_018/stratus1.conf @@ -0,0 +1,15 @@ +# -*- Mode:Python; explicit-buffer-name: "stratus1.conf" -*- + +import helpers + + +# Status1 parameters. +parametersTable = \ + ( ("stratus1.mappingName", TypeString, helpers.sysConfDir+"/stratus2sxlib.xml", + { 'flags':Cfg.Parameter.Flags.NeedRestart|Cfg.Parameter.Flags.MustExist } ) + , ("stratus1.format" , TypeString, "vst") + , ("stratus1.simulator" , TypeString, "asimut") + ,) + + +execfile( helpers.sysConfDir+'/common/stratus1.conf' ) diff --git a/crlcore/etc/scmos_deep_018/technology.conf b/crlcore/etc/scmos_deep_018/technology.conf new file mode 100644 index 00000000..de0e12fa --- /dev/null +++ b/crlcore/etc/scmos_deep_018/technology.conf @@ -0,0 +1,167 @@ +# -*- Mode:Python; explicit-buffer-name: "technology.conf" -*- + +import helpers + +# The informations here are extracted from the Alliance ".rds" file, +# and must be consistent with it. +# +# Provides standard settings for: +# - +# - +# - +# - + +execfile( helpers.sysConfDir+'/common/technology.conf' ) + + +# Format of : +# Each entry is a pair of (string, value). +# * string: a synthetic way to designate the symbolic layer on which +# it applies, an optional real layer in case where there is +# more than one, and the dimension name. +# * value : the rule (dimension) value expressed in lambda. + +symbolicRulesTable = \ + ( ('NWELL.nWell.extention.cap' , 4.0) + , ('PWELL.pWell.extention.cap' , 4.0) + + , ('NTIE.minimum.width' , 3.0) + , ('NTIE.nWell.extention.cap' , 3.0) + , ('NTIE.nWell.extention.width' , 1.0) + , ('NTIE.nImplant.extention.cap' , 3.0) + , ('NTIE.nImplant.extention.width' , 1.0) + , ('NTIE.active.extention.cap' , 2.0) + , ('NTIE.active.extention.width' , 0.0) + + , ('PTIE.minimum.width' , 3.0) + , ('PTIE.pWell.extention.cap' , 3.0) + , ('PTIE.pWell.extention.width' , 1.0) + , ('PTIE.pImplant.extention.cap' , 1.0) + , ('PTIE.pImplant.extention.width' , 1.0) + , ('PTIE.active.extention.cap' , 2.0) + , ('PTIE.active.extention.width' , 0.0) + + , ('NDIF.minimum.width' , 3.0) + , ('NDIF.nImplant.extention.cap' , 5.0) + , ('NDIF.nImplant.extention.width' , 3.0) + , ('NDIF.active.extention.cap' , 2.0) + , ('NDIF.active.extention.width' , 0.0) + + , ('PDIF.minimum.width' , 3.0) + , ('PDIF.pImplant.extention.cap' , 5.0) + , ('PDIF.pImplant.extention.width' , 3.0) + , ('PDIF.active.extention.cap' , 2.0) + , ('PDIF.active.extention.width' , 0.0) + + , ('GATE.minimum.width' , 2.0) + , ('GATE.poly.extention.cap' , 2.5) + + , ('NTRANS.minimum.width' , 2.0) + , ('NTRANS.nImplant.extention.cap' , 3.0) + , ('NTRANS.nImplant.extention.width' , 8.0) + , ('NTRANS.active.extention.cap' , 0.0) + , ('NTRANS.active.extention.width' , 5.0) + , ('NTRANS.poly.extention.cap' , 2.5) + , ('NTRANS.poly.extention.width' , 0.0) + + , ('PTRANS.minimum.width' , 2.0) + , ('PTRANS.nWell.extention.cap' , 3.0) + , ('PTRANS.nWell.extention.width' , 8.0) + , ('PTRANS.pImplant.extention.cap' , 3.0) + , ('PTRANS.pImplant.extention.width' , 8.0) + , ('PTRANS.active.extention.cap' , 0.0) + , ('PTRANS.active.extention.width' , 5.0) + , ('PTRANS.poly.extention.cap' , 2.5) + , ('PTRANS.poly.extention.width' , 0.0) + + , ('POLY.minimum.width' , 2.0) + , ('POLY.poly.extention.cap' , 1.0) + , ('POLY2.minimum.width' , 2.0) + , ('POLY2.poly2.extention.cap' , 2.0) + + # Routing Layers. + , ('METAL1.minimum.width' , 3.0) + , ('METAL1.metal1.extention.cap' , 2.0) + , ('METAL2.minimum.width' , 3.0) + , ('METAL2.metal2.extention.cap' , 2.0) + , ('METAL3.minimum.width' , 3.0) + , ('METAL3.metal3.extention.cap' , 2.0) + , ('METAL4.minimum.width' , 3.0) + , ('METAL4.metal4.extention.cap' , 2.0) + , ('METAL5.minimum.width' , 3.0) + , ('METAL5.metal5.extention.cap' , 2.0) + , ('METAL6.minimum.width' , 4.0) + , ('METAL6.metal6.extention.cap' , 4.0) + , ('METAL7.minimum.width' , 2.0) + , ('METAL7.metal6.extention.cap' , 4.0) + , ('METAL8.minimum.width' , 2.0) + , ('METAL8.metal6.extention.cap' , 4.0) + + # Contacts (i.e. Active <--> Metal). + , ('CONT_BODY_N.minimum.side' , 2.0) + , ('CONT_BODY_N.nWell.enclosure' , 3.0) + , ('CONT_BODY_N.nImplant.enclosure' , 3.0) + , ('CONT_BODY_N.active.enclosure' , 1.0) + , ('CONT_BODY_N.metal1.enclosure' , 1.0) + + , ('CONT_BODY_P.minimum.side' , 2.0) + , ('CONT_BODY_P.pWell.enclosure' , 3.0) + , ('CONT_BODY_P.pImplant.enclosure' , 3.0) + , ('CONT_BODY_P.active.enclosure' , 1.0) + , ('CONT_BODY_P.metal1.enclosure' , 1.0) + + , ('CONT_DIF_N.minimum.side' , 2.0) + , ('CONT_DIF_N.nImplant.enclosure' , 2.0) + , ('CONT_DIF_N.active.enclosure' , 1.0) + , ('CONT_DIF_N.metal1.enclosure' , 1.0) + + , ('CONT_DIF_P.minimum.side' , 2.0) + , ('CONT_DIF_P.pImplant.enclosure' , 2.0) + , ('CONT_DIF_P.active.enclosure' , 1.0) + , ('CONT_DIF_P.metal1.enclosure' , 1.0) + + , ('CONT_POLY.minimum.width' , 2.0) + , ('CONT_POLY.poly.enclosure' , 1.0) + , ('CONT_POLY.metal1.enclosure' , 1.0) + + # VIAs (i.e. Metal <--> Metal). + , ('VIA12.minimum.side' , 3.0) + , ('VIA12.metal1.enclosure' , 1.0) + , ('VIA12.metal2.enclosure' , 1.0) + , ('VIA23.minimum.side' , 3.0) + , ('VIA23.metal2.enclosure' , 1.0) + , ('VIA23.metal3.enclosure' , 1.0) + , ('VIA34.minimum.side' , 3.0) + , ('VIA34.metal3.enclosure' , 1.0) + , ('VIA34.metal4.enclosure' , 1.0) + , ('VIA45.minimum.side' , 3.0) + , ('VIA45.metal4.enclosure' , 1.0) + , ('VIA45.metal5.enclosure' , 1.0) + , ('VIA56.minimum.side' , 4.0) + , ('VIA56.metal5.enclosure' , 3.0) + , ('VIA56.metal6.enclosure' , 3.0) + , ('VIA67.minimum.side' , 2.0) + , ('VIA67.metal6.enclosure' , 3.0) + , ('VIA67.metal7.enclosure' , 3.0) + , ('VIA78.minimum.side' , 2.0) + , ('VIA78.metal7.enclosure' , 3.0) + , ('VIA78.metal8.enclosure' , 3.0) + + # Blockages. + , ('BLOCKAGE1.minimum.width' , 1.0) + , ('BLOCKAGE1.blockage1.extention.cap' , 2.0) + , ('BLOCKAGE2.minimum.width' , 2.0) + , ('BLOCKAGE2.blockage2.extention.cap' , 2.0) + , ('BLOCKAGE3.minimum.width' , 2.0) + , ('BLOCKAGE3.blockage3.extention.cap' , 2.0) + , ('BLOCKAGE4.minimum.width' , 2.0) + , ('BLOCKAGE4.blockage4.extention.cap' , 2.0) + , ('BLOCKAGE5.minimum.width' , 2.0) + , ('BLOCKAGE5.blockage5.extention.cap' , 2.0) + , ('BLOCKAGE6.minimum.width' , 2.0) + , ('BLOCKAGE6.blockage6.extention.cap' , 4.0) + , ('BLOCKAGE7.minimum.width' , 2.0) + , ('BLOCKAGE7.blockage6.extention.cap' , 4.0) + , ('BLOCKAGE8.minimum.width' , 2.0) + , ('BLOCKAGE8.blockage6.extention.cap' , 4.0) + ) diff --git a/crlcore/etc/scn6m_deep/technology.conf b/crlcore/etc/scn6m_deep/technology.conf new file mode 100644 index 00000000..411920b1 --- /dev/null +++ b/crlcore/etc/scn6m_deep/technology.conf @@ -0,0 +1,31 @@ +# -*- Mode:Python; explicit-buffer-name: "technology.conf" -*- + +technoConfig = { 'name' : 'scn6m_deep' + , 'gridValue' : 0.005 + , 'gridUnit' : DbU.UnitPowerMicro + , 'gridsPerLambda': 18 + } + +# Format of an entry in the table: +# (Symbolic_Name, CIF_Name, GDSII_Number) +realLayersTable = \ + ( ("pWell" , "CWN" , 41) + , ("nWell" , "CWP" , 42) + , ("active" , "CAA" , 43) + , ("pImplant", "CSP" , 44) + , ("nImplant", "CSN" , 45) + , ("poly" , "CPG" , 46) + , ("poly2" , "CM1" , 49) # poly2 is in fact metal1. + , ("cut0" , "CCC" , 25) + , ("metal1" , "CM1" , 49) + , ("cut1" , "CV1" , 50) + , ("metal2" , "CM2" , 51) + , ("cut2" , "CV2" , 61) + , ("metal3" , "CM3" , 62) + , ("cut3" , "CV3" , 30) + , ("metal4" , "CM4" , 31) + , ("cut4" , "CV4" , 32) + , ("metal5" , "CM5" , 33) + , ("cut5" , "CV5" , 36) + , ("metal6" , "CM6" , 37) + )