Resistor integration.
* New: In Isobar::PyResistor, manage type RPOLYH and RPOLY2PH. * Change: In Hurricane::Resistor, rename plate nets from "PIN1" and "PIN2" into "t1" and "t2" (try to respect uniform naming scheme). * New: In Karakaze/AnalogDesign.py, support for reading Resistor parameters. * New: In Orosshi, ResistorSnake.py imported from Mariam Tlili's work and associated Resistor.py to make parameter conversion. Currently we only uses vertical layout for resistors. Added METAL2 horizontal terminals for resistors.
This commit is contained in:
parent
2fa8016eaa
commit
e9ce33a857
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@ -248,17 +248,17 @@ class ErrorMessage ( Exception ):
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def catch ( errorObject ):
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def catch ( errorObject ):
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if isinstance(errorObject,ErrorMessage):
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if isinstance(errorObject,ErrorMessage):
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em = errorObject
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em = errorObject
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else:
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else:
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em = ErrorMessage( 2, errorObject )
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em = ErrorMessage( 2, errorObject )
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em.trace = traceback.extract_tb( sys.exc_info()[2] )
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em.trace = traceback.extract_tb( sys.exc_info()[2] )
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#em.scriptPath = __file__
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#em.scriptPath = __file__
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print em
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print em
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print helpers.textStackTrace( em.trace, True, em.scriptPath )
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print helpers.textStackTrace( em.trace, True, em.scriptPath )
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if Viewer.Graphics.get().isEnabled():
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if Viewer.Graphics.get().isEnabled():
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tryCont = ErrorWidget( em ).exec_()
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tryCont = ErrorWidget( em ).exec_()
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if UpdateSession.getStackSize() > 0: UpdateSession.close()
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if UpdateSession.getStackSize() > 0: UpdateSession.close()
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return
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return
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@ -62,9 +62,11 @@ extern "C" {
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}
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}
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switch ( pyType ) {
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switch ( pyType ) {
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case Resistor::LOWRES:
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case Resistor::LOWRES:
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case Resistor::HIRES: break;
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case Resistor::HIRES:
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case Resistor::RPOLYH:
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case Resistor::RPOLY2PH: break;
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default:
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default:
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PyErr_SetString ( ConstructorError, "Resistor.create(): Type argument is neither LOWRES nor HIRES." );
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PyErr_SetString ( ConstructorError, "Resistor.create(): Type argument is neither LOWRES, HIRES, RPOLYH nor RPOLY2PH." );
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return NULL;
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return NULL;
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}
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}
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@ -54,21 +54,21 @@ namespace Analog {
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void Resistor::createConnections ()
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void Resistor::createConnections ()
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{
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{
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Net* pin1 = Net::create( this, Name("PIN1") );
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Net* t1 = Net::create( this, Name("t1") );
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pin1->setExternal(true);
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t1->setExternal(true);
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Net* pin2 = Net::create( this, Name("PIN2") );
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Net* t2 = Net::create( this, Name("t2") );
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pin2->setExternal(true);
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t2->setExternal(true);
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_metaResistor = MetaResistor::create( getSubDevicesLibrary(), Name("R1") );
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_metaResistor = MetaResistor::create( getSubDevicesLibrary(), Name("R1") );
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Instance* metaResistorIns = Instance::create( this, Name("R1Instance"), _metaResistor );
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Instance* metaResistorIns = Instance::create( this, Name("R1Instance"), _metaResistor );
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setReferenceResistor( _metaResistor );
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setReferenceResistor( _metaResistor );
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Plug* mrPin1Plug = metaResistorIns->getPlug( _metaResistor->getPin1() );
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Plug* mrT1Plug = metaResistorIns->getPlug( _metaResistor->getPin1() );
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mrPin1Plug->setNet( pin1 );
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mrT1Plug->setNet( t1 );
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Plug* mrPin2Plug = metaResistorIns->getPlug( _metaResistor->getPin2() );
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Plug* mrT2Plug = metaResistorIns->getPlug( _metaResistor->getPin2() );
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mrPin2Plug->setNet( pin2 );
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mrT2Plug->setNet( t2 );
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}
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}
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@ -88,14 +88,14 @@ namespace Analog {
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unsigned int west = 0;
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unsigned int west = 0;
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unsigned int east = 2;
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unsigned int east = 2;
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unsigned int south = 4;
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unsigned int south = 4;
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unsigned int north = 6;
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unsigned int north = 8;
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unsigned int rule = 0;
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unsigned int rule = 0;
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if (net->getName() == namePin1) {
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if (net->getName() == namePin1) {
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rule = (yes << south) | (yes << east) | (yes << west);
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rule = (yes << east) | (yes << west);
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} else {
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} else {
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if (net->getName() == namePin2) {
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if (net->getName() == namePin2) {
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rule = (yes << north) | (yes << east) | (yes << west);
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rule = (yes << east) | (yes << west);
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} else {
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} else {
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cerr << Error( "Resistor::getRestriction(): Resistor device do not have Net named \"%s\"."
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cerr << Error( "Resistor::getRestriction(): Resistor device do not have Net named \"%s\"."
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, getString(net->getName()).c_str()
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, getString(net->getName()).c_str()
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@ -54,25 +54,27 @@ import Katana
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import Bora
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import Bora
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#helpers.setTraceLevel( 110 )
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helpers.setTraceLevel( 100 )
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NMOS = Transistor.NMOS
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NMOS = Transistor.NMOS
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PMOS = Transistor.PMOS
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PMOS = Transistor.PMOS
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PIP = CapacitorFamily.PIP
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PIP = CapacitorFamily.PIP
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MIM = CapacitorFamily.MIM
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MIM = CapacitorFamily.MIM
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MOM = CapacitorFamily.MOM
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MOM = CapacitorFamily.MOM
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LOWRES = ResistorFamily.LOWRES
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LOWRES = ResistorFamily.LOWRES
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HIRES = ResistorFamily.HIRES
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HIRES = ResistorFamily.HIRES
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Center = SlicingNode.AlignCenter
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RPOLYH = ResistorFamily.RPOLYH
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Left = SlicingNode.AlignLeft
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RPOLY2PH = ResistorFamily.RPOLY2PH
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Right = SlicingNode.AlignRight
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Center = SlicingNode.AlignCenter
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Top = SlicingNode.AlignTop
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Left = SlicingNode.AlignLeft
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Bottom = SlicingNode.AlignBottom
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Right = SlicingNode.AlignRight
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Unknown = SlicingNode.AlignBottom
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Top = SlicingNode.AlignTop
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VNode = 1
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Bottom = SlicingNode.AlignBottom
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HNode = 2
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Unknown = SlicingNode.AlignBottom
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DNode = 3
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VNode = 1
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HNode = 2
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DNode = 3
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def toDbU ( value ): return DbU.fromPhysical( value, DbU.UnitPowerMicro )
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def toDbU ( value ): return DbU.fromPhysical( value, DbU.UnitPowerMicro )
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@ -265,7 +267,7 @@ class AnalogDesign ( object ):
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specSize = 0
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specSize = 0
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if isderived(dspec[0],TransistorFamily): specSize = 12
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if isderived(dspec[0],TransistorFamily): specSize = 12
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elif isderived(dspec[0], CapacitorFamily): specSize = 7
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elif isderived(dspec[0], CapacitorFamily): specSize = 7
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elif isderived(dspec[0], ResistorFamily): specSize = 5
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elif isderived(dspec[0], ResistorFamily): specSize = 8
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else:
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else:
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], has unsupported device type.' \
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], has unsupported device type.' \
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% (count)
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% (count)
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@ -282,7 +284,7 @@ class AnalogDesign ( object ):
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [2] (layout style) is *not* a string.' % count
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [2] (layout style) is *not* a string.' % count
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, '%s' % str(dspec) ])
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, '%s' % str(dspec) ])
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if specSize == 12:
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if isderived(dspec[0],TransistorFamily):
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if dspec[3] not in [NMOS, PMOS]:
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if dspec[3] not in [NMOS, PMOS]:
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [3] (type) must be either NMOS or PMOS.' % count
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [3] (type) must be either NMOS or PMOS.' % count
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, '%s' % str(dspec) ])
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, '%s' % str(dspec) ])
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [11] (bulk connected) is *not* a boolean.' % count
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [11] (bulk connected) is *not* a boolean.' % count
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, '%s' % str(dspec) ])
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, '%s' % str(dspec) ])
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elif specSize == 7:
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elif isderived(dspec[0], CapacitorFamily):
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if dspec[3] not in [PIP, MIM, MOM]:
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if dspec[3] not in [PIP, MIM, MOM]:
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [3] (type) must be either PIP, MIM or MOM.' % count
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [3] (type) must be either PIP, MIM or MOM.' % count
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, '%s' % str(dspec) ])
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, '%s' % str(dspec) ])
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@ -325,11 +327,11 @@ class AnalogDesign ( object ):
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [4] (Cs) should either be *one* float or a *list* of floats.' % count
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [4] (Cs) should either be *one* float or a *list* of floats.' % count
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, '%s' % str(dspec) ])
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, '%s' % str(dspec) ])
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elif specSize == 5:
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elif isderived(dspec[0],ResistorFamily):
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if dspec[3] not in [LOWRES, HIRES]:
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if dspec[3] not in [RPOLYH, RPOLY2PH]:
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [3] (type) must be either LOWRES or HIRES.' % count
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [3] (type) must be either RPOLYH or RPOLY2PH.' % count
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, '%s' % str(dspec) ])
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, '%s' % str(dspec) ])
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if isinstance(dspec[4],float): pass
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if isinstance(dspec[5],float): pass
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else:
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else:
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [4] (resistance) must be a float.' % count
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raise Error( 3, [ 'AnalogDesign.doDevices(): \"self.devicesSpecs\" entry [%d], field [4] (resistance) must be a float.' % count
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, '%s' % str(dspec) ])
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, '%s' % str(dspec) ])
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@ -435,9 +437,15 @@ class AnalogDesign ( object ):
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device.getParameter( 'capacities' ).setValue( i, capaValues[i] )
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device.getParameter( 'capacities' ).setValue( i, capaValues[i] )
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elif isderived(dspec[0],ResistorFamily):
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elif isderived(dspec[0],ResistorFamily):
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print dspec
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device = dspec[0].create( self.library, dspec[1], dspec[3] )
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device = dspec[0].create( self.library, dspec[1], dspec[3] )
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device.getParameter( 'Layout Styles' ).setValue ( dspec[2] )
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device.getParameter( 'R' ).setValue( dspec[4] )
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device.getParameter( 'Resistance' ).setMatrix( dspec[4] )
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device.getParameter( 'W' ).setValue( toDbU(dspec[5]) )
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device.getParameter( 'L' ).setValue( toDbU(dspec[6]) )
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device.getParameter( 'bends' ).setValue( dspec[7] )
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trace( 100, '\tW:{0}\n'.format(dspec[5]) )
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trace( 100, '\tpW:{0}\n'.format(device.getParameter('W')) )
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trace( 100, '\tbends:{0}\n'.format(dspec[7]) )
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else:
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else:
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raise ErrorMessage( 1, 'AnalogDesign.doDevice(): Unknown/unsupported device "%s".' % str(dspec[0]) )
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raise ErrorMessage( 1, 'AnalogDesign.doDevice(): Unknown/unsupported device "%s".' % str(dspec[0]) )
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@ -450,6 +458,7 @@ class AnalogDesign ( object ):
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, Instance.PlacementStatus.UNPLACED )
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, Instance.PlacementStatus.UNPLACED )
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self.__dict__[ dspec[1] ] = instance
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self.__dict__[ dspec[1] ] = instance
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trace( 100, '\tAdd Instance:{0}\n'.format(dspec[1]) )
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return
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return
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@ -15,6 +15,7 @@
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CapacitorRoutedSingle.py
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CapacitorRoutedSingle.py
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MultiCapacitor.py
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MultiCapacitor.py
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ResistorSnake.py
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ResistorSnake.py
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Resistor.py
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)
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)
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install( FILES ${pythonFiles} DESTINATION ${PYTHON_SITE_PACKAGES}/oroshi )
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install( FILES ${pythonFiles} DESTINATION ${PYTHON_SITE_PACKAGES}/oroshi )
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@ -0,0 +1,80 @@
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# -*- coding: utf-8 -*-
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from Hurricane import DataBase
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from Hurricane import UpdateSession
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from Hurricane import DbU
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from Hurricane import Box
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from Hurricane import Net
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import helpers
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import helpers.io
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from helpers import trace
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helpers.setTraceLevel( 100 )
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import Analog
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import ParamsMatrix
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import oroshi
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from Analog import Device
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from ResistorSnake import Resistor
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def checkCoherency ( device, bbMode ):
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message = 'Resistor.checkCoherency(): device "%s".\n' % device.getName()
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techno = DataBase.getDB().getTechnology()
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rules = oroshi.getRules()
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resistance = device.getParameter( 'R' )
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if resistance is None:
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message += ' Missing "resistance" parameter on %s' % str(device)
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return (False, message)
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return (True, "")
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def layout ( device, bbMode ):
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trace( 100, ',+', '\tResistor.layout() called for "%s".\n' % device.getName())
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paramsMatrix = ParamsMatrix.ParamsMatrix()
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try:
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resistance = device.getParameter( 'R' ).getValue()
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width = device.getParameter( 'W' ).getValue()
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length = device.getParameter( 'L' ).getValue()
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bends = device.getParameter( 'bends' ).getValue()
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trace( 100, '\tpW:{0}\n'.format(device.getParameter('W')) )
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trace( 100, '\tresistance:{0}, width:{1}, length:{2}\n'.format(resistance,width,length) )
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typeArg = 'UnknownType'
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if device.isRPOLYH(): typeArg = 'RPOLYH'
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if device.isRPOLY2PH(): typeArg = 'RPOLY2PH'
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netsArg = [ device.getNet('t1'), device.getNet('t2') ]
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resistor = Resistor( device
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, netsArg
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, typeArg
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, resistance
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, resDim={ 'width':width, 'length':length }
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, direction='vertical'
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, bends=bends
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, shape=135
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)
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resistor.create()
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for net in netsArg:
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device.setRestrictions( net, Device.SouthBlocked|Device.NorthBlocked )
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paramsMatrix.setGlobalCapacitorParams( device.getAbutmentBox() )
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trace( 100, '++' )
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#paramsMatrix.trace()
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except Exception, e:
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helpers.io.catch( e )
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trace( 100, '---' )
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return paramsMatrix.getMatrix()
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File diff suppressed because it is too large
Load Diff
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@ -1,4 +0,0 @@
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V ALLIANCE : 6
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H capacitor,P,12/12/2019,100
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A 0,0,27184,27184
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EOF
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