From e6f18a95d37a3ca30b656b4f5a69903d93c391a3 Mon Sep 17 00:00:00 2001
From: Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
Date: Tue, 6 Apr 2021 18:19:16 +0200
Subject: [PATCH] Fix vector mapping in VHDL portmap. one/zero names in
 BlifParser.

* Bug: In Vhdl::VhdlPortmap::toVhdlPortMap(), when the mapped names
    are part of a vector, but *not* in the "downto" direction,
    unvectorize anyway. In the component declarations, vectors are
    always in "downto" order, so they must also be mapped in that
    order.
* Bug: In CRL::BlifParser::newOne() & newZero(), we have to create
    signal names different from instance names for VHDL compliance.
    This is complementary to what is done in blif2vst.
      No completely satisfied with that. Should find a more generic
    way to do it in the future.
---
 .../src/ccore/alliance/vst/VhdlPortMap.cpp    |  3 +-
 crlcore/src/ccore/blif/BlifParser.cpp         | 34 +++++++++++--------
 2 files changed, 22 insertions(+), 15 deletions(-)

diff --git a/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp b/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
index 434043f2..d6e37b00 100644
--- a/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
+++ b/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
@@ -190,7 +190,8 @@ namespace Vhdl {
           if (end    <  0) end   = bitp->getIndex();
           if (deltap == 0) deltap = delta;
   
-          if ( (delta == deltap) and ((delta == -1) or (delta == +1)) ) {
+        //if ( (delta == deltap) and ((delta == -1) or (delta == +1)) ) {
+          if ( (delta == deltap) and (delta == -1) ) {
             end = bit->getIndex();
             deltap = delta;
             continue;
diff --git a/crlcore/src/ccore/blif/BlifParser.cpp b/crlcore/src/ccore/blif/BlifParser.cpp
index 8bce7300..d5edc84f 100644
--- a/crlcore/src/ccore/blif/BlifParser.cpp
+++ b/crlcore/src/ccore/blif/BlifParser.cpp
@@ -516,9 +516,10 @@ namespace {
   {
     if (not _masterNetOne) return NULL; 
     // if (_oneInstance) return _oneInstance->getPlug( _masterNetOne )->getNet();
-    ostringstream name; name << "one_" << _supplyCount++;
-    _oneInstance = Instance::create( _cell, name.str(), _oneCell );
-    Net* one = Net::create( _cell, name.str() );
+    ostringstream sigName; sigName <<      "one_" << _supplyCount;
+    ostringstream insName; insName << "cmpt_one_" << _supplyCount++;
+    _oneInstance = Instance::create( _cell, insName.str(), _oneCell );
+    Net* one = Net::create( _cell, sigName.str() );
     _oneInstance->getPlug( _masterNetOne )->setNet( one );
     return one;
   }
@@ -528,9 +529,10 @@ namespace {
   {
     if (not _masterNetZero) return NULL;
     // if (_zeroInstance) return _zeroInstance->getPlug( _masterNetZero )->getNet();
-    ostringstream name; name << "zero_" << _supplyCount++;
-    _zeroInstance = Instance::create( _cell, name.str(), _zeroCell );
-    Net* zero = Net::create( _cell, name.str() );
+    ostringstream sigName; sigName <<      "zero_" << _supplyCount;
+    ostringstream insName; insName << "cmpt_zero_" << _supplyCount++;
+    _zeroInstance = Instance::create( _cell, insName.str(), _zeroCell );
+    Net* zero = Net::create( _cell, sigName.str() );
     _zeroInstance->getPlug( _masterNetZero )->setNet( zero );
     return zero;
   }
@@ -547,8 +549,8 @@ namespace {
       net->setDirection( (Net::Direction::Code)direction );
       if (isClock) net->setType( Net::Type::CLOCK );
 
-      // if (_cell->getName() == "alu_div0")
-      //   cerr << "alu_div0 net create:" << direction << " " << net << endl;
+      // if (_cell->getName() == "CR_dec19")
+      //   cerr << "CR_dec19 net create:" << direction << " " << net << endl;
     } else {
       net->addAlias( name );
       if (isExternal) net->setExternal( true );
@@ -557,8 +559,8 @@ namespace {
       net->setDirection( (Net::Direction::Code)direction );
       if (isClock) net->setType( Net::Type::CLOCK );
 
-      // if (_cell->getName() == "alu_div0")
-      //   cerr << "alu_div0 net merge:" << direction << " " << net << endl;
+      // if (_cell->getName() == "CR_dec19")
+      //   cerr << "CR_dec19 net merge:" << direction << " " << net << endl;
     }
     return net;
   }
@@ -608,8 +610,8 @@ namespace {
         std::swap( name1, name2 );
       }
 
-      // if (_cell->getName() == "alu_div0")
-      //   cerr << "alu_div0 alias net merge:" << net2 << " -> " << net1 << endl;
+      // if (_cell->getName() == "CR_dec19")
+      //   cerr << "CR_dec19 alias net merge:" << net2 << " -> " << net1 << endl;
 
       net1->merge( net2 ); return net1;
     }
@@ -623,8 +625,8 @@ namespace {
       net1 = Net::create( _cell, name1 );
       net1->setExternal ( false );
 
-      // if (_cell->getName() == "alu_div0")
-      //   cerr << "alu_div0 alias net create:" << net1 << endl;
+      // if (_cell->getName() == "CR_dec19")
+      //   cerr << "CR_dec19 alias net create:" << net1 << endl;
     }
 
     net1->addAlias( name2 );
@@ -854,15 +856,19 @@ namespace CRL {
       }
 
       if (tokenize.state() == Tokenize::Inputs) {
+      //cerr << "Reading .inputs of " << blifModel->getCell() << endl;
         for ( size_t i=1 ; i<blifLine.size() ; ++i ) {
           blifModel->mergeNet( blifLine[i], true, Net::Direction::IN );
         }
+      //cerr << "Reading .inputs of " << blifModel->getCell() << " DONE" << endl;
       }
 
       if (tokenize.state() == Tokenize::Outputs) {
+      //cerr << "Reading .outputs of " << blifModel->getCell() << endl;
         for ( size_t i=1 ; i<blifLine.size() ; ++i ) {
           blifModel->mergeNet( blifLine[i], true, Net::Direction::OUT );
         }
+      //cerr << "Reading .outputs of " << blifModel->getCell() << " DONE" << endl;
       }
 
       if (tokenize.state() & Tokenize::Names) {