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Oroshi - Analog Devices Layouts

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CapacitorStack Member List
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This is the complete list of members for CapacitorStack, including all inherited members.

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__init__CapacitorStack
__isMatchingSchemeOK__CapacitorStack
__isUnitCap__CapacitorStack
capacitorIdOccurenceCapacitorStack
capacitorLineCapacitorStack
capacitorMatrixCapacitorStack
createCapacitorStack
drawAbutmentBoxCapacitorStack
drawBottomPlatesRLayersCapacitorStack
drawTopPlatesRLayersCapacitorStack
getMatchingSchemeCapacitorStack
getMatrixDimCapacitorStack
getVerticalRoutingTrack_widthCapacitorStack
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Oroshi - Analog Devices Layouts

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CapacitorStack Class Reference
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Draws the layout of a compact capacitor or a matrix of adjacent identical capacitors. - More...

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Inherits CapacitorUnit.

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-Public Member Functions

def __init__
 This is the class constructor. More...
 
def __isUnitCap__
 
def __isMatchingSchemeOK__
 
def capacitorIdOccurence
 
def create
 Draw the compact or matrix of capacitors. More...
 
def capacitorLine
 Iteratively draws a horizontal or vertical line of capacitors according to the direction parameter. More...
 
def capacitorMatrix
 Draws a matrix of identical capacitors. More...
 
def drawAbutmentBox
 Draws the abutment box of the matrix or campact capacitor. More...
 
def drawBottomPlatesRLayers
 Draws the routing layers connecting the bottom plate in the matrix of capacitors. More...
 
def drawTopPlatesRLayers
 Draws the routing layers connecting the top plates in the matrix of capacitors. More...
 
def getVerticalRoutingTrack_width
 
def getMatrixDim
 
def getMatchingScheme
 
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Detailed Description

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Draws the layout of a compact capacitor or a matrix of adjacent identical capacitors.

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The matrix can be composed of one type of capacitors, either Poly-Poly or Metal-Metal in 350 nm AMS CMOS technology. When matching mode is off, every adjacent plates of any consecutive elementary capacitors are connected to each other using vertical routing layers. Otherwise, when matching mode is on, any of elementary capacitors can belong to, $ C_1 $ or $ C_2 $ according to the entered matching scheme. Thus, routing is not done in this class. In both modes, the complete routing process is done using the RoutCapacitor class.

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Constructor & Destructor Documentation

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def __init__ ( self,
 device,
 capacitance,
 capacitorType,
 abutmentBoxPosition,
 nets,
 unitCap = 0,
 matrixDim = [1,
 matchingMode = False,
 matchingScheme = [],
 dummyRing = False,
 dummyElement = False 
)
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This is the class constructor.

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Basically, the class there are three categories of attributes. There are the ones related to the capacitor caracteristics, its type, dimensions. Also, there are attributes to parametrize the class into matching mode or not and there are other attributes realted to the layout varibales. The class has defaut input values, thus, in this constructor, there are two "sub-constructors" according to the entered input parameters. The class attributes are :

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Parameters
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deviceThe Hurricane AMS device into which the layout is drawn.
capacitanceThe value of the capacitor, expressed in femto Farad (fF).
capacitorTypeCan be MIM or PIP type capacitor.
abutmentPositionRefers to the abscissa (XMin) of the bottom left corner of the abutment Box.
abutmentBoxYMinRefers to the ordinate (YMin) of the bottom left corner of the abutment Box.
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Except the two last arguments, all the parameters are common with the CapacitorUnit class because the CapacitorStack constructor calls the mother class constructor to create either a compact capacitor of capacitance value or rowNumber* columnNumber unity capacitors.

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Parameters
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rowNumberNumber of rows in the matrix of capacitors.
columnNumberNumber of columns in the matrix of capacitors.
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References CapacitorStack.__areInputDataOK__(), CapacitorUnit.__computeCapDim__(), CapacitorStack.__initGivenNonZeroUnitCap__(), CapacitorStack.__initGivenNonZeroUnitCapInMatchingMode__(), CapacitorStack.__initGivenZeroUnitCap__(), CapacitorStack.__initGivenZeroUnitCapInMatchingMode__(), CapacitorStack.__initMatrixMode__(), CapacitorUnit.__isCapacitorUnitOK__(), CapacitorStack.abutmentBox, CapacitorUnit.abutmentBox, CapacitorStack.abutmentBox_spacing, CapacitorStack.abutmentBoxPosition, CapacitorStack.capacitance, CapacitorStack.capacitorIdOccurence(), CapacitorStack.capacitorsNumber, CapacitorStack.capacitorType, CapacitorUnit.capacitorType, CapacitorStack.compactCapDim, CapacitorStack.computeUnitCap(), CapacitorStack.device, CapacitorUnit.device, Stack.device, CapacitorStack.doMatrix, CapacitorStack.dummyElement, CapacitorStack.dummyRing, CapacitorStack.dummyRingPosition, CapacitorStack.evaluateUnitCap(), CapacitorStack.matchingMode, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, CapacitorStack.minEnclosure_hRoutingLayer_topPlate_cut, CapacitorStack.minEnclosure_vRoutingTrackCut, CapacitorStack.minSpacing_vRoutingTrack, CapacitorStack.minSpacing_vRoutingTrackCut, CapacitorStack.minWidth_hRoutingLayer_topPlate_cut, CapacitorStack.minWidth_vRoutingTrack, CapacitorStack.minWidth_vRoutingTrackCut, CapacitorStack.nets, CapacitorStack.unitCapacitance, CapacitorStack.unitCapDim, and CapacitorStack.vRoutingTrack_width.

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Member Function Documentation

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def __isUnitCap__ ( self)
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True if the drawn capacitor is a compact one. This function is useful when an instance is called in another class. Example : when the matrix or the compact capacitors are to be fully routed.
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def __isMatchingSchemeOK__ ( self)
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Returns
True if the matching scheme specifications are correct. Specifications are :
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  • Similar number of elements as total number of elementary capacitor in the matrix.
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  • Capacitor identifiers equal to '1' or '2' only.
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  • Otherwise, the function returns False.
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References CapacitorStack.matchingScheme, and CapacitorStack.matrixDim.

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Referenced by CapacitorStack.capacitorIdOccurence().

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def capacitorIdOccurence ( self,
 capacitorIdentifier 
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Returns
occurence of capacitor identifier in the entered matching scheme. This is useful to verify that self.matchingScheme is correct.
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References CapacitorStack.__areMatrixDimOK__(), CapacitorStack.__isMatchingSchemeOK__(), CapacitorStack.capacitorsNumber, CapacitorStack.dummyElement, CapacitorStack.dummyRing, CapacitorStack.matchingMode, CapacitorStack.matchingScheme, and CapacitorStack.nets.

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Referenced by CapacitorStack.__init__().

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def create ( self,
 bbMode = False 
)
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Draw the compact or matrix of capacitors.

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First, . Second, . Finally, .

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References CapacitorStack.__initMatchingMode__(), CapacitorStack.abutmentBox_spacing, CapacitorStack.abutmentBoxPosition, CapacitorStack.capacitance, CapacitorStack.capacitorMatrix(), CapacitorStack.capacitorType, CapacitorUnit.capacitorType, CapacitorStack.computeBondingBoxDimensions(), CapacitorStack.device, CapacitorUnit.device, Stack.device, CapacitorStack.doMatrix, CapacitorStack.drawAbutmentBox(), CapacitorUnit.drawAbutmentBox(), CapacitorStack.drawBottomPlatesRLayers(), CapacitorStack.drawCapacitorStack(), CapacitorStack.drawTopPlatesRLayers(), CapacitorStack.dummyRing, CapacitorStack.matchingMode, CapacitorStack.matrixDim, CapacitorStack.nets, CapacitorStack.setRules(), and CapacitorUnit.setRules().

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Referenced by CapacitorStack.capacitorLine(), and CapacitorStack.capacitorMatrix().

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def capacitorLine ( self,
 dy,
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 matchingSchemeRowIndex = 0 
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Iteratively draws a horizontal or vertical line of capacitors according to the direction parameter.

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An exception is raised if the specified direction is different from {'horizontal','vertical'}. At every iteration, an instance of the CapacitorUnit class is created and its layout is drawn.

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a list containing the drawn capacitors.
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dythe vertical position of the first cut in cut line.
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Remarks
An exception is raised if the specified direction is different from {'horizontal','vertical'}
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References CapacitorStack.abutmentBoxPosition, CapacitorStack.capacitorType, CapacitorUnit.capacitorType, CapacitorStack.create(), CapacitorStack.createElementInCapacitorLine(), CapacitorStack.device, CapacitorUnit.device, Stack.device, CapacitorStack.dummyRing, CapacitorStack.matchingMode, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, CapacitorStack.nets, and CapacitorStack.unitCapacitance.

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Referenced by CapacitorStack.capacitorMatrix().

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def capacitorMatrix ( self,
 abutmentBox_spacing = 0 
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Draws a matrix of identical capacitors.

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The matrix is iterativelly constructed. At every iteration, a new horizontal line of capacitors is drawn.

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a nested list of elementary capacitors.
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References CapacitorStack.abutmentBox_spacing, CapacitorStack.abutmentBoxPosition, CapacitorStack.capacitorLine(), CapacitorStack.capacitorType, CapacitorUnit.capacitorType, CapacitorStack.create(), CapacitorStack.device, CapacitorUnit.device, Stack.device, CapacitorStack.dummyRing, CapacitorStack.getCapDim(), CapacitorStack.matrixDim, CapacitorStack.nets, and CapacitorStack.unitCapacitance.

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Referenced by CapacitorStack.create().

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def drawAbutmentBox ( self,
 abutmentBox_spacing = 0 
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Draws the abutment box of the matrix or campact capacitor.

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References CapacitorStack.abutmentBox, CapacitorUnit.abutmentBox, CapacitorStack.abutmentBox_spacing, CapacitorStack.abutmentBoxPosition, CapacitorStack.computeAbutmentBoxDimensions(), and CapacitorUnit.computeAbutmentBoxDimensions().

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Referenced by CapacitorStack.create().

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def drawBottomPlatesRLayers ( self,
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 drawnCapacitor 
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Draws the routing layers connecting the bottom plate in the matrix of capacitors.

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First, the relative positions of the routing layer is of the is extracted from the elementary capacitor instance. Then, its width is computed in a way to connect adjacent plates. Then, the routing layers are iterativelly drawn. The two borders are .

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References CapacitorStack.matrixDim, and CapacitorStack.nets.

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Referenced by CapacitorStack.create().

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def drawTopPlatesRLayers ( self,
 topPlateRLayer,
 drawnCapacitor 
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Draws the routing layers connecting the top plates in the matrix of capacitors.

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First, the relative positions of the routing layers is of the is extracted from the elementary capacitor instance. Then, its width is computed in a way to connect adjacent plates. Then, the routing layers are iterativelly drawn. The two borders are .

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Remarks
An exception is raised if the number of rows in the matrix is lower than 2.
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References CapacitorStack.matrixDim, and CapacitorStack.nets.

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Referenced by CapacitorStack.create().

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def getVerticalRoutingTrack_width ( self)
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The width of the vertical routing tracks in matching mode.
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This function is useful in matching mode, ie., in RoutCapacitor class, when routing the two capacitors.
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def getMatrixDim ( self)
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A dictionary contaning capacitor matrix's dimensions
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References CapacitorStack.compactCapDim, and CapacitorStack.doMatrix.

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def getMatchingScheme ( self)
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the matching scheme. The function is useful in RoutMatchedCapacitor class to load self.matchingScheme attribute.
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Oroshi - Analog Devices Layouts

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RoutMatchedCapacitor Member List
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This is the complete list of members for RoutMatchedCapacitor, including all inherited members.

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__computeConnections__RoutMatchedCapacitor
__init__RoutMatchedCapacitor
__setStretchingDySourceDyTarget__RoutMatchedCapacitor
__stretchTopPlateCompactCap__RoutMatchedCapacitor
__stretchTopPlates__RoutMatchedCapacitor
computeDimensionsRoutMatchedCapacitor
computeHRLayerYCenterRoutMatchedCapacitor
computeHRoutingTrackYCenterRoutMatchedCapacitor
drawCutsRoutMatchedCapacitor
drawCuts_vRoutingTrack_hRoutingTrackRoutMatchedCapacitor
drawHRLayersRoutMatchedCapacitor
drawHRoutingTracksRoutMatchedCapacitor
drawOneCut_vRoutingTrack_HRLayerRoutMatchedCapacitor
routeRoutMatchedCapacitor
setLayersRoutMatchedCapacitor
setRulesRoutMatchedCapacitor
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Oroshi - Analog Devices Layouts

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RoutMatchedCapacitor Class Reference
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Routs two matched capacitors, C1 and C2, drawn in a capacitor matrix. - More...

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Inherits CapacitorUnit, CapacitorStack, and VerticalRoutingTracks.

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def __init__
 A special method used to customize the class instance to an initial state in which : More...
 
def route
 Draws the complete layout given the capacitor matrix. More...
 
def setRules
 Defines technology rules used to draw the layout. More...
 
def setLayers
 Defines all physical layers used to draw the layout. More...
 
def computeDimensions
 Computes, through simple instructions and functions calls, layout variables detailed in Figure 2. More...
 
def computeHRoutingTrackYCenter
 Computes centers' ordinates of the eight horizontal routing tracks. More...
 
def computeHRLayerYCenter
 Sets the stretching value of top plates. More...
 
def drawHRoutingTracks
 Iteratively draws horizontal routing tracks on top and bottom positions of the matrix using physical layer routingTracksLayer. More...
 
def drawHRLayers
 Iteratively draws the horizontal routing layers starting with bottom left elementary capacitor $ C_{00} $. More...
 
def drawCuts
 Draws all required cuts using physical layers : More...
 
def drawOneCut_vRoutingTrack_HRLayer
 Draws one cut, in layer cutLayer, in order to connect a vertical routing track, at position cutXMin in metal 2, and a horizontal routing track, at position cutYMin in metal 3. More...
 
def drawCuts_vRoutingTrack_hRoutingTrack
 Draws cuts to connect vertical routing tracks in metal 2 and horizontal routing tracks in metal 3. More...
 
def __stretchTopPlates__
 Iteratively performs top plates stretching for the capacitor matrix. More...
 
def __stretchTopPlateCompactCap__
 Draws vertical stretched layers for a given elementary capacitor. More...
 
def __setStretchingDySourceDyTarget__
 Sets the abcissas of the extremities of the vertical stretching to be applied to capacitor's top plates for a given elementary capacitor in the matrix. More...
 
def __computeConnections__
 Computes horizontal routing layers source and target abcissas for top and bottom plates connections to its associated routing track. More...
 
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Detailed Description

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Routs two matched capacitors, C1 and C2, drawn in a capacitor matrix.

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Connections are put in place with reference to a given matching scheme. Elementary capacitor units are connected to horizontal and vertical routing tracks that represent top plates and bottom plates nets of C1 and C2 . Supported types of capacitors are Poly-Poly and Metal-Metal. Technologycal rules are provided by 350 nm AMS CMOS technology with three-four metal layers. Metal layers that are used for routing are placed similarly to horziontal-vertical (HV) symbolic Alliance CAD tool router, where horizontal metal channels are drawn in metal 2 and the vertical ones are in metal 3. Given a matrix of dimensions $ R*C $, the total number of vertical tracks is $ 2C+2 $ equivalent to $ C+1 $ couples, ensuring that every elementary capacitor is positioned between four vertical tracks, two from each side. In fact, every adjacent couple of these tracks represent top plates and bottom plates of C1 or C2 as shown in Figure 1.

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-Layout.png -
-Layout
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An elementary capacitor unit can be a part of C1 or C2 according to the matching scheme. However, to respect common-centroid layout specifications, for C1 and C2 to be equal, the matrix number of colums and number of rows must be both even. Addionnally, the number of elementary capacitors dedicated to C1 must be equal to those dedicated to C2. These two conditions are tested in one of the class methods. An exception is raised if at least one of the two is not respected.

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Constructor & Destructor Documentation

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def __init__ ( self,
 vRTInstance 
)
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A special method used to customize the class instance to an initial state in which :

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  • the attributes related to the capacitor matrix are copied from the CapacitorStack instance.
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Position and dimensions attributes, also refered by layout variables, in Figure 2, are defined below :

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Parameters
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deviceThe Hurricane AMS device onto which the layout is drawn.
capacitorInstanceInstance of CapacitorStack class.
capacitorA nested list containing the matrix elements, which are CapacitorUnit objects.
matchingSchemeA nested list, with equal dimensions as capacitor attribute, containing assignements of matrix elementary units to C1 and C2, identified by 1 and 2, respectively. Therefore, self.matchingScheme content is a succession of 1 and 2 values, defined as \ capacitor identifiers. For example, given a matrix of dimensions 2x2, the matching scheme can be $ [ [1,2], [1,2] ] or [ [2,1], [2,1] ] $. The first sub-list dictates that the first elementary capacitor, $ C_{00} $. The second element $ C_{01} $ is affected to C2 and so on. An immediate and obvious consequence to this, is that an error is raised if self.matchingSchem and self.capacitor dimensions are not identical or if self.matchingScheme content is different from supported capacitor identifiers, '1' and '2'.
capacitorTypeSupported types of capacitors are MIM and PIP only. An exception is raised otherwise.
abutmentBoxThe matrix's abutment box.
matrxiDimThe matrix dimensions, also equal to self.matchingScheme nested list dimensions.
abutmentBox_spacingThe spacing between elementary units in the matrix. It is computed in CapacitorStack and is reloaded in RoutMatchedCapacitor. self.abutmentBox_spacing includes, vertical routing tracks width and minimum allowed spacing between two adjacent ones.
hRoutingLayer_widthThe width of horizontal routing layers in metal 2, which connect capacitors plates to vertical routing tracks.
vRoutingTrack_widthThe width of vertical routing tracks in metal 3, which connects identical nets together ( ie : bottom plates of C1, top plates of C2, bottom plates of C2 and top plates of C2 ).
hRoutingTrack_widthThe width of horizontal routing tracks in metal 2, which connect identical vertical routing tracks together.
minSpacing_hRoutingTrackMinimum spacing between horizontal routing tracks. Wide metal 2 specifications are considered since metal 2 dimensions may exceed 10 $ m$.
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Remark:
For more information about wide metal specifications, refer to ENG-183_rev8.pdf technology manual.
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Parameters
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minimumPositionThe ordinate of the top plate's routing layer's bottom extremity after stretching.
maximumPositionThe ordinate of the top plate's routing layer's top extremity, also equivalent to the top plate's top extremity.
vRoutingTrackXCenterA nested list of ordered dictionaries, with dimensions equal to self.matrixDim, containing abcissas of vertical routing tracks. All sub-lists' lengths are identical and are equal to 2. The first and second elements describe position of top plate track and bottom plate track, respectively. For example, given a matrix of dimensions 2x2, self.vRoutingTrackXCenter can be [[0, 2], [4,6], [8,10]] $ \mu m$. Elements of this nested list have particular indexing as described in Figure 2.
hRoutingtrackYCenterA nested dictonary containing two keys, topTracks and bottomTracks. Each key contains as value a dictionary describing centers' ordinates of four parallel horizontal tracks. The reason why four tracks are needed on top and bottom positions of the matrix is that four nets are used, two for every capacitor Ci, were i is in [1,2].
hRoutingLayerYCenterA nested dicitonary containing two keys, top and bottom. Each key contains as value a dictionary describing centers' ordinates of horizontal routing layers.
vRoutingTrackDictA dictionary of routing tracks top and bottom extremities ordinates.
topPlateStretchingSince not only the same metal 2 layer is used to draw top/bottom plates connections to vertical tracks but also the two plates are superimposed, the top plate's routing tracks is stretched. self.topPlateStretching is therefore the length added to top plate's routing layer in order to avoid short circuits between top and bottom plates routing to vertical tracks since the same metal is used for both.
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References RoutMatchedCapacitor.capacitor, CapacitorStack.dummyRing, RoutMatchedCapacitor.dummyRing, RoutMatchedCapacitor.dummyRingCapacitor, RoutMatchedCapacitor.hRoutingLayer_width, RoutMatchedCapacitor.hRoutingLayerYCenter, RoutMatchedCapacitor.hRoutingTrack_width, RoutMatchedCapacitor.hRoutingtrackYCenter, CapacitorStack.matrixDim, VerticalRoutingTracks.matrixDim, RoutMatchedCapacitor.maximumPosition, RoutMatchedCapacitor.minimumPosition, RoutMatchedCapacitor.minSpacing_hRoutingTrack, RoutMatchedCapacitor.topPlateStretching, and RoutMatchedCapacitor.vRTInstance.

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Member Function Documentation

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def route ( self,
 bbMode = False 
)
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Draws the complete layout given the capacitor matrix.

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route method is succession of calls to user-defined methods inside a newly created Updatesession. The following tasks are excecuted :

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  1. A nex UpdateSession is created,
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  2. all required physical layers are loaded,
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  4. layout dimension parameters are computed,
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  5. routing tracks and layers are drawn,
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  6. top plates are stretched,
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  7. all required cuts are drawn,
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  8. The UpdateSession is closed.
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Meanwhile, an exception is raised when the entered capacitor is not a capacitor matrix or if the capacitor type is unsupported.

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References RoutMatchedCapacitor.__stretchTopPlates__(), RoutMatchedCapacitor.capacitor, RoutMatchedCapacitor.computeDimensions(), CapacitorUnit.computeDimensions(), Stack.computeDimensions(), RoutMatchedCapacitor.drawCuts(), RoutMatchedCapacitor.drawDummyRing_hRTracks_Cuts(), RoutMatchedCapacitor.drawHRLayers(), RoutMatchedCapacitor.drawHRoutingTracks(), CapacitorStack.dummyRing, RoutMatchedCapacitor.dummyRing, RoutMatchedCapacitor.dummyRingCapacitor, VerticalRoutingTracks.getVTrackYMax(), VerticalRoutingTracks.getVTrackYMin(), CapacitorUnit.hpitch, RoutMatchedCapacitor.hRoutingtrackYCenter, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, VerticalRoutingTracks.matrixDim, RoutMatchedCapacitor.maximumPosition, CapacitorUnit.metal3Width, RoutMatchedCapacitor.minimumPosition, VerticalRoutingTracks.nets, CapacitorStack.nets, RoutMatchedCapacitor.routeDummyRing(), RoutMatchedCapacitor.routeLeftAndRightSides(), RoutMatchedCapacitor.routeTopOrBottomSide(), RoutMatchedCapacitor.setLayers(), CapacitorStack.setRules(), CapacitorUnit.setRules(), RoutMatchedCapacitor.setRules(), CapacitorUnit.vpitch, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, and RoutMatchedCapacitor.vRoutingTrackXCenter.

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def setRules ( self)
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Defines technology rules used to draw the layout.

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Some of the rules, namely those describing routing layers and tracks are applicable for both MIM and PIP capacitors. However, cuts rules are different.

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Remark:
All CapacitorStack class rules are also reloaded in this class. An exception is raised if the entered capacitor type is unsupported.
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Returns
a dictionary with rules labels as keys and rules content as values.
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References CapacitorStack.capacitorType, CapacitorUnit.capacitorType, RoutMatchedCapacitor.capacitorType, CapacitorStack.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minSpacing_hRoutingLayer, RoutMatchedCapacitor.minSpacing_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minSpacing_hRoutingLayer_vRoutingTrack_cut, RoutMatchedCapacitor.minSpacing_hRoutingTrackCut, CapacitorStack.minSpacing_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_vRoutingTrackCut, CapacitorStack.minWidth_hRoutingLayer_topPlate_cut, and RoutMatchedCapacitor.minWidth_hRoutingLayer_topPlate_cut.

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Referenced by RoutMatchedCapacitor.route(), and VerticalRoutingTracks.setRules().

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def setLayers ( self)
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Defines all physical layers used to draw the layout.

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Layers are loaded using DataBase API. The same routing layers are used for both capacitor types except cuts layers that connect top plates to vertical routing tracks. Basicaly, metal 2, meta 3, cut 1 and cut 2 are the ones defined.

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Returns
a dictionary composed of layers labels as keys and layers as values.
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References CapacitorStack.capacitorType, CapacitorUnit.capacitorType, RoutMatchedCapacitor.capacitorType, CapacitorStack.dummyRing, and RoutMatchedCapacitor.dummyRing.

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Referenced by RoutMatchedCapacitor.route().

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def computeDimensions ( self,
 bbMode 
)
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Computes, through simple instructions and functions calls, layout variables detailed in Figure 2.

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References CapacitorStack.abutmentBox_spacing, RoutMatchedCapacitor.abutmentBox_spacing, VerticalRoutingTracks.capacitorsNumber, CapacitorStack.capacitorsNumber, RoutMatchedCapacitor.computeBondingBoxDimInbbMode(), RoutMatchedCapacitor.computeHRLayerYCenter(), RoutMatchedCapacitor.computeHRoutingTrackYCenter(), RoutMatchedCapacitor.hRoutingLayer_width, CapacitorStack.matrixDim, VerticalRoutingTracks.matrixDim, RoutMatchedCapacitor.maximumPosition, CapacitorStack.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minEnclosure_hRoutingLayer_topPlate_cut, VerticalRoutingTracks.minEnclosure_hRoutingLayer_vRoutingTrack_cut, RoutMatchedCapacitor.minimumPosition, VerticalRoutingTracks.minWidth_hRoutingLayer, CapacitorStack.minWidth_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minWidth_hRoutingLayer_topPlate_cut, VerticalRoutingTracks.minWidth_hRoutingLayer_vRoutingTrack_cut, RoutMatchedCapacitor.vRoutingTrack_spacing, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, RoutMatchedCapacitor.vRoutingTrackDict, and RoutMatchedCapacitor.vRoutingTrackXCenter.

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Referenced by RoutMatchedCapacitor.route().

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def computeHRoutingTrackYCenter ( self)
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Computes centers' ordinates of the eight horizontal routing tracks.

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The tracks include four on top and four on bottom of the matrix. To do the computations, fist, center of the first bottom or top track, given in Figure 2, is computed. Then, all adjacent three centers are deduced by simples translation of the first one. Translation quantity is equal to the sum of distance between adjacent routing tracks, self.hRoutingTracks_spacing, and half width of the routing track itself, self.hRoutingTrack_width.

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References RoutMatchedCapacitor.__setPlatesIds__(), CapacitorUnit.hpitch, RoutMatchedCapacitor.hRoutingtrackYCenter, RoutMatchedCapacitor.maximumPosition, and RoutMatchedCapacitor.minimumPosition.

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Referenced by RoutMatchedCapacitor.computeDimensions().

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def computeHRLayerYCenter ( self)
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Sets the stretching value of top plates.

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Then iteratively computes the centers of horizontal routing layer regarding top and bottom plates.

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References RoutMatchedCapacitor.__findPossibleShortCircuits__(), VerticalRoutingTracks.__setStretching__(), RoutMatchedCapacitor.__setStretchingDySourceDyTarget__(), RoutMatchedCapacitor.bondingBox, RoutMatchedCapacitor.capacitor, RoutMatchedCapacitor.hRoutingLayer_width, RoutMatchedCapacitor.hRoutingLayerYCenter, RoutMatchedCapacitor.hRoutingTrack_width, RoutMatchedCapacitor.hRoutingtrackYCenter, CapacitorStack.matrixDim, VerticalRoutingTracks.matrixDim, RoutMatchedCapacitor.minSpacing_hRoutingLayer, RoutMatchedCapacitor.topPlateStretching, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, and RoutMatchedCapacitor.vRoutingTrackXCenter.

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Referenced by RoutMatchedCapacitor.computeDimensions().

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def drawHRoutingTracks ( self,
 routingTracksLayer 
)
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Iteratively draws horizontal routing tracks on top and bottom positions of the matrix using physical layer routingTracksLayer.

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References RoutMatchedCapacitor.hRoutingTrack_width, RoutMatchedCapacitor.hRoutingtrackYCenter, VerticalRoutingTracks.nets, CapacitorStack.nets, and RoutMatchedCapacitor.vRoutingTrackXCenter.

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Referenced by RoutMatchedCapacitor.route().

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def drawHRLayers ( self,
 xPlateRLayer 
)
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Iteratively draws the horizontal routing layers starting with bottom left elementary capacitor $ C_{00} $.

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References RoutMatchedCapacitor.__computeConnections__(), RoutMatchedCapacitor.hRoutingLayer_width, RoutMatchedCapacitor.hRoutingLayerYCenter, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, VerticalRoutingTracks.matrixDim, CapacitorStack.matrixDim, VerticalRoutingTracks.nets, and CapacitorStack.nets.

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Referenced by RoutMatchedCapacitor.route().

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def drawCuts ( self,
 layer_hRTrack_hRLayer,
 layer_tracksCut,
 layer_topPlateCut 
)
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Draws all required cuts using physical layers :

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  • layer_hRTrack_hRLayer to connect bottom plates to vertical routing tracks,
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  • layer_tracksCut to connect vertical routing tracks to horizontal ones,
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References RoutMatchedCapacitor.__setPlatesLabels__(), VerticalRoutingTracks.capacitorIds, VerticalRoutingTracks.capacitorsNumber, CapacitorStack.capacitorsNumber, RoutMatchedCapacitor.drawCuts_stretchedTopPlate(), RoutMatchedCapacitor.drawCuts_vRoutingTrack_HRLayer(), RoutMatchedCapacitor.drawCuts_vRoutingTrack_hRoutingTrack(), RoutMatchedCapacitor.drawOneCut_vRoutingTrack_HRLayer(), RoutMatchedCapacitor.hRoutingLayerYCenter, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, VerticalRoutingTracks.matrixDim, CapacitorStack.matrixDim, CapacitorStack.minEnclosure_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_hRoutingTrackCut, CapacitorStack.minSpacing_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_vRoutingTrackCut, VerticalRoutingTracks.minWidth_hRoutingTrackCut, CapacitorStack.minWidth_vRoutingTrackCut, VerticalRoutingTracks.nets, CapacitorStack.nets, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, and RoutMatchedCapacitor.vRoutingTrackXCenter.

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Referenced by RoutMatchedCapacitor.route().

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def drawOneCut_vRoutingTrack_HRLayer ( self,
 net,
 cutLayer,
 cutXMin,
 cutYMin,
 cutNumber 
)
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Draws one cut, in layer cutLayer, in order to connect a vertical routing track, at position cutXMin in metal 2, and a horizontal routing track, at position cutYMin in metal 3.

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References RoutMatchedCapacitor.minSpacing_hRoutingLayer_vRoutingTrack_cut, and VerticalRoutingTracks.minWidth_hRoutingLayer_vRoutingTrack_cut.

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Referenced by RoutMatchedCapacitor.drawCuts().

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def drawCuts_vRoutingTrack_hRoutingTrack ( self,
 cutLayer,
 cutNumber,
 enclosure_cut 
)
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Draws cuts to connect vertical routing tracks in metal 2 and horizontal routing tracks in metal 3.

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References RoutMatchedCapacitor.__setPlatesIds__(), RoutMatchedCapacitor.capacitor, RoutMatchedCapacitor.dummyRingCapacitor, RoutMatchedCapacitor.hRoutingLayerYCenter, RoutMatchedCapacitor.hRoutingtrackYCenter, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, VerticalRoutingTracks.matrixDim, CapacitorStack.matrixDim, CapacitorStack.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minEnclosure_hRoutingLayer_topPlate_cut, CapacitorStack.minEnclosure_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minSpacing_hRoutingTrackCut, CapacitorStack.minSpacing_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_vRoutingTrackCut, CapacitorStack.minWidth_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minWidth_hRoutingLayer_topPlate_cut, VerticalRoutingTracks.minWidth_hRoutingTrackCut, CapacitorStack.minWidth_vRoutingTrackCut, VerticalRoutingTracks.nets, CapacitorStack.nets, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, and RoutMatchedCapacitor.vRoutingTrackXCenter.

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Referenced by RoutMatchedCapacitor.drawCuts().

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def __stretchTopPlates__ ( self,
 capacitor,
 rlayer 
)
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Iteratively performs top plates stretching for the capacitor matrix.

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Vertical segments are connected to top plate routing layer.

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Parameters
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capacitorCapacitor matrix.
rlayerLayer of the drawn vertical rectangle.
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References RoutMatchedCapacitor.__stretchTopPlateCompactCap__(), VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, VerticalRoutingTracks.matrixDim, CapacitorStack.matrixDim, VerticalRoutingTracks.nets, and CapacitorStack.nets.

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Referenced by RoutMatchedCapacitor.route().

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def __stretchTopPlateCompactCap__ ( self,
 net,
 capacitor,
 routingLayer,
 j = 0 
)
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Draws vertical stretched layers for a given elementary capacitor.

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References RoutMatchedCapacitor.__setStretchingDySourceDyTarget__(), and RoutMatchedCapacitor.topPlateStretching.

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Referenced by RoutMatchedCapacitor.__stretchTopPlates__().

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def __setStretchingDySourceDyTarget__ ( self,
 capacitor,
 deltay 
)
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Sets the abcissas of the extremities of the vertical stretching to be applied to capacitor's top plates for a given elementary capacitor in the matrix.

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Parameters
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capacitor.values() Elementary unit capacitor.
deltayStretching value.
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A list that contains dySource and as top extremity and bottom extermity, respectively.
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Referenced by RoutMatchedCapacitor.__stretchTopPlateCompactCap__(), and RoutMatchedCapacitor.computeHRLayerYCenter().

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def __computeConnections__ ( self,
 i,
 j,
 capacitorIdentifier 
)
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Computes horizontal routing layers source and target abcissas for top and bottom plates connections to its associated routing track.

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Parameters
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(i,j)row and column indexes, respectively, in the matrix which describe the elementary capacitor position in the matrix.
capacitorIdentifierequal to '1' if C1 and '2' if C2.
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Returns
A nested dicitionary. The overal dictionary is composed of keys equal to topPlate and bottomPlate and values equal to sub-dictionaries. The sub-dictionaries, are in their turn composed of two keys standing for the abcissa of the source and the abcissa of the target.
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Remark:
Naturally, an exception is raised if an unsupported capacitor identifier is given.
- -

References RoutMatchedCapacitor.__findHRLDyTrarget__(), RoutMatchedCapacitor.__isCapacitorAdummy__(), RoutMatchedCapacitor.__setPlatesLabels__(), RoutMatchedCapacitor.capacitor, VerticalRoutingTracks.capacitorIds, VerticalRoutingTracks.capacitorsNumber, CapacitorStack.capacitorsNumber, CapacitorStack.dummyElement, RoutMatchedCapacitor.dummyElement, CapacitorStack.dummyRing, RoutMatchedCapacitor.dummyRing, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, VerticalRoutingTracks.matrixDim, CapacitorStack.matrixDim, VerticalRoutingTracks.nets, CapacitorStack.nets, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, RoutMatchedCapacitor.vRoutingTrackXCenter, and RoutMatchedCapacitor.vRTsDistribution.

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Referenced by RoutMatchedCapacitor.drawHRLayers().

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Oroshi - Analog Devices LayoutsCopyright © 2018-2018 UPMC. All rights reserved
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Oroshi - Analog Devices Layouts

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CapacitorUnit Member List
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This is the complete list of members for CapacitorUnit, including all inherited members.

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__computeCapDim__CapacitorUnit
__init__CapacitorUnit
__isCapacitorUnitOK__CapacitorUnit
__setCapacitorPerUnit__CapacitorUnit
computeBottomPlateCutsCapacitorUnit
computeTopPlateCutsCapacitorUnit
createCapacitorUnit
cutLineCapacitorUnit
cutMatrixCapacitorUnit
cutMaxNumberCapacitorUnit
drawAbutmentBoxCapacitorUnit
drawBottomPlateCutCapacitorUnit
drawCapacitorCapacitorUnit
drawOnePlateCapacitorUnit
drawRoutingLayersCapacitorUnit
drawTopPlateCutCapacitorUnit
getBotPlateLeftRLayerXCenterCapacitorUnit
getBotPlateLeftRLayerXMaxCapacitorUnit
getBotPlateLeftRLayerXMinCapacitorUnit
getBotPlateRightRLayerXCenterCapacitorUnit
getBotPlateRLayerWidthCapacitorUnit
getBotPlateRLayerYMaxCapacitorUnit
getBotPlateRLayerYMinCapacitorUnit
getBottomPlateLeftCutXMinCapacitorUnit
getBottomPlateLeftCutYMaxCapacitorUnit
getBottomPlateLeftCutYMinCapacitorUnit
getBottomPlateRightCutXMinCapacitorUnit
getBottomPlateRightCutYCenterCapacitorUnit
getBottomPlateRightCutYMaxCapacitorUnit
getBottomPlateRightCutYMinCapacitorUnit
getBottomPlateYMaxCapacitorUnit
getCapacitorTypeCapacitorUnit
getLayersCapacitorUnit
getMaximumCapWidthCapacitorUnit
getMinimumCapWidthCapacitorUnit
getTopPlateRLayerWidthCapacitorUnit
getTopPlateRLayerXCenterCapacitorUnit
getTopPlateRLayerXMaxCapacitorUnit
getTopPlateRLayerXMinCapacitorUnit
getTopPlateRLayerYMaxCapacitorUnit
getTopPlateRLayerYMinCapacitorUnit
setRulesCapacitorUnit
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Oroshi - Analog Devices Layouts

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-Public Member Functions | -List of all members
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CapacitorUnit Class Reference
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Draws a capacitor of type Poly-Poly or Metal-Metal in 350 nm AMS CMOS technology. - More...

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-Public Member Functions

def __init__
 This is the class constructor. More...
 
def __setCapacitorPerUnit__
 Sets the area and perimeter capacitances as specified in 350 nm AMS technology and according to capacitorType (MIM or PIP). More...
 
def __computeCapDim__
 Computes width and length of the capacitor. More...
 
def __isCapacitorUnitOK__
 Checks if the computed capacitor dimensions exceed or are less than maximum and minimum limits, respectively, as specified in technology rules. More...
 
def setRules
 Selects technological rules according to the capacitor type. More...
 
def getCapacitorType
 
def getMaximumCapWidth
 maximum size of capacitor's top plate. More...
 
def getMinimumCapWidth
 
def getLayers
 Loads the technology file then extracts the adequate layers according to the capacitor type (MIM or PIP). More...
 
def create
 When bonding box mode is activated, the function draws all layout physical layers of the capacitor after checking its dimensions. More...
 
def drawCapacitor
 Draws all layout physicial layers of the capacitor. More...
 
def computeBottomPlateCuts
 Computes needed parameters to draw bottom plate cuts in its exact position, including : More...
 
def computeTopPlateCuts
 Computes needed parameters to draw top plate cuts in its exact position, including : More...
 
def drawAbutmentBox
 Draws the abutment box of the capacitor in position <(abutmentBoxXMin, abutmentBoxYMin)>. More...
 
def drawOnePlate
 Draws the top or bottom plate through inflation of the Box under it. More...
 
def drawBottomPlateCut
 Draws the required cuts to connect the bottom plate. More...
 
def drawTopPlateCut
 Draws the top plate's cuts after computing the maximal number of cuts that can be placed and its exact enclosure in the top plate. More...
 
def drawRoutingLayers
 Draws the routing layers of both bottom and top plates after computing widths and the exact position of these layers. More...
 
def cutMaxNumber
 Computes the maximal number of cuts to be placed on a layer of width width_layer considering specifications such as the spacing between the cuts, its width and its enclosure in the layer. More...
 
def cutLine
 Creates a horizontal or vertical line of contacts according to the specified direction. More...
 
def cutMatrix
 Creates a matrix of cuts by vertically stacking horizontal lines of identical cuts. More...
 
def getBottomPlateYMax
 
def getBottomPlateLeftCutXMin
 
def getBottomPlateLeftCutYMin
 
def getBottomPlateLeftCutYMax
 
def getBottomPlateRightCutXMin
 
def getBottomPlateRightCutYMin
 
def getBottomPlateRightCutYMax
 
def getBotPlateLeftRLayerXMax
 
def getBottomPlateRightCutYCenter
 
def getBotPlateLeftRLayerXMin
 
def getBotPlateRLayerYMin
 
def getBotPlateRLayerYMax
 
def getBotPlateRLayerWidth
 
def getBotPlateRightRLayerXCenter
 
def getBotPlateLeftRLayerXCenter
 
def getTopPlateRLayerYMin
 
def getTopPlateRLayerYMax
 
def getTopPlateRLayerWidth
 
def getTopPlateRLayerXCenter
 
def getTopPlateRLayerXMin
 
def getTopPlateRLayerXMax
 
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Detailed Description

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Draws a capacitor of type Poly-Poly or Metal-Metal in 350 nm AMS CMOS technology.

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PIP and MIM capacitors are the result of surface superposition between poly1 and poly2 or metal2 and metalcap layers, respectively. Given the capacitor value, layout dimensions are computed, then, capacitor layers are drawn. Capacitor value, $C$, is given in the expression below, where $ C_{a}, C_{p}, A $ and $ P $ are, area capacitance, perimeter capacitance, area and permiter of the capacitor, respectively :

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-\[ C = C_{a}A + C_{p}P \] -

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The drawn layout shape is square. Thus, metcap or poly2 length and width are equal and are computed using the capacitor expression. Furthermore, given $ C_{a} $, $ C_{p} $ and enclosure technological rules, dimensions and positions of the abutment box as well as the bottom plate are computed. Layouts with dimensions that exceed technological limits cannot be drawn.

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Constructor & Destructor Documentation

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def __init__ ( self,
 device,
 capacitorType,
 abutmentBoxPosition,
 capacitance = 0,
 capDim = {} 
)
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This is the class constructor.

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Few of the class attributes final values are computed in this level. Most of attributes are only initialized to zero or empty values. Then, it is computed in dedicated class method. Input parameters are :

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Parameters
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deviceHurricane AMS device into which layout is drawn.
capacitanceCapacitor value, expressed in $ femto Farad (fF) $.
abutmentBoxPositionA list containing abscissa and ordinate of the bottom left corner of the abutment box.
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Class attributes are described in the list below. Most of class attributes refer to layout dimensions. Dictionaries are used to group attributes related to the same layout varibale. Layout dimensions and variables are described in Figure 1.

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Parameters
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deviceHurricane AMS device into which layout is drawn.
capacitanceCapacitor value, expressed in $ femto Farad (fF) $.
capacitorTypeCan be 'MIMCap' or 'PIPCap' as capacitor type.
abutmentBoxDictA dictionary containing abscissa and ordinate of the bottom left corner of the abutment box, (XMin) and (YMin), respectively.
abutmentBoxAbutment box drawn square. It is an object of type Box.
bottomPlateBoxBottom plate drawn square. It is an object of type Box.
topPlateBoxTop plate drawn square. It is an object of type Box.
cut2MatrixDictA dictionary containing center position of the left bottom, which is cut the first to be drawn in the matrix of cuts. Initially, the dictionary is empty. It is only updated when self.capacitorType is equal to 'MIMCap'.
cutLeftLineDictA dictionary containing abcissa and ordinate of the bottom cut in the left line of cuts to be drawn on bottom plate's layer.
cutRightLineDictA dictionary containing abcissa and ordinate of the bottom cut in the right line of cuts to be drawn on bottom plate's layer.
topCutLineDictA dictionary containing abcissa and ordinate of the bottom cut in the right line of cuts to be drawn on top plate's layer. Initially, the dictionary is empty. It is only updated when self.capacitorType is equal to 'PIPCap'.
topPlateRLayerDictA dictionary containing position information of the top plate's routing layer. The dictionary includes ordinates of the layer's top and bottom extremities, 'XMin' and 'YMin', respectively, the abcissa of it's center, 'XCenter' and its width, 'width'.
bottomPlateRLayerDictA dictionary containing
enclosure_botPlate_topPlateTop plate's layer encolusre in bottom plate's layer.
minheight_topPlatecutMinimum height of cuts for top plate connection to other metal layer.
topCutLineNumberMaximum possible number cuts to be drawn for top plate's connection.
bottomCutLineNumberMaximum possible number cuts to be drawn for top plate's connection.
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Remark:
Abutment box must be defined as an attribute because the position of dummy capacitor in NonUnitCapacitor class must be precisely defined.
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References CapacitorUnit.__computeCapacitance__(), CapacitorUnit.__computeCapDim__(), CapacitorUnit.__initCapDim__(), CapacitorUnit.abutmentBox, CapacitorUnit.abutmentBoxDict, CapacitorUnit.bottomCutLineNumber, CapacitorUnit.bottomPlateBox, CapacitorUnit.bottomPlateBoxDict, CapacitorUnit.bottomPlateRLayerDict, CapacitorUnit.capacitorType, CapacitorUnit.capDim, CapacitorUnit.cut2MatrixDict, CapacitorUnit.cutLeftLineDict, CapacitorUnit.cutRightLineDict, CapacitorUnit.device, Stack.device, CapacitorUnit.enclosure_botPlate_abtBox, CapacitorUnit.enclosure_botPlate_topPlate, CapacitorUnit.minheight_topPlatecut, CapacitorUnit.topCutLineDict, CapacitorUnit.topCutLineNumber, CapacitorUnit.topPlateBox, CapacitorUnit.topPlateBoxDict, and CapacitorUnit.topPlateRLayerDict.

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Member Function Documentation

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def __setCapacitorPerUnit__ ( self,
 capacitorType 
)
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Sets the area and perimeter capacitances as specified in 350 nm AMS technology and according to capacitorType (MIM or PIP).

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Returns
a list containing the area and perimeter capacitances.
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Remarks
An exception is raised if the entered capacitor type is unknown.
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Referenced by CapacitorUnit.__computeCapDim__().

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def __computeCapDim__ ( self,
 capacitance,
 capacitorType 
)
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Computes width and length of the capacitor.

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Given capacitance value as well as the permiter and area capacitances, a quadratic equation is solved where the unknown parameter is the width (also equivalent to the length).

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Returns
a dictionary containing width and length.
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Remark:
The capacitor is square. Thus, length and width are equal.
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References CapacitorUnit.__setCapacitorPerUnit__().

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Referenced by CapacitorStack.__init__(), and CapacitorUnit.__init__().

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def __isCapacitorUnitOK__ ( self,
 capDim 
)
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Checks if the computed capacitor dimensions exceed or are less than maximum and minimum limits, respectively, as specified in technology rules.

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Returns
True if all rules are respected.
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Remark:
Maximum poly2 layer dimensions for PIP capacitor are not specified in technology rules. Thus, only minimum limit condition is checked.
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References CapacitorUnit.capacitorType, CapacitorUnit.getMaximumCapWidth(), and CapacitorUnit.getMinimumCapWidth().

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Referenced by CapacitorStack.__init__(), and CapacitorUnit.create().

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def setRules ( self)
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Selects technological rules according to the capacitor type.

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Returns
a dictionary with rules labels as keys and rules as values. Example of technology rules are :
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  • minimum spacing between cuts or metals,
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  • etc. Every rule takes two possible value according to the capacitor type (MIM or PIP). Therefore, dictionary keys are generic and its values are specific to the capacitor type.
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Remark:
An exception is raised if the entered capacitor type is unknown.
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References CapacitorUnit.capacitorType, CapacitorUnit.hpitch, CapacitorUnit.isVH, Stack.isVH, CapacitorUnit.METAL2Pitch, CapacitorUnit.metal2Width, CapacitorUnit.METAL3Pitch, CapacitorUnit.metal3Width, CapacitorUnit.minEnclo_botPlate_botPlateCut, CapacitorUnit.minEnclo_botPlateRMetal_botPlateCut, CapacitorUnit.minEnclo_routingTrackMetal_cut, CapacitorUnit.minEnclo_topPlate_topPlateCut, CapacitorUnit.minEnclo_topPlateRMetal_topPlateCut, CapacitorUnit.minheight_topPlatecut, CapacitorUnit.minSpacing_botPlate, CapacitorUnit.minSpacing_botPlateCut_topPlate, CapacitorUnit.minSpacingOnBotPlate_cut, CapacitorUnit.minSpacingOnTopPlate_cut, CapacitorUnit.minWidth_botPlatecut, CapacitorUnit.minWidth_botRMetal, CapacitorUnit.minWidth_routingTrackcut, CapacitorUnit.minWidth_topPlate, CapacitorUnit.minWidth_topPlatecut, CapacitorUnit.minWidth_topRMetal, and CapacitorUnit.vpitch.

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Referenced by CapacitorStack.create(), CapacitorUnit.create(), RoutMatchedCapacitor.route(), and VerticalRoutingTracks.setRules().

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def getCapacitorType ( self)
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Returns
capacitor type 'MIMCap' or 'PIPCap'.
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Remarks
getCapacitorType() is especially useful when an instance of CapacitorUnit class is called in another classes instances to identify the capacitor's type.
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def getMaximumCapWidth ( self)
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maximum size of capacitor's top plate.

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getMaximumCapWidth() is called to check if capacitor dimensions are within acceptable technological limits. An exception is raised if the entered capacitor type is unknown.

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Remarks
1. This function is especially usefull in drawing the layout of a unity capacitor, where it is important to garantee that the capacitor size does not exeed the maximum possible value. It is also useful when drawing a matrix of capacitors to make sure that also the unity capacitor respects the maximal values specified.
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-2. The maximum value of the poly2 size in PIP capacitor is not specified. Thus, it is not considered in getMaximumCapWidth()
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References CapacitorUnit.capacitorType.

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Referenced by CapacitorUnit.__isCapacitorUnitOK__().

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def getMinimumCapWidth ( self)
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Returns
The minimum size of the capacitor's top plate. An exception is raised if the entered capacitor type is unknown.
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Remarks
This function is especially usefull in drawing the layout of a matrix of capacitors where it is important to ensure that the unity capacitor respects the minimal values specified.
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References CapacitorUnit.capacitorType.

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Referenced by CapacitorUnit.__isCapacitorUnitOK__().

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def getLayers ( self)
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Loads the technology file then extracts the adequate layers according to the capacitor type (MIM or PIP).

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Returns
a dictionary containing the layer labels as attributes and its values.
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Remarks
An exception is raised if the entered capacitor type is unknown.
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References CapacitorUnit.capacitorType.

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Referenced by CapacitorUnit.create().

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def create ( self,
 t,
 b,
 bbMode = False,
 vEnclosure_botPlate_abtBox = None,
 hEnclosure_botPlate_abtBox = None 
)
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When bonding box mode is activated, the function draws all layout physical layers of the capacitor after checking its dimensions.

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All functions are excecuted in a new Update Session. In the contrary, only an exact estimation of layout dimensions is given. An error is raised when dimensions reach technological limits for MIM and PIP capacitors or when bbMode parameters is other than True or False.

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Parameters
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(t , b ) nets of top and bottom plates, respectively
bbModeactivates bonding box dimensions computing when set to True
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References CapacitorUnit.__isCapacitorUnitOK__(), CapacitorUnit.abutmentBoxDict, CapacitorUnit.capDim, CapacitorUnit.computeDimensions(), Stack.computeDimensions(), CapacitorUnit.drawAbutmentBox(), CapacitorUnit.drawCapacitor(), Technology.getLayers(), CapacitorUnit.getLayers(), and CapacitorUnit.setRules().

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def drawCapacitor ( self,
 layerDict,
 t,
 b 
)
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Draws all layout physicial layers of the capacitor.

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Parameters
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layerDicta dictionary containing a description of the required physical layers according to capacitor type
(t , b ) nets of top and bottom plates, respectively
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References CapacitorUnit.bottomPlateBox, CapacitorUnit.bottomPlateBoxDict, CapacitorUnit.drawBottomPlateCut(), CapacitorUnit.drawOnePlate(), CapacitorUnit.drawRoutingLayers(), CapacitorUnit.drawTopPlateCut(), CapacitorUnit.topPlateBox, and CapacitorUnit.topPlateBoxDict.

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Referenced by CapacitorUnit.create().

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def computeBottomPlateCuts ( self)
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Computes needed parameters to draw bottom plate cuts in its exact position, including :

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  • adjusted enclosure of
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Given parameters described above, it is possible to draw the entire lines of cuts on both sides of bottom plate using cutLine function.

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References CapacitorUnit.bottomCutLineNumber, CapacitorUnit.bottomPlateBoxDict, CapacitorUnit.cutLeftLineDict, CapacitorUnit.cutMaxNumber(), CapacitorUnit.cutRightLineDict, CapacitorUnit.minEnclo_botPlate_botPlateCut, CapacitorUnit.minheight_topPlatecut, CapacitorUnit.minSpacing_botPlateCut_topPlate, CapacitorUnit.minSpacingOnBotPlate_cut, CapacitorUnit.minWidth_topPlatecut, and CapacitorUnit.topPlateBoxDict.

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Referenced by CapacitorUnit.drawAbutmentBox().

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def computeTopPlateCuts ( self)
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Computes needed parameters to draw top plate cuts in its exact position, including :

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  • adjusted enclosure of
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Given parameters described above, it is possible to draw the entire lines of cuts on both sides of bottom plate using cutLine function.

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References CapacitorUnit.abutmentBoxDict, CapacitorUnit.bottomPlateBoxDict, CapacitorUnit.bottomPlateRLayerDict, CapacitorUnit.capacitorType, CapacitorUnit.cut2MatrixDict, CapacitorUnit.cutLeftLineDict, CapacitorUnit.cutMaxNumber(), CapacitorUnit.cutRightLineDict, CapacitorUnit.enclosure_botPlate_topPlate, CapacitorUnit.hEnclosure_botPlate_abtBox, CapacitorUnit.minEnclo_botPlate_botPlateCut, CapacitorUnit.minEnclo_botPlateRMetal_botPlateCut, CapacitorUnit.minEnclo_routingTrackMetal_cut, CapacitorUnit.minEnclo_topPlate_topPlateCut, CapacitorUnit.minEnclo_topPlateRMetal_topPlateCut, CapacitorUnit.minheight_topPlatecut, CapacitorUnit.minSpacing_botPlate, CapacitorUnit.minSpacing_botPlateCut_topPlate, CapacitorUnit.minSpacingOnTopPlate_cut, CapacitorUnit.minWidth_botPlatecut, CapacitorUnit.minWidth_botRMetal, CapacitorUnit.minWidth_routingTrackcut, CapacitorUnit.minWidth_topPlatecut, CapacitorUnit.setBottomPlateAbtBoxEnclosure(), CapacitorUnit.topCutLineDict, CapacitorUnit.topCutLineNumber, CapacitorUnit.topPlateBoxDict, CapacitorUnit.topPlateRLayerDict, and CapacitorUnit.vEnclosure_botPlate_abtBox.

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Referenced by CapacitorUnit.drawAbutmentBox().

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def drawAbutmentBox ( self)
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Draws the abutment box of the capacitor in position <(abutmentBoxXMin, abutmentBoxYMin)>.

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First, the minimum enclosure of the top plate inside the bottom plate is computed. Second, using this parameters as well as the capacitor dimensions, the width and height of the abutment box are computed. The box is finally drawn.

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References CapacitorUnit.abutmentBox, CapacitorUnit.abutmentBoxDict, CapacitorUnit.bottomPlateBoxDict, CapacitorUnit.computeAbutmentBoxDimensions(), CapacitorUnit.computeBottomPlateCuts(), CapacitorUnit.computeOnePlateBoxDimensions(), CapacitorUnit.computeRoutingLayersDimensions(), CapacitorUnit.computeTopPlateCuts(), CapacitorUnit.enclosure_botPlate_topPlate, CapacitorUnit.hEnclosure_botPlate_abtBox, CapacitorUnit.topPlateBoxDict, and CapacitorUnit.vEnclosure_botPlate_abtBox.

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Referenced by CapacitorStack.create(), and CapacitorUnit.create().

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def drawOnePlate ( self,
 layer,
 net,
 boxDimensions 
)
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Draws the top or bottom plate through inflation of the Box under it.

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These boxes are the abutment box in the case of the bottom plate and the bottom plate's box in the case of the top plate. This function also creates a a net for the drawn plate and sets it as external.

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Returns
The drawn box.
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Referenced by CapacitorUnit.drawCapacitor().

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def drawBottomPlateCut ( self,
 layer,
 b 
)
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Draws the required cuts to connect the bottom plate.

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First, the maximal possible number of cuts that can be drawn is computed. Second, using the computed number, the enclosure of this cuts in the bottom plate's layer is adjusted while the minimal enclosure is respected. Third, the relative positions of the cuts on both sides of the plate are computed. Finally, two vertical lines of cuts are drawns.

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Remark:
The relative positions describe the cordinates of the first bottom cut in every line of cuts. Then, knowing the spacing and width specifications of these cuts the rest of the line is easilly constructed.
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References CapacitorUnit.bottomCutLineNumber, CapacitorUnit.cutLeftLineDict, CapacitorUnit.cutLine(), CapacitorUnit.cutRightLineDict, CapacitorUnit.minheight_topPlatecut, CapacitorUnit.minSpacingOnBotPlate_cut, and CapacitorUnit.minWidth_botPlatecut.

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Referenced by CapacitorUnit.drawCapacitor().

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def drawTopPlateCut ( self,
 layer,
 t 
)
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Draws the top plate's cuts after computing the maximal number of cuts that can be placed and its exact enclosure in the top plate.

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References CapacitorUnit.capacitorType, CapacitorUnit.cut2MatrixDict, CapacitorUnit.cutLine(), CapacitorUnit.cutMatrix(), CapacitorUnit.minheight_topPlatecut, CapacitorUnit.minSpacingOnTopPlate_cut, CapacitorUnit.minWidth_topPlatecut, CapacitorUnit.topCutLineDict, and CapacitorUnit.topCutLineNumber.

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Referenced by CapacitorUnit.drawCapacitor().

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def drawRoutingLayers ( self,
 bottomPlateLayer,
 topPlateLayer,
 t,
 b 
)
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Draws the routing layers of both bottom and top plates after computing widths and the exact position of these layers.

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Also computes positions if rlayers that are crucial for routing.

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References CapacitorUnit.bottomPlateRLayerDict, CapacitorUnit.cutLeftLineDict, CapacitorUnit.cutRightLineDict, and CapacitorUnit.topPlateRLayerDict.

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Referenced by CapacitorUnit.drawCapacitor().

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def cutMaxNumber ( self,
 width_layer,
 width_cut,
 spacing_cut,
 enclosure_cut 
)
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Computes the maximal number of cuts to be placed on a layer of width width_layer considering specifications such as the spacing between the cuts, its width and its enclosure in the layer.

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Referenced by CapacitorUnit.computeBottomPlateCuts(), and CapacitorUnit.computeTopPlateCuts().

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def cutLine ( self,
 net,
 layer,
 firstCutXCenter,
 firstCutYCenter,
 width_cut,
 height_cut,
 spacing_cut,
 cutNumber,
 direction 
)
-
- -

Creates a horizontal or vertical line of contacts according to the specified direction.

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Referenced by CapacitorUnit.cutMatrix(), CapacitorUnit.drawBottomPlateCut(), and CapacitorUnit.drawTopPlateCut().

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def cutMatrix ( self,
 net,
 layer,
 firstCutXCenter,
 firstCutYCenter,
 width_cut,
 height_cut,
 spacing_cut,
 cutColumnNumber,
 cutRowNumber 
)
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Creates a matrix of cuts by vertically stacking horizontal lines of identical cuts.

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Parameters
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netnet to which the cuts belong
layercuts physical layer
firstCutXCentercenter's abcissa of the bottom left cut ( that is the first cut to be drawn in the matrix )
firstCutYCentercenter's abcissa of the bottom left cut
(width_cut,height_cut,spacing_cut)cuts dimenions
(cutColumnNumber,cutRowNumber)matrix dimensions
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Remarks
The matrix can have any dimensions zero or negative one.
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References CapacitorUnit.cutLine().

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Referenced by CapacitorUnit.drawTopPlateCut().

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def getBottomPlateYMax ( self)
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the ordinate of the bottom plate's highest end-point ( that is equivalent to dySource of the bottom plate's box ) .
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References CapacitorUnit.bottomPlateBoxDict.

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the abcissa of the bottom plate's left line of cuts.
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def getBottomPlateLeftCutYMin ( self)
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the ordinate of the first ( or bottom) cut in the left line of cuts on the bottom plate.
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def getBottomPlateLeftCutYMax ( self)
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the ordinate of the highest cut of the bottom plate's left line of cuts.
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References CapacitorUnit.bottomCutLineNumber, CapacitorUnit.minSpacingOnBotPlate_cut, and CapacitorUnit.minWidth_botPlatecut.

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the absissa of the bottom plate's right line of cuts.
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the ordinate of the first ( or bottom) cut in the right line of cuts on the bottom plate.
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Referenced by CapacitorUnit.getBottomPlateRightCutYCenter().

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def getBottomPlateRightCutYMax ( self)
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the ordinate of the highest ( or top) cut in the right line of cuts on the bottom plate.
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References CapacitorUnit.bottomCutLineNumber, CapacitorUnit.minSpacingOnBotPlate_cut, and CapacitorUnit.minWidth_botPlatecut.

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Referenced by CapacitorUnit.getBottomPlateRightCutYCenter().

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def getBotPlateLeftRLayerXMax ( self)
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the center's ordinate of the bottom plate's left cut (the cut that is the first one in the line).
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def getBottomPlateRightCutYCenter ( self)
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Returns
the position of the bottom plate's right cuts on the horitontal axis (also applicable to left cuts).
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References CapacitorUnit.getBottomPlateRightCutYMax(), and CapacitorUnit.getBottomPlateRightCutYMin().

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def getBotPlateLeftRLayerXMin ( self)
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the position of the bottom plate's left cuts on the horitontal axis.
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def getBotPlateRLayerYMin ( self)
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the position of bottom plate's left cuts on the horitontal axis.
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the position of bottom plate's left cuts on the horitontal axis.
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def getBotPlateRLayerWidth ( self)
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the position of bottom plate's left cuts on the horitontal axis.
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def getBotPlateRightRLayerXCenter ( self)
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the position of bottom plate's left cuts on the horitontal axis.
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the position of bottom plate's left cuts on the horitontal axis.
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def getTopPlateRLayerYMin ( self)
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the ordinate of the bottom end points of the top plate routing layer.
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def getTopPlateRLayerYMax ( self)
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the ordinate of the higher end points of the top plate routing layer.
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the width of top plate's routing layer.
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the center's abcissa of the bottom plate routing layer.
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def getTopPlateRLayerXMin ( self)
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Returns
the origin (bottom-left end point) abcissa of the top plate routing layers.
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References CapacitorUnit.topPlateRLayerDict.

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def getTopPlateRLayerXMax ( self)
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Returns
the abscissa of the bottom-right end-point of the top plate routing layer.
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References CapacitorUnit.topPlateRLayerDict.

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Oroshi - Analog Devices LayoutsCopyright © 2018-2018 UPMC. All rights reserved
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Oroshi - Analog Devices Layouts

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VerticalRoutingTracks Member List
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This is the complete list of members for VerticalRoutingTracks, including all inherited members.

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__setStretching__VerticalRoutingTracks
drawVRoutingTracksVerticalRoutingTracks
setRulesVerticalRoutingTracks
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Oroshi - Analog Devices Layouts

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-Public Member Functions | -List of all members
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VerticalRoutingTracks Class Reference
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Route two matched capacitors, C1 and C2, drawn in a capacitor matrix. - More...

- -

Inherits CapacitorUnit, and CapacitorStack.

- - - - - - - - - - - -

-Public Member Functions

def __setStretching__
 Sets vertical stretching value considering spacing between elementary capacitors in the matrix. More...
 
def setRules
 Defines technology rules used to draw the layout. More...
 
def drawVRoutingTracks
 Iteratively draws vertical routing tracks given the physical layer vRoutingTracksLayer. More...
 
-

Detailed Description

-

Route two matched capacitors, C1 and C2, drawn in a capacitor matrix.

-

Connections are put in place with reference to a given matching scheme. Elementary capacitor units are connected to horizontal and vertical routing tracks that represent top plates and bottom plates nets of C1 and C2. Supported types of capacitors are Poly-Poly and Metal-Metal. Technologycal rules are provided by 350 nm AMS CMOS technology with three-four metal layers. Metal layers that are used for routeing are placed similarly to horziontal-vertical (HV) symbolic Alliance CAD tool router, where horizontal metal channels are drawn in metal 2 and the vertical ones are in metal 3. Given a matrix of dimensions $ R*C $, the total number of vertical tracks is $ 2C+2 $ equivalent to $ C+1 $ couples, ensuring that every elementary capacitor is positioned between four vertical tracks, two from each side. In fact, every adjacent couple of these tracks represent top plates and bottom plates of C1 or C2 as shown in Figure 1.

-
-Layout.png -
-Layout
-

An elementary capacitor unit can be a part of C1 or C2 according to the matching scheme. However, to respect common-centroid layout specifications, for C1 and C2 to be equal, the matrix number of colums and number of rows must be both even. Addionnally, the number of elementary capacitors dedicated to C1 must be equal to those dedicated to C2. These two conditions are tested in one of the class methods. An exception is raised if at least one of the two is not respected.

-

Member Function Documentation

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def __setStretching__ ( self)
-
- -

Sets vertical stretching value considering spacing between elementary capacitors in the matrix.

-
Returns
stratching value.
- -

References VerticalRoutingTracks.abutmentBox_spacing, CapacitorStack.abutmentBox_spacing, and RoutMatchedCapacitor.abutmentBox_spacing.

- -

Referenced by RoutMatchedCapacitor.computeHRLayerYCenter(), and VerticalRoutingTracks.drawVRoutingTracks().

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def setRules ( self)
-
- -

Defines technology rules used to draw the layout.

-

Some of the rules, namely those describing routeing layers and tracks are applicable for both MIM and PIP capacitors. However, cuts rules are different.

-
Remark:
All CapacitorStack class rules are also reloaded in this class. An exception is raised if the entered capacitor type is unsupported.
-
Returns
a dictionary with rules labels as keys and rules content as values.
- -

References VerticalRoutingTracks.capacitorsNumber, CapacitorStack.capacitorsNumber, VerticalRoutingTracks.computeVRTDimensions(), VerticalRoutingTracks.drawVRoutingTracks(), VerticalRoutingTracks.minEnclosure_hRoutingLayer_vRoutingTrack_cut, VerticalRoutingTracks.minEnclosure_hRoutingTrackCut, VerticalRoutingTracks.minimizeVRTs(), VerticalRoutingTracks.minSpacing_hRoutingTrack, RoutMatchedCapacitor.minSpacing_hRoutingTrack, VerticalRoutingTracks.minWidth_hRoutingLayer, VerticalRoutingTracks.minWidth_hRoutingLayer_vRoutingTrack_cut, VerticalRoutingTracks.minWidth_hRoutingTrack, VerticalRoutingTracks.minWidth_hRoutingTrackCut, VerticalRoutingTracks.setRules(), CapacitorStack.setRules(), CapacitorUnit.setRules(), and RoutMatchedCapacitor.setRules().

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Referenced by VerticalRoutingTracks.setRules().

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def drawVRoutingTracks ( self,
 vRoutingTracksLayer 
)
-
- -

Iteratively draws vertical routing tracks given the physical layer vRoutingTracksLayer.

-

Every elementary capacitor is consequently positioned between four routing tracks, two from each side. Each couple of adjacent routeing tracks represent top plate and bottom plate nets of Ci, where i is in [1,2]. As given in Figure 2, capacitor $ C_{ij} $ with an even j value situated in even columns have and inversely for odd columns numbers.

- -

References VerticalRoutingTracks.__computeVRTsNumber__(), VerticalRoutingTracks.__findCapIdsToEliminate__(), VerticalRoutingTracks.__findCapIdsToEliminatePerColumn__(), VerticalRoutingTracks.__findUsedCapIdsPerColumn__(), VerticalRoutingTracks.__findVRTsToEliminate__(), VerticalRoutingTracks.__setNetsDistribution__(), VerticalRoutingTracks.__setPlatesDistribution__(), VerticalRoutingTracks.__setStretching__(), VerticalRoutingTracks.__setVRTsDistribution__(), VerticalRoutingTracks.abutmentBox_spacing, CapacitorStack.abutmentBox_spacing, RoutMatchedCapacitor.abutmentBox_spacing, VerticalRoutingTracks.capacitorIds, VerticalRoutingTracks.capacitorsNumber, CapacitorStack.capacitorsNumber, VerticalRoutingTracks.computeXCenters(), VerticalRoutingTracks.dummyElement, CapacitorStack.dummyElement, RoutMatchedCapacitor.dummyElement, VerticalRoutingTracks.dummyRing, CapacitorStack.dummyRing, RoutMatchedCapacitor.dummyRing, VerticalRoutingTracks.getVTrackYMax(), VerticalRoutingTracks.getVTrackYMin(), CapacitorUnit.hpitch, RoutMatchedCapacitor.hRoutingTrack_width, VerticalRoutingTracks.hRoutingTrack_width, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, VerticalRoutingTracks.matrixDim, RoutMatchedCapacitor.maximumPosition, VerticalRoutingTracks.maximumPosition, CapacitorUnit.metal2Width, VerticalRoutingTracks.minEnclosure_hRoutingTrackCut, VerticalRoutingTracks.minimizeVRT, RoutMatchedCapacitor.minimumPosition, VerticalRoutingTracks.minimumPosition, VerticalRoutingTracks.minWidth_hRoutingTrack, VerticalRoutingTracks.minWidth_hRoutingTrackCut, VerticalRoutingTracks.nets, CapacitorStack.nets, VerticalRoutingTracks.platesDistribution, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, VerticalRoutingTracks.vRoutingTrackDict, RoutMatchedCapacitor.vRoutingTrackDict, VerticalRoutingTracks.vRoutingTrackXCenter, RoutMatchedCapacitor.vRoutingTrackXCenter, VerticalRoutingTracks.vRTsDistribution, RoutMatchedCapacitor.vRTsDistribution, and VerticalRoutingTracks.vRTsToEliminate.

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Referenced by VerticalRoutingTracks.setRules().

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The documentation for this class was generated from the following file: -
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Generated by doxygen 1.8.5 on Thu Mar 19 2020Return to top of page
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Oroshi - Analog Devices LayoutsCopyright © 2018-2018 UPMC. All rights reserved
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Oroshi - Analog Devices Layouts

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Stack Member List
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This is the complete list of members for Stack, including all inherited members.

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__init__Stack
computeDimensionsStack
doLayoutStack
setWiringsStack
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Oroshi - Analog Devices Layouts

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Stack Class Reference
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Draw a Stack of Transistors. - More...

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Inherits object.

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-Public Member Functions

def __init__
 [API] Constructor More...
 
def setWirings
 [API] Set the Stack wiring specification. More...
 
def computeDimensions
 [internal] Compute Stack dimensions from the technological rules. More...
 
def doLayout
 [API] Draw the complete layout. More...
 
-

Detailed Description

-

Draw a Stack of Transistors.

-

A Stack of Transistors is a set of transistor put into a regular band and connected through their sources/drains. All share the exact same W & L. The way they are connecteds defines what functionnality the Stack implement.

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The abutment box of the stack is adjusted so that both height and width are even multiples of the track pitches, so the device can be easily placed and handled by the mixed router. The extra space needed for padding is added around the active area. Due to the presence of tracks at the top and bottom of the stack, the active area will be horizontally centered but not vertically.

-

The drawing of the stack is controlled through a set of variables (attributes) that allows to create it regardless of the technology. The technology is taken into account in the way those variables are computed and, obviously, their values. The following schematics details the main stack drawing variables along with their computations.

-

-Stack Layout

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-Gate pitch

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  • self.gatePitch : the pitch of transistors gates, inside the stack. It also applies to dummy transistors.
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-gate-pitch-1.png -
-Gate Pitch
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-Active Side Width

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  • self.activeSideWidth : the distance between the axis of the last transistor gate (on the left or right) and the edge of the active area (not the diffusion area).
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-active-side-width-1.png -
-Active Side Width
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-H-Track Distance

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  • self.hTrackDistance : the minimal distance between either the top or bottom edge of the active area and the axis of the first track.
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-htrack-distance-1.png -
-H-Track distance
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-BoundingBox & Overall Variables

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  • self.xpitches : the number of vertical track pitches needed to fully enclose the active area.
    • -
  • self.ypitches : the number of horizontal track pitches needed to fully enclose the active area.
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-stack-layout-3.png -
-General Stack Layout
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-Wiring Specifications

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Stack routing is done through vertical metal1 wires coming from the gates and diffusions areas and metal2 horizontal wires that can be either above or below the active area. metal2 wires (or track) goes through the whole stack and are assigned to one net only. A net will have at least one track above or below and may have both.

-

The connections to the diffusions areas and gates of the various fingers are specified through a list. The stack is made of a regular alternation of diffusions and gates. The list tells, for each one starting from the left, to which net and track they are connected. For a stack of $NFs$ transistor fingers, the must wiring specification must contains $ 3 + (NFs-1) \times 2$ elements. The list is given through one string with each elements separated by one or more whitespace. The syntax for one element is detailed Atomic Wiring Specification.

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Track numbering scheme

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Tracks above (top) the active area and below (bottom) each have their own numbering. In both case, the count start from the active area. This, the top tracks will be numbered by increasing Y and the bottom tracks by decreasing Y.

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Track/Net assignement

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The track/net assignement is deduced from the atomic wiring specifications. It also allows to compute the total number of tracks needed above and below the active area.

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-wiring-spec-2.png -
-Wiring Specification
-

-Atomic Wiring Specification

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An atomic wiring specification has the same syntax for either diffusions or gates. It must not comprise any whitespaces. it is made of the following parts:

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    • -
  • Whether the track is above the active area ("t") or below ("b"). The special case ("z") means that this element must be left unconnected (is such case possible?).
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-wiring-spec-1.png -
-Atomic Wiring Specification
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-Stack Implementation Details

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The __setattr__() and __getattr__ functions have been redefined so that the technological values (rules) can be accessed has normal attributes of the Stack class, in addition to the regular ones.

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Constructor & Destructor Documentation

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def __init__ ( self,
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)
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[API] Constructor

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param rules The physical rule set.

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Parameters
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deviceThe Hurricane AMS device into which the layout will be drawn.
NERCNumber of contact rows in external (first & last) diffusion connectors.
NIRCNumber of contact rows in middle diffusion connectors. param w The width of every transistor of the stack (aka fingers). param L The length of every transistor. param NFs The total number of fingers (dummies includeds). param NDs The number of dummies to put on each side of the stack.
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References Stack.bImplantLayer, Stack.botTracks, Stack.botWTracks, Stack.bulkNet, Stack.bulks, Stack.device, Stack.dimensioned, Bulk.flags, Stack.flags, Stack.isNmos(), Stack.L, Stack.metaTnb(), Stack.metaTransistors, Stack.NDs, Stack.NERC, Stack.NFs, Stack.NIRC, Stack.tImplantLayer, Stack.topTracks, Stack.topWTracks, Stack.w, Stack.wellLayer, and Stack.wirings.

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Member Function Documentation

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def setWirings ( self,
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)
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[API] Set the Stack wiring specification.

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Parameters
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wiringSpecA string defining the connections for the gates and diffusion areas.
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For a comprehensive explanation of the wiring specification, refers to Wiring Specifications .

- -

References Stack.botTracks, Stack.botTracksNb(), Stack.botWTracks, Stack.bulkNet, Stack.computeDimensions(), Stack.device, Stack.dimensioned, Stack.eDiffMetal1Width, Bulk.flags, Stack.flags, Stack.gatePitch, Stack.getBotTrackY(), Stack.getHorizontalWidth(), Stack.horPitch, Stack.L, Stack.metal1ToGate, Stack.metaTransistors, Stack.sideActiveWidth, Stack.topTracks, Stack.topTracksNb(), Stack.topWTracks, Stack.wirings, and Stack.ypitches.

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def computeDimensions ( self)
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[internal] Compute Stack dimensions from the technological rules.

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Internal function. Perform the computation of:

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  • self.minWidth_metal1
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  • self.sideActiveWidth
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  • self.ypitches
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References Stack.activeBox, Stack.activeOffsetX, Stack.activeOffsetY, Stack.bbHeight, Stack.bbWidth, Stack.botWTracks, Stack.boundingBox, Stack.bulks, Stack.bulkWidth, Stack.computeLayoutParasitics(), Stack.computeStressEffect(), Stack.contactDiffPitch, Stack.contactDiffSide, Stack.DGG, Stack.DGI, Stack.dimensioned, Stack.DMCG, Stack.DMCGT, Stack.DMCI, Stack.eDiffMetal1Width, Bulk.flags, Stack.flags, Stack.gatePitch, Stack.gateVia1Pitch, Stack.getBotTrackY(), Stack.getHorizontalWidth(), Stack.getLastTopTrackY(), Stack.horPitch, Stack.hTrackDistance, Stack.iDiffMetal1Width, Stack.isVH, Stack.L, Stack.metal1ToGate, Stack.metal2Pitch, Stack.metal2TechnoPitch, Stack.metal3Pitch, Stack.NERC, Stack.NFs, Stack.NIRC, Stack.sideActiveWidth, Stack.tracksNbPitch(), Stack.vBulkDistance, Stack.verPitch, Stack.w, Stack.wire1Width, Stack.wire2Width, Stack.wire3Width, Stack.wirings, Stack.xpitches, and Stack.ypitches.

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Referenced by CapacitorUnit.create(), Stack.doLayout(), RoutMatchedCapacitor.route(), and Stack.setWirings().

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def doLayout ( self,
 bbMode 
)
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[API] Draw the complete layout.

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Draw the commplete layout of the Stack.

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References Stack.activeOffsetX, Stack.activeOffsetY, Stack.bbWidth, Stack.botTracks, Stack.botWTracks, Stack.boundingBox, Stack.bulkNet, Stack.bulks, Stack.bulkWidth, Stack.computeDimensions(), Stack.contactDiffPitch, Stack.device, Stack.DGG, Stack.DGI, Stack.DMCG, Stack.DMCGT, Stack.DMCI, Stack.drawActive(), Stack.drawGate(), Stack.drawSourceDrain(), Stack.drawWell(), Stack.eDiffMetal1Width, Bulk.flags, Stack.flags, Stack.gatePitch, Stack.gateVia1Pitch, Stack.getBotTrackY(), Stack.getHorizontalAxis(), Stack.getHorizontalWidth(), Stack.getTopTrackY(), Stack.getWiringWidth(), Stack.horPitch, Stack.iDiffMetal1Width, Stack.isBotTrack(), Stack.isVH, Stack.L, Stack.metal1ToGate, Stack.NERC, Stack.NFs, Stack.NIRC, Stack.sideActiveWidth, Stack.tImplantLayer, Stack.topTracks, Stack.topWTracks, Stack.w, Stack.wellLayer, Stack.wire1Width, Stack.wire2Width, Stack.wire3Width, and Stack.wirings.

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Oroshi - Analog Devices LayoutsCopyright © 2018-2018 UPMC. All rights reserved
- - diff --git a/oroshi/doc/latex/classpython_1_1CapacitorMatrix_1_1CapacitorStack.tex b/oroshi/doc/latex/classpython_1_1CapacitorMatrix_1_1CapacitorStack.tex deleted file mode 100644 index 183e505c..00000000 --- a/oroshi/doc/latex/classpython_1_1CapacitorMatrix_1_1CapacitorStack.tex +++ /dev/null @@ -1,338 +0,0 @@ -\hypertarget{classpython_1_1CapacitorMatrix_1_1CapacitorStack}{\section{Capacitor\-Stack Class Reference} -\label{classpython_1_1CapacitorMatrix_1_1CapacitorStack}\index{Capacitor\-Stack@{Capacitor\-Stack}} -} - - -Draws the layout of a compact capacitor or a matrix of adjacent identical capacitors. - - - - -Inherits Capacitor\-Unit. - -\subsection*{Public Member Functions} -\begin{DoxyCompactItemize} -\item -def \hyperlink{classpython_1_1CapacitorMatrix_1_1CapacitorStack_ac775ee34451fdfa742b318538164070e}{\-\_\-\-\_\-init\-\_\-\-\_\-} -\begin{DoxyCompactList}\small\item\em This is the class constructor. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a4b59d20a15f0e548ed19c24814efbeb6}{\-\_\-\-\_\-is\-Unit\-Cap\-\_\-\-\_\-} -\item -def \hyperlink{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a8dbb6274d6cdbb570bdea61d09e54e73}{\-\_\-\-\_\-is\-Matching\-Scheme\-O\-K\-\_\-\-\_\-} -\item -def \hyperlink{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a8540eb76875171b18a3ae9e5e5f56fd3}{capacitor\-Id\-Occurence} -\item -def \hyperlink{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a5b7ef0221e471e99fa7f0a87a28ba1ea}{create} -\begin{DoxyCompactList}\small\item\em Draw the compact or matrix of capacitors. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a0357fcbd57878fb26a1b994b13bb0cf7}{capacitor\-Line} -\begin{DoxyCompactList}\small\item\em Iteratively draws a horizontal or vertical line of capacitors according to the {\ttfamily direction} parameter. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorMatrix_1_1CapacitorStack_acd1475de157c5375cd58ccf98f825055}{capacitor\-Matrix} -\begin{DoxyCompactList}\small\item\em Draws a matrix of identical capacitors. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorMatrix_1_1CapacitorStack_ac5cd73be473bc321a29a75311f808835}{draw\-Abutment\-Box} -\begin{DoxyCompactList}\small\item\em Draws the abutment box of the matrix or campact capacitor. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorMatrix_1_1CapacitorStack_ac815a7351301379178cd6352e6ee46cd}{draw\-Bottom\-Plates\-R\-Layers} -\begin{DoxyCompactList}\small\item\em Draws the routing layers connecting the bottom plate in the matrix of capacitors. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorMatrix_1_1CapacitorStack_ac4efd1ea3fef3eaa9a07798c9157ea11}{draw\-Top\-Plates\-R\-Layers} -\begin{DoxyCompactList}\small\item\em Draws the routing layers connecting the top plates in the matrix of capacitors. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a54ac11219d9fce4c7336f4a50e69959a}{get\-Vertical\-Routing\-Track\-\_\-width} -\item -def \hyperlink{classpython_1_1CapacitorMatrix_1_1CapacitorStack_af5105be38ca05d15559b998f1da475df}{get\-Matrix\-Dim} -\item -def \hyperlink{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a73209c91d8a68eb52e957dee22e05a55}{get\-Matching\-Scheme} -\end{DoxyCompactItemize} - - -\subsection{Detailed Description} -Draws the layout of a compact capacitor or a matrix of adjacent identical capacitors. - -The matrix can be composed of one type of capacitors, either Poly-\/\-Poly or Metal-\/\-Metal in 350 nm A\-M\-S C\-M\-O\-S technology. When matching mode is off, every adjacent plates of any consecutive elementary capacitors are connected to each other using vertical routing layers. Otherwise, when matching mode is on, any of elementary capacitors can belong to, $ C_1 $ or $ C_2 $ according to the entered matching scheme. Thus, routing is not done in this class. In both modes, the complete routing process is done using the {\ttfamily Rout\-Capacitor} class. - -\subsection{Constructor \& Destructor Documentation} -\hypertarget{classpython_1_1CapacitorMatrix_1_1CapacitorStack_ac775ee34451fdfa742b318538164070e}{\index{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}!\-\_\-\-\_\-init\-\_\-\-\_\-@{\-\_\-\-\_\-init\-\_\-\-\_\-}} -\index{\-\_\-\-\_\-init\-\_\-\-\_\-@{\-\_\-\-\_\-init\-\_\-\-\_\-}!python::CapacitorMatrix::CapacitorStack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}} -\subsubsection[{\-\_\-\-\_\-init\-\_\-\-\_\-}]{\setlength{\rightskip}{0pt plus 5cm}def \-\_\-\-\_\-init\-\_\-\-\_\- ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{device, } -\item[{}]{capacitance, } -\item[{}]{capacitor\-Type, } -\item[{}]{abutment\-Box\-Position, } -\item[{}]{nets, } -\item[{}]{unit\-Cap = {\ttfamily 0}, } -\item[{}]{matrix\-Dim = {\ttfamily \mbox{[}1}, } -\item[{}]{matching\-Mode = {\ttfamily False}, } -\item[{}]{matching\-Scheme = {\ttfamily \mbox{[}\mbox{]}}, } -\item[{}]{dummy\-Ring = {\ttfamily False}, } -\item[{}]{dummy\-Element = {\ttfamily False}} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorMatrix_1_1CapacitorStack_ac775ee34451fdfa742b318538164070e} - - -This is the class constructor. - -Basically, the class there are three categories of attributes. There are the ones related to the capacitor caracteristics, its type, dimensions. Also, there are attributes to parametrize the class into matching mode or not and there are other attributes realted to the layout varibales. The class has defaut input values, thus, in this constructor, there are two \char`\"{}sub-\/constructors\char`\"{} according to the entered input parameters. The class attributes are \-: - - -\begin{DoxyParams}{Parameters} -{\em device} & The {\bf Hurricane} A\-M\-S device into which the layout is drawn. \\ -\hline -{\em capacitance} & The value of the capacitor, expressed in femto Farad (f\-F). \\ -\hline -{\em capacitor\-Type} & Can be M\-I\-M or P\-I\-P type capacitor. \\ -\hline -{\em abutment\-Position} & Refers to the abscissa (X\-Min) of the bottom left corner of the abutment Box. \\ -\hline -{\em abutment\-Box\-Y\-Min} & Refers to the ordinate (Y\-Min) of the bottom left corner of the abutment Box.\\ -\hline -\end{DoxyParams} -Except the two last arguments, all the parameters are common with the Capacitor\-Unit class because the {\ttfamily \hyperlink{classpython_1_1CapacitorMatrix_1_1CapacitorStack}{Capacitor\-Stack}} constructor calls the mother class constructor to create either a compact capacitor of {\ttfamily capacitance} value or {\ttfamily row\-Number$\ast$} {\ttfamily column\-Number} unity capacitors. - - -\begin{DoxyParams}{Parameters} -{\em row\-Number} & Number of rows in the matrix of capacitors. \\ -\hline -{\em column\-Number} & Number of columns in the matrix of capacitors. \\ -\hline -\end{DoxyParams} - - -References Capacitor\-Stack.\-\_\-\-\_\-are\-Input\-Data\-O\-K\-\_\-\-\_\-(), Capacitor\-Unit.\-\_\-\-\_\-compute\-Cap\-Dim\-\_\-\-\_\-(), Capacitor\-Stack.\-\_\-\-\_\-init\-Given\-Non\-Zero\-Unit\-Cap\-\_\-\-\_\-(), Capacitor\-Stack.\-\_\-\-\_\-init\-Given\-Non\-Zero\-Unit\-Cap\-In\-Matching\-Mode\-\_\-\-\_\-(), Capacitor\-Stack.\-\_\-\-\_\-init\-Given\-Zero\-Unit\-Cap\-\_\-\-\_\-(), Capacitor\-Stack.\-\_\-\-\_\-init\-Given\-Zero\-Unit\-Cap\-In\-Matching\-Mode\-\_\-\-\_\-(), Capacitor\-Stack.\-\_\-\-\_\-init\-Matrix\-Mode\-\_\-\-\_\-(), Capacitor\-Unit.\-\_\-\-\_\-is\-Capacitor\-Unit\-O\-K\-\_\-\-\_\-(), Capacitor\-Stack.\-abutment\-Box, Capacitor\-Unit.\-abutment\-Box, Capacitor\-Stack.\-abutment\-Box\-\_\-spacing, Capacitor\-Stack.\-abutment\-Box\-Position, Capacitor\-Stack.\-capacitance, Capacitor\-Stack.\-capacitor\-Id\-Occurence(), Capacitor\-Stack.\-capacitors\-Number, Capacitor\-Stack.\-capacitor\-Type, Capacitor\-Unit.\-capacitor\-Type, Capacitor\-Stack.\-compact\-Cap\-Dim, Capacitor\-Stack.\-compute\-Unit\-Cap(), Capacitor\-Stack.\-device, Capacitor\-Unit.\-device, Stack.\-device, Capacitor\-Stack.\-do\-Matrix, Capacitor\-Stack.\-dummy\-Element, Capacitor\-Stack.\-dummy\-Ring, Capacitor\-Stack.\-dummy\-Ring\-Position, Capacitor\-Stack.\-evaluate\-Unit\-Cap(), Capacitor\-Stack.\-matching\-Mode, Capacitor\-Stack.\-matching\-Scheme, Capacitor\-Stack.\-matrix\-Dim, Capacitor\-Stack.\-min\-Enclosure\-\_\-h\-Routing\-Layer\-\_\-top\-Plate\-\_\-cut, Capacitor\-Stack.\-min\-Enclosure\-\_\-v\-Routing\-Track\-Cut, Capacitor\-Stack.\-min\-Spacing\-\_\-v\-Routing\-Track, Capacitor\-Stack.\-min\-Spacing\-\_\-v\-Routing\-Track\-Cut, Capacitor\-Stack.\-min\-Width\-\_\-h\-Routing\-Layer\-\_\-top\-Plate\-\_\-cut, Capacitor\-Stack.\-min\-Width\-\_\-v\-Routing\-Track, Capacitor\-Stack.\-min\-Width\-\_\-v\-Routing\-Track\-Cut, Capacitor\-Stack.\-nets, Capacitor\-Stack.\-unit\-Capacitance, Capacitor\-Stack.\-unit\-Cap\-Dim, and Capacitor\-Stack.\-v\-Routing\-Track\-\_\-width. - - - -\subsection{Member Function Documentation} -\hypertarget{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a4b59d20a15f0e548ed19c24814efbeb6}{\index{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}!\-\_\-\-\_\-is\-Unit\-Cap\-\_\-\-\_\-@{\-\_\-\-\_\-is\-Unit\-Cap\-\_\-\-\_\-}} -\index{\-\_\-\-\_\-is\-Unit\-Cap\-\_\-\-\_\-@{\-\_\-\-\_\-is\-Unit\-Cap\-\_\-\-\_\-}!python::CapacitorMatrix::CapacitorStack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}} -\subsubsection[{\-\_\-\-\_\-is\-Unit\-Cap\-\_\-\-\_\-}]{\setlength{\rightskip}{0pt plus 5cm}def \-\_\-\-\_\-is\-Unit\-Cap\-\_\-\-\_\- ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a4b59d20a15f0e548ed19c24814efbeb6} -\begin{DoxyReturn}{Returns} -True if the drawn capacitor is a compact one. This function is useful when an instance is called in another class. {\bfseries Example} \-: when the matrix or the compact capacitors are to be fully routed. -\end{DoxyReturn} -\hypertarget{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a8dbb6274d6cdbb570bdea61d09e54e73}{\index{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}!\-\_\-\-\_\-is\-Matching\-Scheme\-O\-K\-\_\-\-\_\-@{\-\_\-\-\_\-is\-Matching\-Scheme\-O\-K\-\_\-\-\_\-}} -\index{\-\_\-\-\_\-is\-Matching\-Scheme\-O\-K\-\_\-\-\_\-@{\-\_\-\-\_\-is\-Matching\-Scheme\-O\-K\-\_\-\-\_\-}!python::CapacitorMatrix::CapacitorStack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}} -\subsubsection[{\-\_\-\-\_\-is\-Matching\-Scheme\-O\-K\-\_\-\-\_\-}]{\setlength{\rightskip}{0pt plus 5cm}def \-\_\-\-\_\-is\-Matching\-Scheme\-O\-K\-\_\-\-\_\- ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a8dbb6274d6cdbb570bdea61d09e54e73} -\begin{DoxyReturn}{Returns} -{\ttfamily True} if the matching scheme specifications are correct. Specifications are \-: -\begin{DoxyItemize} -\item Similar number of elements as total number of elementary capacitor in the matrix. -\item Equal number of affected capacitors to C1 as to C2. -\item Capacitor identifiers equal to '1' or '2' only. -\item Otherwise, the function returns {\ttfamily False}. -\end{DoxyItemize} -\end{DoxyReturn} - - -References Capacitor\-Stack.\-matching\-Scheme, and Capacitor\-Stack.\-matrix\-Dim. - - - -Referenced by Capacitor\-Stack.\-capacitor\-Id\-Occurence(). - -\hypertarget{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a8540eb76875171b18a3ae9e5e5f56fd3}{\index{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}!capacitor\-Id\-Occurence@{capacitor\-Id\-Occurence}} -\index{capacitor\-Id\-Occurence@{capacitor\-Id\-Occurence}!python::CapacitorMatrix::CapacitorStack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}} -\subsubsection[{capacitor\-Id\-Occurence}]{\setlength{\rightskip}{0pt plus 5cm}def capacitor\-Id\-Occurence ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{capacitor\-Identifier} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a8540eb76875171b18a3ae9e5e5f56fd3} -\begin{DoxyReturn}{Returns} -occurence of capacitor identifier in the entered matching scheme. This is useful to verify that {\ttfamily self.\-matching\-Scheme} is correct. -\end{DoxyReturn} - - -References Capacitor\-Stack.\-\_\-\-\_\-are\-Matrix\-Dim\-O\-K\-\_\-\-\_\-(), Capacitor\-Stack.\-\_\-\-\_\-is\-Matching\-Scheme\-O\-K\-\_\-\-\_\-(), Capacitor\-Stack.\-capacitors\-Number, Capacitor\-Stack.\-dummy\-Element, Capacitor\-Stack.\-dummy\-Ring, Capacitor\-Stack.\-matching\-Mode, Capacitor\-Stack.\-matching\-Scheme, and Capacitor\-Stack.\-nets. - - - -Referenced by Capacitor\-Stack.\-\_\-\-\_\-init\-\_\-\-\_\-(). - -\hypertarget{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a5b7ef0221e471e99fa7f0a87a28ba1ea}{\index{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}!create@{create}} -\index{create@{create}!python::CapacitorMatrix::CapacitorStack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}} -\subsubsection[{create}]{\setlength{\rightskip}{0pt plus 5cm}def create ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{bb\-Mode = {\ttfamily False}} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a5b7ef0221e471e99fa7f0a87a28ba1ea} - - -Draw the compact or matrix of capacitors. - -First, . Second, . Finally, . - -References Capacitor\-Stack.\-\_\-\-\_\-init\-Matching\-Mode\-\_\-\-\_\-(), Capacitor\-Stack.\-abutment\-Box\-\_\-spacing, Capacitor\-Stack.\-abutment\-Box\-Position, Capacitor\-Stack.\-capacitance, Capacitor\-Stack.\-capacitor\-Matrix(), Capacitor\-Stack.\-capacitor\-Type, Capacitor\-Unit.\-capacitor\-Type, Capacitor\-Stack.\-compute\-Bonding\-Box\-Dimensions(), Capacitor\-Stack.\-device, Capacitor\-Unit.\-device, Stack.\-device, Capacitor\-Stack.\-do\-Matrix, Capacitor\-Stack.\-draw\-Abutment\-Box(), Capacitor\-Unit.\-draw\-Abutment\-Box(), Capacitor\-Stack.\-draw\-Bottom\-Plates\-R\-Layers(), Capacitor\-Stack.\-draw\-Capacitor\-Stack(), Capacitor\-Stack.\-draw\-Top\-Plates\-R\-Layers(), Capacitor\-Stack.\-dummy\-Ring, Capacitor\-Stack.\-matching\-Mode, Capacitor\-Stack.\-matrix\-Dim, Capacitor\-Stack.\-nets, Capacitor\-Stack.\-set\-Rules(), and Capacitor\-Unit.\-set\-Rules(). - - - -Referenced by Capacitor\-Stack.\-capacitor\-Line(), and Capacitor\-Stack.\-capacitor\-Matrix(). - -\hypertarget{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a0357fcbd57878fb26a1b994b13bb0cf7}{\index{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}!capacitor\-Line@{capacitor\-Line}} -\index{capacitor\-Line@{capacitor\-Line}!python::CapacitorMatrix::CapacitorStack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}} -\subsubsection[{capacitor\-Line}]{\setlength{\rightskip}{0pt plus 5cm}def capacitor\-Line ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{dy, } -\item[{}]{abutment\-Box\-\_\-spacing, } -\item[{}]{matching\-Scheme\-Row\-Index = {\ttfamily 0}} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a0357fcbd57878fb26a1b994b13bb0cf7} - - -Iteratively draws a horizontal or vertical line of capacitors according to the {\ttfamily direction} parameter. - -An exception is raised if the specified direction is different from {\ttfamily \{'horizontal'},'vertical'\}. At every iteration, an instance of the Capacitor\-Unit class is created and its layout is drawn. \begin{DoxyReturn}{Returns} -a list containing the drawn capacitors. -\end{DoxyReturn} - -\begin{DoxyParams}{Parameters} -{\em dy} & the vertical position of the first cut in cut line. \\ -\hline -\end{DoxyParams} -\begin{DoxyRemark}{Remarks} -An exception is raised if the specified direction is different from {\ttfamily \{'horizontal'},'vertical'\} -\end{DoxyRemark} - - -References Capacitor\-Stack.\-abutment\-Box\-Position, Capacitor\-Stack.\-capacitor\-Type, Capacitor\-Unit.\-capacitor\-Type, Capacitor\-Stack.\-create(), Capacitor\-Stack.\-create\-Element\-In\-Capacitor\-Line(), Capacitor\-Stack.\-device, Capacitor\-Unit.\-device, Stack.\-device, Capacitor\-Stack.\-dummy\-Ring, Capacitor\-Stack.\-matching\-Mode, Capacitor\-Stack.\-matching\-Scheme, Capacitor\-Stack.\-matrix\-Dim, Capacitor\-Stack.\-nets, and Capacitor\-Stack.\-unit\-Capacitance. - - - -Referenced by Capacitor\-Stack.\-capacitor\-Matrix(). - -\hypertarget{classpython_1_1CapacitorMatrix_1_1CapacitorStack_acd1475de157c5375cd58ccf98f825055}{\index{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}!capacitor\-Matrix@{capacitor\-Matrix}} -\index{capacitor\-Matrix@{capacitor\-Matrix}!python::CapacitorMatrix::CapacitorStack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}} -\subsubsection[{capacitor\-Matrix}]{\setlength{\rightskip}{0pt plus 5cm}def capacitor\-Matrix ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{abutment\-Box\-\_\-spacing = {\ttfamily 0}} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorMatrix_1_1CapacitorStack_acd1475de157c5375cd58ccf98f825055} - - -Draws a matrix of identical capacitors. - -The matrix is iterativelly constructed. At every iteration, a new horizontal line of capacitors is drawn. \begin{DoxyReturn}{Returns} -a nested list of elementary capacitors. -\end{DoxyReturn} - - -References Capacitor\-Stack.\-abutment\-Box\-\_\-spacing, Capacitor\-Stack.\-abutment\-Box\-Position, Capacitor\-Stack.\-capacitor\-Line(), Capacitor\-Stack.\-capacitor\-Type, Capacitor\-Unit.\-capacitor\-Type, Capacitor\-Stack.\-create(), Capacitor\-Stack.\-device, Capacitor\-Unit.\-device, Stack.\-device, Capacitor\-Stack.\-dummy\-Ring, Capacitor\-Stack.\-get\-Cap\-Dim(), Capacitor\-Stack.\-matrix\-Dim, Capacitor\-Stack.\-nets, and Capacitor\-Stack.\-unit\-Capacitance. - - - -Referenced by Capacitor\-Stack.\-create(). - -\hypertarget{classpython_1_1CapacitorMatrix_1_1CapacitorStack_ac5cd73be473bc321a29a75311f808835}{\index{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}!draw\-Abutment\-Box@{draw\-Abutment\-Box}} -\index{draw\-Abutment\-Box@{draw\-Abutment\-Box}!python::CapacitorMatrix::CapacitorStack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}} -\subsubsection[{draw\-Abutment\-Box}]{\setlength{\rightskip}{0pt plus 5cm}def draw\-Abutment\-Box ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{abutment\-Box\-\_\-spacing = {\ttfamily 0}} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorMatrix_1_1CapacitorStack_ac5cd73be473bc321a29a75311f808835} - - -Draws the abutment box of the matrix or campact capacitor. - - - -References Capacitor\-Stack.\-abutment\-Box, Capacitor\-Unit.\-abutment\-Box, Capacitor\-Stack.\-abutment\-Box\-\_\-spacing, Capacitor\-Stack.\-abutment\-Box\-Position, Capacitor\-Stack.\-compute\-Abutment\-Box\-Dimensions(), and Capacitor\-Unit.\-compute\-Abutment\-Box\-Dimensions(). - - - -Referenced by Capacitor\-Stack.\-create(). - -\hypertarget{classpython_1_1CapacitorMatrix_1_1CapacitorStack_ac815a7351301379178cd6352e6ee46cd}{\index{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}!draw\-Bottom\-Plates\-R\-Layers@{draw\-Bottom\-Plates\-R\-Layers}} -\index{draw\-Bottom\-Plates\-R\-Layers@{draw\-Bottom\-Plates\-R\-Layers}!python::CapacitorMatrix::CapacitorStack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}} -\subsubsection[{draw\-Bottom\-Plates\-R\-Layers}]{\setlength{\rightskip}{0pt plus 5cm}def draw\-Bottom\-Plates\-R\-Layers ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{bottom\-Plate\-R\-Layer, } -\item[{}]{drawn\-Capacitor} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorMatrix_1_1CapacitorStack_ac815a7351301379178cd6352e6ee46cd} - - -Draws the routing layers connecting the bottom plate in the matrix of capacitors. - -First, the relative positions of the routing layer is of the is extracted from the elementary capacitor instance. Then, its width is computed in a way to connect adjacent plates. Then, the routing layers are iterativelly drawn. The two borders are . - -References Capacitor\-Stack.\-matrix\-Dim, and Capacitor\-Stack.\-nets. - - - -Referenced by Capacitor\-Stack.\-create(). - -\hypertarget{classpython_1_1CapacitorMatrix_1_1CapacitorStack_ac4efd1ea3fef3eaa9a07798c9157ea11}{\index{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}!draw\-Top\-Plates\-R\-Layers@{draw\-Top\-Plates\-R\-Layers}} -\index{draw\-Top\-Plates\-R\-Layers@{draw\-Top\-Plates\-R\-Layers}!python::CapacitorMatrix::CapacitorStack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}} -\subsubsection[{draw\-Top\-Plates\-R\-Layers}]{\setlength{\rightskip}{0pt plus 5cm}def draw\-Top\-Plates\-R\-Layers ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{top\-Plate\-R\-Layer, } -\item[{}]{drawn\-Capacitor} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorMatrix_1_1CapacitorStack_ac4efd1ea3fef3eaa9a07798c9157ea11} - - -Draws the routing layers connecting the top plates in the matrix of capacitors. - -First, the relative positions of the routing layers is of the is extracted from the elementary capacitor instance. Then, its width is computed in a way to connect adjacent plates. Then, the routing layers are iterativelly drawn. The two borders are . \begin{DoxyRemark}{Remarks} -An exception is raised if the number of rows in the matrix is lower than 2. -\end{DoxyRemark} - - -References Capacitor\-Stack.\-matrix\-Dim, and Capacitor\-Stack.\-nets. - - - -Referenced by Capacitor\-Stack.\-create(). - -\hypertarget{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a54ac11219d9fce4c7336f4a50e69959a}{\index{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}!get\-Vertical\-Routing\-Track\-\_\-width@{get\-Vertical\-Routing\-Track\-\_\-width}} -\index{get\-Vertical\-Routing\-Track\-\_\-width@{get\-Vertical\-Routing\-Track\-\_\-width}!python::CapacitorMatrix::CapacitorStack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}} -\subsubsection[{get\-Vertical\-Routing\-Track\-\_\-width}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Vertical\-Routing\-Track\-\_\-width ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a54ac11219d9fce4c7336f4a50e69959a} -\begin{DoxyReturn}{Returns} -The width of the vertical routing tracks in matching mode. -\end{DoxyReturn} -\begin{DoxyParagraph}{Remark\-:} -This function is useful in matching mode, ie., in Rout\-Capacitor class, when routing the two capacitors. -\end{DoxyParagraph} -\hypertarget{classpython_1_1CapacitorMatrix_1_1CapacitorStack_af5105be38ca05d15559b998f1da475df}{\index{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}!get\-Matrix\-Dim@{get\-Matrix\-Dim}} -\index{get\-Matrix\-Dim@{get\-Matrix\-Dim}!python::CapacitorMatrix::CapacitorStack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}} -\subsubsection[{get\-Matrix\-Dim}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Matrix\-Dim ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorMatrix_1_1CapacitorStack_af5105be38ca05d15559b998f1da475df} -\begin{DoxyReturn}{Returns} -A dictionary contaning capacitor matrix's dimensions -\end{DoxyReturn} - - -References Capacitor\-Stack.\-compact\-Cap\-Dim, and Capacitor\-Stack.\-do\-Matrix. - -\hypertarget{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a73209c91d8a68eb52e957dee22e05a55}{\index{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}!get\-Matching\-Scheme@{get\-Matching\-Scheme}} -\index{get\-Matching\-Scheme@{get\-Matching\-Scheme}!python::CapacitorMatrix::CapacitorStack@{python\-::\-Capacitor\-Matrix\-::\-Capacitor\-Stack}} -\subsubsection[{get\-Matching\-Scheme}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Matching\-Scheme ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorMatrix_1_1CapacitorStack_a73209c91d8a68eb52e957dee22e05a55} -\begin{DoxyReturn}{Returns} -the matching scheme. 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-\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor}\index{Rout\-Matched\-Capacitor@{Rout\-Matched\-Capacitor}} -} - - -Routs two matched capacitors, C1 and C2, drawn in a capacitor matrix. - - - - -Inherits Capacitor\-Unit, Capacitor\-Stack, and Vertical\-Routing\-Tracks. - -\subsection*{Public Member Functions} -\begin{DoxyCompactItemize} -\item -def \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_ac775ee34451fdfa742b318538164070e}{\-\_\-\-\_\-init\-\_\-\-\_\-} -\begin{DoxyCompactList}\small\item\em A special method used to customize the class instance to an initial state in which \-: \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a15ec3e3156133327b307cd0e4b75f22c}{route} -\begin{DoxyCompactList}\small\item\em Draws the complete layout given the capacitor matrix. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a3b578035b1559391931dade7c2508105}{set\-Rules} -\begin{DoxyCompactList}\small\item\em Defines technology rules used to draw the layout. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_ae361a87f8ad999bb5f1b9851773f481b}{set\-Layers} -\begin{DoxyCompactList}\small\item\em Defines all physical layers used to draw the layout. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a20b46b43488cc58c302b123a89299d85}{compute\-Dimensions} -\begin{DoxyCompactList}\small\item\em Computes, through simple instructions and functions calls, layout variables detailed in Figure 2. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_ab00cae047369eb93c10e44e316fa991b}{compute\-H\-Routing\-Track\-Y\-Center} -\begin{DoxyCompactList}\small\item\em Computes centers' ordinates of the eight horizontal routing tracks. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a0d90b75abe0f4ce0f0b9b1b405462300}{compute\-H\-R\-Layer\-Y\-Center} -\begin{DoxyCompactList}\small\item\em Sets the stretching value of top plates. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_afbe39494b52b035fe3efdb0ddb896f69}{draw\-H\-Routing\-Tracks} -\begin{DoxyCompactList}\small\item\em Iteratively draws horizontal routing tracks on top and bottom positions of the matrix using physical layer {\ttfamily routing\-Tracks\-Layer}. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a6bba48a4b1d4834c6617a5af5553be1c}{draw\-H\-R\-Layers} -\begin{DoxyCompactList}\small\item\em Iteratively draws the horizontal routing layers starting with bottom left elementary capacitor $ C_{00} $. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a2019f4bb1e22a8d622ce4d155c934eb0}{draw\-Cuts} -\begin{DoxyCompactList}\small\item\em Draws all required cuts using physical layers \-: \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_ab3fd42d04811b9c88654c0ca0e6e2de7}{draw\-One\-Cut\-\_\-v\-Routing\-Track\-\_\-\-H\-R\-Layer} -\begin{DoxyCompactList}\small\item\em Draws one cut, in layer {\ttfamily cut\-Layer}, in order to connect a vertical routing track, at position {\ttfamily cut\-X\-Min} in metal 2, and a horizontal routing track, at position {\ttfamily cut\-Y\-Min} in metal 3. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a05e49f5537d31e0ab19b8a86eb6e7b1c}{draw\-Cuts\-\_\-v\-Routing\-Track\-\_\-h\-Routing\-Track} -\begin{DoxyCompactList}\small\item\em Draws cuts to connect vertical routing tracks in metal 2 and horizontal routing tracks in metal 3. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a7d642764cf9e385710751eec3f43f7af}{\-\_\-\-\_\-stretch\-Top\-Plates\-\_\-\-\_\-} -\begin{DoxyCompactList}\small\item\em Iteratively performs top plates stretching for the capacitor matrix. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a57eade928345587b01420a05be475a8f}{\-\_\-\-\_\-stretch\-Top\-Plate\-Compact\-Cap\-\_\-\-\_\-} -\begin{DoxyCompactList}\small\item\em Draws vertical stretched layers for a given elementary capacitor. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a1077752f46c512f70377cc60bd772034}{\-\_\-\-\_\-set\-Stretching\-Dy\-Source\-Dy\-Target\-\_\-\-\_\-} -\begin{DoxyCompactList}\small\item\em Sets the abcissas of the extremities of the vertical stretching to be applied to capacitor's top plates for a given elementary capacitor in the matrix. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_aaaf2e610688441a439b8a3624e1393b9}{\-\_\-\-\_\-compute\-Connections\-\_\-\-\_\-} -\begin{DoxyCompactList}\small\item\em Computes horizontal routing layers source and target abcissas for top and bottom plates connections to its associated routing track. \end{DoxyCompactList}\end{DoxyCompactItemize} - - -\subsection{Detailed Description} -Routs two matched capacitors, C1 and C2, drawn in a capacitor matrix. - -Connections are put in place with reference to a given matching scheme. Elementary capacitor units are connected to horizontal and vertical routing tracks that represent top plates and bottom plates nets of C1 and C2 . Supported types of capacitors are Poly-\/\-Poly and Metal-\/\-Metal. Technologycal rules are provided by 350 nm A\-M\-S C\-M\-O\-S technology with three-\/four metal layers. Metal layers that are used for routing are placed similarly to horziontal-\/vertical (H\-V) symbolic Alliance C\-A\-D tool router, where horizontal metal channels are drawn in metal 2 and the vertical ones are in metal 3. Given a matrix of dimensions $ R*C $, the total number of vertical tracks is $ 2C+2 $ equivalent to $ C+1 $ couples, ensuring that every elementary capacitor is positioned between four vertical tracks, two from each side. In fact, every adjacent couple of these tracks represent top plates and bottom plates of C1 or C2 as shown in Figure 1. An elementary capacitor unit can be a part of C1 or C2 according to the matching scheme. However, to respect common-\/centroid layout specifications, for C1 and C2 to be equal, the matrix number of colums and number of rows must be both even. Addionnally, the number of elementary capacitors dedicated to C1 must be equal to those dedicated to C2. These two conditions are tested in one of the class methods. An exception is raised if at least one of the two is not respected. - -\subsection{Constructor \& Destructor Documentation} -\hypertarget{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_ac775ee34451fdfa742b318538164070e}{\index{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}!\-\_\-\-\_\-init\-\_\-\-\_\-@{\-\_\-\-\_\-init\-\_\-\-\_\-}} -\index{\-\_\-\-\_\-init\-\_\-\-\_\-@{\-\_\-\-\_\-init\-\_\-\-\_\-}!python::CapacitorRouted::RoutMatchedCapacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}} -\subsubsection[{\-\_\-\-\_\-init\-\_\-\-\_\-}]{\setlength{\rightskip}{0pt plus 5cm}def \-\_\-\-\_\-init\-\_\-\-\_\- ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{v\-R\-T\-Instance} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_ac775ee34451fdfa742b318538164070e} - - -A special method used to customize the class instance to an initial state in which \-: - - -\begin{DoxyItemize} -\item the class attirbutes describing positions and dimensions of the layout are computed in dedicated class methods, -\item the attributes related to the capacitor matrix are copied from the {\ttfamily Capacitor\-Stack} instance. -\end{DoxyItemize} - -Position and dimensions attributes, also refered by layout variables, in Figure 2, are defined below \-: -\begin{DoxyParams}{Parameters} -{\em device} & The {\bf Hurricane} A\-M\-S device onto which the layout is drawn. \\ -\hline -{\em capacitor\-Instance} & Instance of {\ttfamily Capacitor\-Stack} class. \\ -\hline -{\em capacitor} & A nested list containing the matrix elements, which are {\ttfamily Capacitor\-Unit} objects. \\ -\hline -{\em matching\-Scheme} & A nested list, with equal dimensions as {\ttfamily capacitor} attribute, containing assignements of matrix elementary units to C1 and C2, identified by 1 and 2, respectively. Therefore, {\ttfamily self.\-matching\-Scheme} content is a succession of 1 and 2 values, defined as \textbackslash{} capacitor identifiers. For example, given a matrix of dimensions 2x2, the matching scheme can be $ [ [1,2], [1,2] ] or [ [2,1], [2,1] ] $. The first sub-\/list dictates that the first elementary capacitor, $ C_{00} $. The second element $ C_{01} $ is affected to C2 and so on. An immediate and obvious consequence to this, is that an error is raised if {\ttfamily self.\-matching\-Schem} and {\ttfamily self.\-capacitor} dimensions are not identical or if {\ttfamily self.\-matching\-Scheme} content is different from supported capacitor identifiers, '1' and '2'.\\ -\hline -{\em capacitor\-Type} & Supported types of capacitors are M\-I\-M and P\-I\-P only. An exception is raised otherwise. \\ -\hline -{\em abutment\-Box} & The matrix's abutment box. \\ -\hline -{\em matrxi\-Dim} & The matrix dimensions, also equal to {\ttfamily self.\-matching\-Scheme} nested list dimensions. \\ -\hline -{\em abutment\-Box\-\_\-spacing} & The spacing between elementary units in the matrix. It is computed in {\ttfamily Capacitor\-Stack} and is reloaded in {\ttfamily \hyperlink{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor}{Rout\-Matched\-Capacitor}}. {\ttfamily self.\-abutment\-Box\-\_\-spacing} includes, vertical routing tracks width and minimum allowed spacing between two adjacent ones. \\ -\hline -{\em h\-Routing\-Layer\-\_\-width} & The width of horizontal routing layers in metal 2, which connect capacitors plates to vertical routing tracks. \\ -\hline -{\em v\-Routing\-Track\-\_\-width} & The width of vertical routing tracks in metal 3, which connects identical nets together ( ie \-: bottom plates of C1, top plates of C2, bottom plates of C2 and top plates of C2 ). \\ -\hline -{\em h\-Routing\-Track\-\_\-width} & The width of horizontal routing tracks in metal 2, which connect identical vertical routing tracks together. \\ -\hline -{\em min\-Spacing\-\_\-h\-Routing\-Track} & Minimum spacing between horizontal routing tracks. Wide metal 2 specifications are considered since metal 2 dimensions may exceed 10 $ m$.\\ -\hline -\end{DoxyParams} -\begin{DoxyParagraph}{Remark\-:} -For more information about wide metal specifications, refer to E\-N\-G-\/183\-\_\-rev8.\-pdf technology manual. -\end{DoxyParagraph} - -\begin{DoxyParams}{Parameters} -{\em minimum\-Position} & The ordinate of the top plate's routing layer's bottom extremity after stretching. \\ -\hline -{\em maximum\-Position} & The ordinate of the top plate's routing layer's top extremity, also equivalent to the top plate's top extremity. \\ -\hline -{\em v\-Routing\-Track\-X\-Center} & A nested list of ordered dictionaries, with dimensions equal to {\ttfamily self.\-matrix\-Dim}, containing abcissas of vertical routing tracks. All sub-\/lists' lengths are identical and are equal to 2. The first and second elements describe position of top plate track and bottom plate track, respectively. For example, given a matrix of dimensions 2x2, {\ttfamily self.\-v\-Routing\-Track\-X\-Center} can be \mbox{[}\mbox{[}0, 2\mbox{]}, \mbox{[}4,6\mbox{]}, \mbox{[}8,10\mbox{]}\mbox{]} $ \mu m$. Elements of this nested list have particular indexing as described in Figure 2.\\ -\hline -{\em h\-Routingtrack\-Y\-Center} & A nested dictonary containing two keys, {\ttfamily top\-Tracks} and {\ttfamily bottom\-Tracks}. Each key contains as value a dictionary describing centers' ordinates of four parallel horizontal tracks. The reason why four tracks are needed on top and bottom positions of the matrix is that four nets are used, two for every capacitor {\ttfamily Ci}, were {\ttfamily i} is in \mbox{[}1,2\mbox{]}. \\ -\hline -{\em h\-Routing\-Layer\-Y\-Center} & A nested dicitonary containing two keys, {\ttfamily top} and {\ttfamily bottom}. Each key contains as value a dictionary describing centers' ordinates of horizontal routing layers. \\ -\hline -{\em v\-Routing\-Track\-Dict} & A dictionary of routing tracks top and bottom extremities ordinates. \\ -\hline -{\em top\-Plate\-Stretching} & Since not only the same metal 2 layer is used to draw top/bottom plates connections to vertical tracks but also the two plates are superimposed, the top plate's routing tracks is stretched. {\ttfamily self.\-top\-Plate\-Stretching} is therefore the length added to top plate's routing layer in order to avoid short circuits between top and bottom plates routing to vertical tracks since the same metal is used for both. \\ -\hline -\end{DoxyParams} - - -References Rout\-Matched\-Capacitor.\-capacitor, Capacitor\-Stack.\-dummy\-Ring, Rout\-Matched\-Capacitor.\-dummy\-Ring, Rout\-Matched\-Capacitor.\-dummy\-Ring\-Capacitor, Rout\-Matched\-Capacitor.\-h\-Routing\-Layer\-\_\-width, Rout\-Matched\-Capacitor.\-h\-Routing\-Layer\-Y\-Center, Rout\-Matched\-Capacitor.\-h\-Routing\-Track\-\_\-width, Rout\-Matched\-Capacitor.\-h\-Routingtrack\-Y\-Center, Capacitor\-Stack.\-matrix\-Dim, Vertical\-Routing\-Tracks.\-matrix\-Dim, Rout\-Matched\-Capacitor.\-maximum\-Position, Rout\-Matched\-Capacitor.\-minimum\-Position, Rout\-Matched\-Capacitor.\-min\-Spacing\-\_\-h\-Routing\-Track, Rout\-Matched\-Capacitor.\-top\-Plate\-Stretching, and Rout\-Matched\-Capacitor.\-v\-R\-T\-Instance. - - - -\subsection{Member Function Documentation} -\hypertarget{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a15ec3e3156133327b307cd0e4b75f22c}{\index{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}!route@{route}} -\index{route@{route}!python::CapacitorRouted::RoutMatchedCapacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}} -\subsubsection[{route}]{\setlength{\rightskip}{0pt plus 5cm}def route ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{bb\-Mode = {\ttfamily False}} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a15ec3e3156133327b307cd0e4b75f22c} - - -Draws the complete layout given the capacitor matrix. - -{\ttfamily route} method is succession of calls to user-\/defined methods inside a newly created {\ttfamily Updatesession}. The following tasks are excecuted \-: -\begin{DoxyEnumerate} -\item A nex {\ttfamily Update\-Session} is created, -\item all required physical layers are loaded, -\item technology rules are defined according to capacitor type, -\item layout dimension parameters are computed, -\item routing tracks and layers are drawn, -\item top plates are stretched, -\item all required cuts are drawn, -\item The {\ttfamily Update\-Session} is closed. -\end{DoxyEnumerate} - -Meanwhile, an exception is raised when the entered {\ttfamily capacitor} is not a capacitor matrix or if the capacitor type is unsupported. - -References Rout\-Matched\-Capacitor.\-\_\-\-\_\-stretch\-Top\-Plates\-\_\-\-\_\-(), Rout\-Matched\-Capacitor.\-capacitor, Rout\-Matched\-Capacitor.\-compute\-Dimensions(), Capacitor\-Unit.\-compute\-Dimensions(), Stack.\-compute\-Dimensions(), Rout\-Matched\-Capacitor.\-draw\-Cuts(), Rout\-Matched\-Capacitor.\-draw\-Dummy\-Ring\-\_\-h\-R\-Tracks\-\_\-\-Cuts(), Rout\-Matched\-Capacitor.\-draw\-H\-R\-Layers(), Rout\-Matched\-Capacitor.\-draw\-H\-Routing\-Tracks(), Capacitor\-Stack.\-dummy\-Ring, Rout\-Matched\-Capacitor.\-dummy\-Ring, Rout\-Matched\-Capacitor.\-dummy\-Ring\-Capacitor, Vertical\-Routing\-Tracks.\-get\-V\-Track\-Y\-Max(), Vertical\-Routing\-Tracks.\-get\-V\-Track\-Y\-Min(), Capacitor\-Unit.\-hpitch, Rout\-Matched\-Capacitor.\-h\-Routingtrack\-Y\-Center, Vertical\-Routing\-Tracks.\-matching\-Scheme, Capacitor\-Stack.\-matching\-Scheme, Capacitor\-Stack.\-matrix\-Dim, Vertical\-Routing\-Tracks.\-matrix\-Dim, Rout\-Matched\-Capacitor.\-maximum\-Position, Capacitor\-Unit.\-metal3\-Width, Rout\-Matched\-Capacitor.\-minimum\-Position, Vertical\-Routing\-Tracks.\-nets, Capacitor\-Stack.\-nets, Rout\-Matched\-Capacitor.\-route\-Dummy\-Ring(), Rout\-Matched\-Capacitor.\-route\-Left\-And\-Right\-Sides(), Rout\-Matched\-Capacitor.\-route\-Top\-Or\-Bottom\-Side(), Rout\-Matched\-Capacitor.\-set\-Layers(), Capacitor\-Stack.\-set\-Rules(), Capacitor\-Unit.\-set\-Rules(), Rout\-Matched\-Capacitor.\-set\-Rules(), Capacitor\-Unit.\-vpitch, Vertical\-Routing\-Tracks.\-v\-Routing\-Track\-\_\-width, Capacitor\-Stack.\-v\-Routing\-Track\-\_\-width, and Rout\-Matched\-Capacitor.\-v\-Routing\-Track\-X\-Center. - -\hypertarget{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a3b578035b1559391931dade7c2508105}{\index{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}!set\-Rules@{set\-Rules}} -\index{set\-Rules@{set\-Rules}!python::CapacitorRouted::RoutMatchedCapacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}} -\subsubsection[{set\-Rules}]{\setlength{\rightskip}{0pt plus 5cm}def set\-Rules ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a3b578035b1559391931dade7c2508105} - - -Defines technology rules used to draw the layout. - -Some of the rules, namely those describing routing layers and tracks are applicable for both M\-I\-M and P\-I\-P capacitors. However, cuts rules are different. - -\begin{DoxyParagraph}{Remark\-:} -All {\ttfamily Capacitor\-Stack} class rules are also reloaded in this class. An exception is raised if the entered capacitor type is unsupported. -\end{DoxyParagraph} -\begin{DoxyReturn}{Returns} -a dictionary with rules labels as keys and rules content as values. -\end{DoxyReturn} - - -References Capacitor\-Stack.\-capacitor\-Type, Capacitor\-Unit.\-capacitor\-Type, Rout\-Matched\-Capacitor.\-capacitor\-Type, Capacitor\-Stack.\-min\-Enclosure\-\_\-h\-Routing\-Layer\-\_\-top\-Plate\-\_\-cut, Rout\-Matched\-Capacitor.\-min\-Enclosure\-\_\-h\-Routing\-Layer\-\_\-top\-Plate\-\_\-cut, Rout\-Matched\-Capacitor.\-min\-Spacing\-\_\-h\-Routing\-Layer, Rout\-Matched\-Capacitor.\-min\-Spacing\-\_\-h\-Routing\-Layer\-\_\-top\-Plate\-\_\-cut, Rout\-Matched\-Capacitor.\-min\-Spacing\-\_\-h\-Routing\-Layer\-\_\-v\-Routing\-Track\-\_\-cut, Rout\-Matched\-Capacitor.\-min\-Spacing\-\_\-h\-Routing\-Track\-Cut, Capacitor\-Stack.\-min\-Spacing\-\_\-v\-Routing\-Track\-Cut, Rout\-Matched\-Capacitor.\-min\-Spacing\-\_\-v\-Routing\-Track\-Cut, Capacitor\-Stack.\-min\-Width\-\_\-h\-Routing\-Layer\-\_\-top\-Plate\-\_\-cut, and Rout\-Matched\-Capacitor.\-min\-Width\-\_\-h\-Routing\-Layer\-\_\-top\-Plate\-\_\-cut. - - - -Referenced by Rout\-Matched\-Capacitor.\-route(), and Vertical\-Routing\-Tracks.\-set\-Rules(). - -\hypertarget{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_ae361a87f8ad999bb5f1b9851773f481b}{\index{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}!set\-Layers@{set\-Layers}} -\index{set\-Layers@{set\-Layers}!python::CapacitorRouted::RoutMatchedCapacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}} -\subsubsection[{set\-Layers}]{\setlength{\rightskip}{0pt plus 5cm}def set\-Layers ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_ae361a87f8ad999bb5f1b9851773f481b} - - -Defines all physical layers used to draw the layout. - -Layers are loaded using {\ttfamily Data\-Base} A\-P\-I. The same routing layers are used for both capacitor types except cuts layers that connect top plates to vertical routing tracks. Basicaly, metal 2, meta 3, cut 1 and cut 2 are the ones defined. \begin{DoxyReturn}{Returns} -a dictionary composed of layers labels as keys and layers as values. -\end{DoxyReturn} - - -References Capacitor\-Stack.\-capacitor\-Type, Capacitor\-Unit.\-capacitor\-Type, Rout\-Matched\-Capacitor.\-capacitor\-Type, Capacitor\-Stack.\-dummy\-Ring, and Rout\-Matched\-Capacitor.\-dummy\-Ring. - - - -Referenced by Rout\-Matched\-Capacitor.\-route(). - -\hypertarget{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a20b46b43488cc58c302b123a89299d85}{\index{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}!compute\-Dimensions@{compute\-Dimensions}} -\index{compute\-Dimensions@{compute\-Dimensions}!python::CapacitorRouted::RoutMatchedCapacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}} -\subsubsection[{compute\-Dimensions}]{\setlength{\rightskip}{0pt plus 5cm}def compute\-Dimensions ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{bb\-Mode} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a20b46b43488cc58c302b123a89299d85} - - -Computes, through simple instructions and functions calls, layout variables detailed in Figure 2. - - - -References Capacitor\-Stack.\-abutment\-Box\-\_\-spacing, Rout\-Matched\-Capacitor.\-abutment\-Box\-\_\-spacing, Vertical\-Routing\-Tracks.\-capacitors\-Number, Capacitor\-Stack.\-capacitors\-Number, Rout\-Matched\-Capacitor.\-compute\-Bonding\-Box\-Dim\-Inbb\-Mode(), Rout\-Matched\-Capacitor.\-compute\-H\-R\-Layer\-Y\-Center(), Rout\-Matched\-Capacitor.\-compute\-H\-Routing\-Track\-Y\-Center(), Rout\-Matched\-Capacitor.\-h\-Routing\-Layer\-\_\-width, Capacitor\-Stack.\-matrix\-Dim, Vertical\-Routing\-Tracks.\-matrix\-Dim, Rout\-Matched\-Capacitor.\-maximum\-Position, Capacitor\-Stack.\-min\-Enclosure\-\_\-h\-Routing\-Layer\-\_\-top\-Plate\-\_\-cut, Rout\-Matched\-Capacitor.\-min\-Enclosure\-\_\-h\-Routing\-Layer\-\_\-top\-Plate\-\_\-cut, Vertical\-Routing\-Tracks.\-min\-Enclosure\-\_\-h\-Routing\-Layer\-\_\-v\-Routing\-Track\-\_\-cut, Rout\-Matched\-Capacitor.\-minimum\-Position, Vertical\-Routing\-Tracks.\-min\-Width\-\_\-h\-Routing\-Layer, Capacitor\-Stack.\-min\-Width\-\_\-h\-Routing\-Layer\-\_\-top\-Plate\-\_\-cut, Rout\-Matched\-Capacitor.\-min\-Width\-\_\-h\-Routing\-Layer\-\_\-top\-Plate\-\_\-cut, Vertical\-Routing\-Tracks.\-min\-Width\-\_\-h\-Routing\-Layer\-\_\-v\-Routing\-Track\-\_\-cut, Rout\-Matched\-Capacitor.\-v\-Routing\-Track\-\_\-spacing, Vertical\-Routing\-Tracks.\-v\-Routing\-Track\-\_\-width, Capacitor\-Stack.\-v\-Routing\-Track\-\_\-width, Rout\-Matched\-Capacitor.\-v\-Routing\-Track\-Dict, and Rout\-Matched\-Capacitor.\-v\-Routing\-Track\-X\-Center. - - - -Referenced by Rout\-Matched\-Capacitor.\-route(). - -\hypertarget{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_ab00cae047369eb93c10e44e316fa991b}{\index{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}!compute\-H\-Routing\-Track\-Y\-Center@{compute\-H\-Routing\-Track\-Y\-Center}} -\index{compute\-H\-Routing\-Track\-Y\-Center@{compute\-H\-Routing\-Track\-Y\-Center}!python::CapacitorRouted::RoutMatchedCapacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}} -\subsubsection[{compute\-H\-Routing\-Track\-Y\-Center}]{\setlength{\rightskip}{0pt plus 5cm}def compute\-H\-Routing\-Track\-Y\-Center ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_ab00cae047369eb93c10e44e316fa991b} - - -Computes centers' ordinates of the eight horizontal routing tracks. - -The tracks include four on top and four on bottom of the matrix. To do the computations, fist, center of the first bottom or top track, given in Figure 2, is computed. Then, all adjacent three centers are deduced by simples translation of the first one. Translation quantity is equal to the sum of distance between adjacent routing tracks, self.\-h\-Routing\-Tracks\-\_\-spacing, and half width of the routing track itself, {\ttfamily self.\-h\-Routing\-Track\-\_\-width}. - -References Rout\-Matched\-Capacitor.\-\_\-\-\_\-set\-Plates\-Ids\-\_\-\-\_\-(), Capacitor\-Unit.\-hpitch, Rout\-Matched\-Capacitor.\-h\-Routingtrack\-Y\-Center, Rout\-Matched\-Capacitor.\-maximum\-Position, and Rout\-Matched\-Capacitor.\-minimum\-Position. - - - -Referenced by Rout\-Matched\-Capacitor.\-compute\-Dimensions(). - -\hypertarget{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a0d90b75abe0f4ce0f0b9b1b405462300}{\index{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}!compute\-H\-R\-Layer\-Y\-Center@{compute\-H\-R\-Layer\-Y\-Center}} -\index{compute\-H\-R\-Layer\-Y\-Center@{compute\-H\-R\-Layer\-Y\-Center}!python::CapacitorRouted::RoutMatchedCapacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}} -\subsubsection[{compute\-H\-R\-Layer\-Y\-Center}]{\setlength{\rightskip}{0pt plus 5cm}def compute\-H\-R\-Layer\-Y\-Center ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a0d90b75abe0f4ce0f0b9b1b405462300} - - -Sets the stretching value of top plates. - -Then iteratively computes the centers of horizontal routing layer regarding top and bottom plates. - -References Rout\-Matched\-Capacitor.\-\_\-\-\_\-find\-Possible\-Short\-Circuits\-\_\-\-\_\-(), Vertical\-Routing\-Tracks.\-\_\-\-\_\-set\-Stretching\-\_\-\-\_\-(), Rout\-Matched\-Capacitor.\-\_\-\-\_\-set\-Stretching\-Dy\-Source\-Dy\-Target\-\_\-\-\_\-(), Rout\-Matched\-Capacitor.\-bonding\-Box, Rout\-Matched\-Capacitor.\-capacitor, Rout\-Matched\-Capacitor.\-h\-Routing\-Layer\-\_\-width, Rout\-Matched\-Capacitor.\-h\-Routing\-Layer\-Y\-Center, Rout\-Matched\-Capacitor.\-h\-Routing\-Track\-\_\-width, Rout\-Matched\-Capacitor.\-h\-Routingtrack\-Y\-Center, Capacitor\-Stack.\-matrix\-Dim, Vertical\-Routing\-Tracks.\-matrix\-Dim, Rout\-Matched\-Capacitor.\-min\-Spacing\-\_\-h\-Routing\-Layer, Rout\-Matched\-Capacitor.\-top\-Plate\-Stretching, Vertical\-Routing\-Tracks.\-v\-Routing\-Track\-\_\-width, Capacitor\-Stack.\-v\-Routing\-Track\-\_\-width, and Rout\-Matched\-Capacitor.\-v\-Routing\-Track\-X\-Center. - - - -Referenced by Rout\-Matched\-Capacitor.\-compute\-Dimensions(). - -\hypertarget{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_afbe39494b52b035fe3efdb0ddb896f69}{\index{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}!draw\-H\-Routing\-Tracks@{draw\-H\-Routing\-Tracks}} -\index{draw\-H\-Routing\-Tracks@{draw\-H\-Routing\-Tracks}!python::CapacitorRouted::RoutMatchedCapacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}} -\subsubsection[{draw\-H\-Routing\-Tracks}]{\setlength{\rightskip}{0pt plus 5cm}def draw\-H\-Routing\-Tracks ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{routing\-Tracks\-Layer} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_afbe39494b52b035fe3efdb0ddb896f69} - - -Iteratively draws horizontal routing tracks on top and bottom positions of the matrix using physical layer {\ttfamily routing\-Tracks\-Layer}. - - - -References Rout\-Matched\-Capacitor.\-h\-Routing\-Track\-\_\-width, Rout\-Matched\-Capacitor.\-h\-Routingtrack\-Y\-Center, Vertical\-Routing\-Tracks.\-nets, Capacitor\-Stack.\-nets, and Rout\-Matched\-Capacitor.\-v\-Routing\-Track\-X\-Center. - - - -Referenced by Rout\-Matched\-Capacitor.\-route(). - -\hypertarget{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a6bba48a4b1d4834c6617a5af5553be1c}{\index{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}!draw\-H\-R\-Layers@{draw\-H\-R\-Layers}} -\index{draw\-H\-R\-Layers@{draw\-H\-R\-Layers}!python::CapacitorRouted::RoutMatchedCapacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}} -\subsubsection[{draw\-H\-R\-Layers}]{\setlength{\rightskip}{0pt plus 5cm}def draw\-H\-R\-Layers ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{x\-Plate\-R\-Layer} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a6bba48a4b1d4834c6617a5af5553be1c} - - -Iteratively draws the horizontal routing layers starting with bottom left elementary capacitor $ C_{00} $. - - - -References Rout\-Matched\-Capacitor.\-\_\-\-\_\-compute\-Connections\-\_\-\-\_\-(), Rout\-Matched\-Capacitor.\-h\-Routing\-Layer\-\_\-width, Rout\-Matched\-Capacitor.\-h\-Routing\-Layer\-Y\-Center, Vertical\-Routing\-Tracks.\-matching\-Scheme, Capacitor\-Stack.\-matching\-Scheme, Vertical\-Routing\-Tracks.\-matrix\-Dim, Capacitor\-Stack.\-matrix\-Dim, Vertical\-Routing\-Tracks.\-nets, and Capacitor\-Stack.\-nets. - - - -Referenced by Rout\-Matched\-Capacitor.\-route(). - -\hypertarget{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a2019f4bb1e22a8d622ce4d155c934eb0}{\index{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}!draw\-Cuts@{draw\-Cuts}} -\index{draw\-Cuts@{draw\-Cuts}!python::CapacitorRouted::RoutMatchedCapacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}} -\subsubsection[{draw\-Cuts}]{\setlength{\rightskip}{0pt plus 5cm}def draw\-Cuts ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{layer\-\_\-h\-R\-Track\-\_\-h\-R\-Layer, } -\item[{}]{layer\-\_\-tracks\-Cut, } -\item[{}]{layer\-\_\-top\-Plate\-Cut} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a2019f4bb1e22a8d622ce4d155c934eb0} - - -Draws all required cuts using physical layers \-: - - -\begin{DoxyItemize} -\item {\ttfamily layer\-\_\-h\-R\-Track\-\_\-h\-R\-Layer} to connect bottom plates to vertical routing tracks, -\item {\ttfamily layer\-\_\-tracks\-Cut} to connect vertical routing tracks to horizontal ones, -\item {\ttfamily layer\-\_\-top\-Plate\-Cut} to connect top plates to vertical routing tracks. A\-Lso in {\ttfamily draw\-Cuts}, n\-Umber of maximum cuts number on every layer is computed and cuts enclosure is adjusted according to layer's width. -\end{DoxyItemize} - -References Rout\-Matched\-Capacitor.\-\_\-\-\_\-set\-Plates\-Labels\-\_\-\-\_\-(), Vertical\-Routing\-Tracks.\-capacitor\-Ids, Vertical\-Routing\-Tracks.\-capacitors\-Number, Capacitor\-Stack.\-capacitors\-Number, Rout\-Matched\-Capacitor.\-draw\-Cuts\-\_\-stretched\-Top\-Plate(), Rout\-Matched\-Capacitor.\-draw\-Cuts\-\_\-v\-Routing\-Track\-\_\-\-H\-R\-Layer(), Rout\-Matched\-Capacitor.\-draw\-Cuts\-\_\-v\-Routing\-Track\-\_\-h\-Routing\-Track(), Rout\-Matched\-Capacitor.\-draw\-One\-Cut\-\_\-v\-Routing\-Track\-\_\-\-H\-R\-Layer(), Rout\-Matched\-Capacitor.\-h\-Routing\-Layer\-Y\-Center, Vertical\-Routing\-Tracks.\-matching\-Scheme, Capacitor\-Stack.\-matching\-Scheme, Vertical\-Routing\-Tracks.\-matrix\-Dim, Capacitor\-Stack.\-matrix\-Dim, Capacitor\-Stack.\-min\-Enclosure\-\_\-v\-Routing\-Track\-Cut, Rout\-Matched\-Capacitor.\-min\-Spacing\-\_\-h\-Routing\-Track\-Cut, Capacitor\-Stack.\-min\-Spacing\-\_\-v\-Routing\-Track\-Cut, Rout\-Matched\-Capacitor.\-min\-Spacing\-\_\-v\-Routing\-Track\-Cut, Vertical\-Routing\-Tracks.\-min\-Width\-\_\-h\-Routing\-Track\-Cut, Capacitor\-Stack.\-min\-Width\-\_\-v\-Routing\-Track\-Cut, Vertical\-Routing\-Tracks.\-nets, Capacitor\-Stack.\-nets, Vertical\-Routing\-Tracks.\-v\-Routing\-Track\-\_\-width, Capacitor\-Stack.\-v\-Routing\-Track\-\_\-width, and Rout\-Matched\-Capacitor.\-v\-Routing\-Track\-X\-Center. - - - -Referenced by Rout\-Matched\-Capacitor.\-route(). - -\hypertarget{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_ab3fd42d04811b9c88654c0ca0e6e2de7}{\index{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}!draw\-One\-Cut\-\_\-v\-Routing\-Track\-\_\-\-H\-R\-Layer@{draw\-One\-Cut\-\_\-v\-Routing\-Track\-\_\-\-H\-R\-Layer}} -\index{draw\-One\-Cut\-\_\-v\-Routing\-Track\-\_\-\-H\-R\-Layer@{draw\-One\-Cut\-\_\-v\-Routing\-Track\-\_\-\-H\-R\-Layer}!python::CapacitorRouted::RoutMatchedCapacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}} -\subsubsection[{draw\-One\-Cut\-\_\-v\-Routing\-Track\-\_\-\-H\-R\-Layer}]{\setlength{\rightskip}{0pt plus 5cm}def draw\-One\-Cut\-\_\-v\-Routing\-Track\-\_\-\-H\-R\-Layer ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{net, } -\item[{}]{cut\-Layer, } -\item[{}]{cut\-X\-Min, } -\item[{}]{cut\-Y\-Min, } -\item[{}]{cut\-Number} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_ab3fd42d04811b9c88654c0ca0e6e2de7} - - -Draws one cut, in layer {\ttfamily cut\-Layer}, in order to connect a vertical routing track, at position {\ttfamily cut\-X\-Min} in metal 2, and a horizontal routing track, at position {\ttfamily cut\-Y\-Min} in metal 3. - - - -References Rout\-Matched\-Capacitor.\-min\-Spacing\-\_\-h\-Routing\-Layer\-\_\-v\-Routing\-Track\-\_\-cut, and Vertical\-Routing\-Tracks.\-min\-Width\-\_\-h\-Routing\-Layer\-\_\-v\-Routing\-Track\-\_\-cut. - - - -Referenced by Rout\-Matched\-Capacitor.\-draw\-Cuts(). - -\hypertarget{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a05e49f5537d31e0ab19b8a86eb6e7b1c}{\index{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}!draw\-Cuts\-\_\-v\-Routing\-Track\-\_\-h\-Routing\-Track@{draw\-Cuts\-\_\-v\-Routing\-Track\-\_\-h\-Routing\-Track}} -\index{draw\-Cuts\-\_\-v\-Routing\-Track\-\_\-h\-Routing\-Track@{draw\-Cuts\-\_\-v\-Routing\-Track\-\_\-h\-Routing\-Track}!python::CapacitorRouted::RoutMatchedCapacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}} -\subsubsection[{draw\-Cuts\-\_\-v\-Routing\-Track\-\_\-h\-Routing\-Track}]{\setlength{\rightskip}{0pt plus 5cm}def draw\-Cuts\-\_\-v\-Routing\-Track\-\_\-h\-Routing\-Track ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{cut\-Layer, } -\item[{}]{cut\-Number, } -\item[{}]{enclosure\-\_\-cut} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a05e49f5537d31e0ab19b8a86eb6e7b1c} - - -Draws cuts to connect vertical routing tracks in metal 2 and horizontal routing tracks in metal 3. - - - -References Rout\-Matched\-Capacitor.\-\_\-\-\_\-set\-Plates\-Ids\-\_\-\-\_\-(), Rout\-Matched\-Capacitor.\-capacitor, Rout\-Matched\-Capacitor.\-dummy\-Ring\-Capacitor, Rout\-Matched\-Capacitor.\-h\-Routing\-Layer\-Y\-Center, Rout\-Matched\-Capacitor.\-h\-Routingtrack\-Y\-Center, Vertical\-Routing\-Tracks.\-matching\-Scheme, Capacitor\-Stack.\-matching\-Scheme, Vertical\-Routing\-Tracks.\-matrix\-Dim, Capacitor\-Stack.\-matrix\-Dim, Capacitor\-Stack.\-min\-Enclosure\-\_\-h\-Routing\-Layer\-\_\-top\-Plate\-\_\-cut, Rout\-Matched\-Capacitor.\-min\-Enclosure\-\_\-h\-Routing\-Layer\-\_\-top\-Plate\-\_\-cut, Capacitor\-Stack.\-min\-Enclosure\-\_\-v\-Routing\-Track\-Cut, Rout\-Matched\-Capacitor.\-min\-Spacing\-\_\-h\-Routing\-Layer\-\_\-top\-Plate\-\_\-cut, Rout\-Matched\-Capacitor.\-min\-Spacing\-\_\-h\-Routing\-Track\-Cut, Capacitor\-Stack.\-min\-Spacing\-\_\-v\-Routing\-Track\-Cut, Rout\-Matched\-Capacitor.\-min\-Spacing\-\_\-v\-Routing\-Track\-Cut, Capacitor\-Stack.\-min\-Width\-\_\-h\-Routing\-Layer\-\_\-top\-Plate\-\_\-cut, Rout\-Matched\-Capacitor.\-min\-Width\-\_\-h\-Routing\-Layer\-\_\-top\-Plate\-\_\-cut, Vertical\-Routing\-Tracks.\-min\-Width\-\_\-h\-Routing\-Track\-Cut, Capacitor\-Stack.\-min\-Width\-\_\-v\-Routing\-Track\-Cut, Vertical\-Routing\-Tracks.\-nets, Capacitor\-Stack.\-nets, Vertical\-Routing\-Tracks.\-v\-Routing\-Track\-\_\-width, Capacitor\-Stack.\-v\-Routing\-Track\-\_\-width, and Rout\-Matched\-Capacitor.\-v\-Routing\-Track\-X\-Center. - - - -Referenced by Rout\-Matched\-Capacitor.\-draw\-Cuts(). - -\hypertarget{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a7d642764cf9e385710751eec3f43f7af}{\index{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}!\-\_\-\-\_\-stretch\-Top\-Plates\-\_\-\-\_\-@{\-\_\-\-\_\-stretch\-Top\-Plates\-\_\-\-\_\-}} -\index{\-\_\-\-\_\-stretch\-Top\-Plates\-\_\-\-\_\-@{\-\_\-\-\_\-stretch\-Top\-Plates\-\_\-\-\_\-}!python::CapacitorRouted::RoutMatchedCapacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}} -\subsubsection[{\-\_\-\-\_\-stretch\-Top\-Plates\-\_\-\-\_\-}]{\setlength{\rightskip}{0pt plus 5cm}def \-\_\-\-\_\-stretch\-Top\-Plates\-\_\-\-\_\- ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{capacitor, } -\item[{}]{rlayer} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a7d642764cf9e385710751eec3f43f7af} - - -Iteratively performs top plates stretching for the capacitor matrix. - -Vertical segments are connected to top plate routing layer. -\begin{DoxyParams}{Parameters} -{\em capacitor} & Capacitor matrix. \\ -\hline -{\em rlayer} & Layer of the drawn vertical rectangle. \\ -\hline -\end{DoxyParams} - - -References Rout\-Matched\-Capacitor.\-\_\-\-\_\-stretch\-Top\-Plate\-Compact\-Cap\-\_\-\-\_\-(), Vertical\-Routing\-Tracks.\-matching\-Scheme, Capacitor\-Stack.\-matching\-Scheme, Vertical\-Routing\-Tracks.\-matrix\-Dim, Capacitor\-Stack.\-matrix\-Dim, Vertical\-Routing\-Tracks.\-nets, and Capacitor\-Stack.\-nets. - - - -Referenced by Rout\-Matched\-Capacitor.\-route(). - -\hypertarget{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a57eade928345587b01420a05be475a8f}{\index{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}!\-\_\-\-\_\-stretch\-Top\-Plate\-Compact\-Cap\-\_\-\-\_\-@{\-\_\-\-\_\-stretch\-Top\-Plate\-Compact\-Cap\-\_\-\-\_\-}} -\index{\-\_\-\-\_\-stretch\-Top\-Plate\-Compact\-Cap\-\_\-\-\_\-@{\-\_\-\-\_\-stretch\-Top\-Plate\-Compact\-Cap\-\_\-\-\_\-}!python::CapacitorRouted::RoutMatchedCapacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}} -\subsubsection[{\-\_\-\-\_\-stretch\-Top\-Plate\-Compact\-Cap\-\_\-\-\_\-}]{\setlength{\rightskip}{0pt plus 5cm}def \-\_\-\-\_\-stretch\-Top\-Plate\-Compact\-Cap\-\_\-\-\_\- ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{net, } -\item[{}]{capacitor, } -\item[{}]{routing\-Layer, } -\item[{}]{j = {\ttfamily 0}} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a57eade928345587b01420a05be475a8f} - - -Draws vertical stretched layers for a given elementary capacitor. - - - -References Rout\-Matched\-Capacitor.\-\_\-\-\_\-set\-Stretching\-Dy\-Source\-Dy\-Target\-\_\-\-\_\-(), and Rout\-Matched\-Capacitor.\-top\-Plate\-Stretching. - - - -Referenced by Rout\-Matched\-Capacitor.\-\_\-\-\_\-stretch\-Top\-Plates\-\_\-\-\_\-(). - -\hypertarget{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a1077752f46c512f70377cc60bd772034}{\index{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}!\-\_\-\-\_\-set\-Stretching\-Dy\-Source\-Dy\-Target\-\_\-\-\_\-@{\-\_\-\-\_\-set\-Stretching\-Dy\-Source\-Dy\-Target\-\_\-\-\_\-}} -\index{\-\_\-\-\_\-set\-Stretching\-Dy\-Source\-Dy\-Target\-\_\-\-\_\-@{\-\_\-\-\_\-set\-Stretching\-Dy\-Source\-Dy\-Target\-\_\-\-\_\-}!python::CapacitorRouted::RoutMatchedCapacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}} -\subsubsection[{\-\_\-\-\_\-set\-Stretching\-Dy\-Source\-Dy\-Target\-\_\-\-\_\-}]{\setlength{\rightskip}{0pt plus 5cm}def \-\_\-\-\_\-set\-Stretching\-Dy\-Source\-Dy\-Target\-\_\-\-\_\- ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{capacitor, } -\item[{}]{deltay} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_a1077752f46c512f70377cc60bd772034} - - -Sets the abcissas of the extremities of the vertical stretching to be applied to capacitor's top plates for a given elementary capacitor in the matrix. - - -\begin{DoxyParams}{Parameters} -{\em capacitor} & .values() Elementary unit capacitor. \\ -\hline -{\em deltay} & Stretching value. \\ -\hline -\end{DoxyParams} -\begin{DoxyReturn}{Returns} -A list that contains {\ttfamily dy\-Source} and as top extremity and bottom extermity, respectively. -\end{DoxyReturn} - - -Referenced by Rout\-Matched\-Capacitor.\-\_\-\-\_\-stretch\-Top\-Plate\-Compact\-Cap\-\_\-\-\_\-(), and Rout\-Matched\-Capacitor.\-compute\-H\-R\-Layer\-Y\-Center(). - -\hypertarget{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_aaaf2e610688441a439b8a3624e1393b9}{\index{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}!\-\_\-\-\_\-compute\-Connections\-\_\-\-\_\-@{\-\_\-\-\_\-compute\-Connections\-\_\-\-\_\-}} -\index{\-\_\-\-\_\-compute\-Connections\-\_\-\-\_\-@{\-\_\-\-\_\-compute\-Connections\-\_\-\-\_\-}!python::CapacitorRouted::RoutMatchedCapacitor@{python\-::\-Capacitor\-Routed\-::\-Rout\-Matched\-Capacitor}} -\subsubsection[{\-\_\-\-\_\-compute\-Connections\-\_\-\-\_\-}]{\setlength{\rightskip}{0pt plus 5cm}def \-\_\-\-\_\-compute\-Connections\-\_\-\-\_\- ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{i, } -\item[{}]{j, } -\item[{}]{capacitor\-Identifier} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor_aaaf2e610688441a439b8a3624e1393b9} - - -Computes horizontal routing layers source and target abcissas for top and bottom plates connections to its associated routing track. - - -\begin{DoxyParams}{Parameters} -{\em (i,j)} & row and column indexes, respectively, in the matrix which describe the elementary capacitor position in the matrix. \\ -\hline -{\em capacitor\-Identifier} & equal to '1' if C1 and '2' if C2. \\ -\hline -\end{DoxyParams} -\begin{DoxyReturn}{Returns} -A nested dicitionary. The overal dictionary is composed of keys equal to {\ttfamily top\-Plate} and bottom\-Plate and values equal to sub-\/dictionaries. The sub-\/dictionaries, are in their turn composed of two keys standing for the abcissa of the source and the abcissa of the target. -\end{DoxyReturn} -\begin{DoxyParagraph}{Remark\-:} -Naturally, an exception is raised if an unsupported capacitor identifier is given. -\end{DoxyParagraph} - - -References Rout\-Matched\-Capacitor.\-\_\-\-\_\-find\-H\-R\-L\-Dy\-Trarget\-\_\-\-\_\-(), Rout\-Matched\-Capacitor.\-\_\-\-\_\-is\-Capacitor\-Adummy\-\_\-\-\_\-(), Rout\-Matched\-Capacitor.\-\_\-\-\_\-set\-Plates\-Labels\-\_\-\-\_\-(), Rout\-Matched\-Capacitor.\-capacitor, Vertical\-Routing\-Tracks.\-capacitor\-Ids, Vertical\-Routing\-Tracks.\-capacitors\-Number, Capacitor\-Stack.\-capacitors\-Number, Capacitor\-Stack.\-dummy\-Element, Rout\-Matched\-Capacitor.\-dummy\-Element, Capacitor\-Stack.\-dummy\-Ring, Rout\-Matched\-Capacitor.\-dummy\-Ring, Vertical\-Routing\-Tracks.\-matching\-Scheme, Capacitor\-Stack.\-matching\-Scheme, Vertical\-Routing\-Tracks.\-matrix\-Dim, Capacitor\-Stack.\-matrix\-Dim, Vertical\-Routing\-Tracks.\-nets, Capacitor\-Stack.\-nets, Vertical\-Routing\-Tracks.\-v\-Routing\-Track\-\_\-width, Capacitor\-Stack.\-v\-Routing\-Track\-\_\-width, Rout\-Matched\-Capacitor.\-v\-Routing\-Track\-X\-Center, and Rout\-Matched\-Capacitor.\-v\-R\-Ts\-Distribution. - - - -Referenced by Rout\-Matched\-Capacitor.\-draw\-H\-R\-Layers(). - - - -The documentation for this class was generated from the following file\-:\begin{DoxyCompactItemize} -\item -Capacitor\-Routed.\-py\end{DoxyCompactItemize} diff --git a/oroshi/doc/latex/classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor__inherit__graph.md5 b/oroshi/doc/latex/classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor__inherit__graph.md5 deleted file mode 100644 index 597d36ac..00000000 --- a/oroshi/doc/latex/classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor__inherit__graph.md5 +++ /dev/null @@ -1 +0,0 @@ -0e5f4d4a0b1b72800d34abf8064118a1 \ No newline at end of file diff --git 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\hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ac775ee34451fdfa742b318538164070e}{\-\_\-\-\_\-init\-\_\-\-\_\-} -\begin{DoxyCompactList}\small\item\em This is the class constructor. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a217d8871ff92e0ad45001492875261e1}{\-\_\-\-\_\-set\-Capacitor\-Per\-Unit\-\_\-\-\_\-} -\begin{DoxyCompactList}\small\item\em Sets the area and perimeter capacitances as specified in 350 nm A\-M\-S technology and according to {\ttfamily capacitor\-Type} (M\-I\-M or P\-I\-P). \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a914a2dadb095ebca95a60ee5c8ddd7a0}{\-\_\-\-\_\-compute\-Cap\-Dim\-\_\-\-\_\-} -\begin{DoxyCompactList}\small\item\em Computes width and length of the capacitor. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ac114a243874b413707b6fa7d30529d76}{\-\_\-\-\_\-is\-Capacitor\-Unit\-O\-K\-\_\-\-\_\-} -\begin{DoxyCompactList}\small\item\em Checks if the computed capacitor dimensions exceed or are less than maximum and minimum limits, respectively, as specified in technology rules. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a3b578035b1559391931dade7c2508105}{set\-Rules} -\begin{DoxyCompactList}\small\item\em Selects technological rules according to the capacitor type. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a127dcda66d458f9320e541649101607e}{get\-Capacitor\-Type} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a7afefaf3a15d637ffe979bc54d57c6c2}{get\-Maximum\-Cap\-Width} -\begin{DoxyCompactList}\small\item\em maximum size of capacitor's top plate. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aacb6369181aa03823cb1ce42adb0ee25}{get\-Minimum\-Cap\-Width} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a7be694eb909dc1e49326e3b5dd1e6887}{get\-Layers} -\begin{DoxyCompactList}\small\item\em Loads the technology file then extracts the adequate layers according to the capacitor type (M\-I\-M or P\-I\-P). \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a5b7ef0221e471e99fa7f0a87a28ba1ea}{create} -\begin{DoxyCompactList}\small\item\em When bonding box mode is activated, the function draws all layout physical layers of the capacitor after checking its dimensions. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ae2ec4683c7f6c30fbb1687934673410c}{draw\-Capacitor} -\begin{DoxyCompactList}\small\item\em Draws all layout physicial layers of the capacitor. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a8f71111f71d084f05742fadf134cb87e}{compute\-Bottom\-Plate\-Cuts} -\begin{DoxyCompactList}\small\item\em Computes needed parameters to draw bottom plate cuts in its exact position, including \-: \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aceb634d48d79f2079c690297c820da0b}{compute\-Top\-Plate\-Cuts} -\begin{DoxyCompactList}\small\item\em Computes needed parameters to draw top plate cuts in its exact position, including \-: \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ac5cd73be473bc321a29a75311f808835}{draw\-Abutment\-Box} -\begin{DoxyCompactList}\small\item\em Draws the abutment box of the capacitor in position {\ttfamily $<$}(abutment\-Box\-X\-Min, abutment\-Box\-Y\-Min)$>$. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a7b4116e4696b869f462d86b1ddf00246}{draw\-One\-Plate} -\begin{DoxyCompactList}\small\item\em Draws the top or bottom plate through inflation of the Box under it. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a1a998a3072560eaee998c9e5531a5f5b}{draw\-Bottom\-Plate\-Cut} -\begin{DoxyCompactList}\small\item\em Draws the required cuts to connect the bottom plate. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a8d4cd239412ffde81f0cda52123b9c1d}{draw\-Top\-Plate\-Cut} -\begin{DoxyCompactList}\small\item\em Draws the top plate's cuts after computing the maximal number of cuts that can be placed and its exact enclosure in the top plate. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a444cc6c0ee175ba22b5092d0706bc0d6}{draw\-Routing\-Layers} -\begin{DoxyCompactList}\small\item\em Draws the routing layers of both bottom and top plates after computing widths and the exact position of these layers. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a5c03a894501e69f2e6a6d40e93df8ef2}{cut\-Max\-Number} -\begin{DoxyCompactList}\small\item\em Computes the maximal number of cuts to be placed on a layer of width {\ttfamily width\-\_\-layer} considering specifications such as the spacing between the cuts, its width and its enclosure in the layer. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a95ebae95cc0be711de5adbb1faa85f98}{cut\-Line} -\begin{DoxyCompactList}\small\item\em Creates a horizontal or vertical line of contacts according to the specified direction. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a4b8fe45cf122a2682cd8120bcbc5e5fd}{cut\-Matrix} -\begin{DoxyCompactList}\small\item\em Creates a matrix of cuts by vertically stacking horizontal lines of identical cuts. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a876d31edaaabe0716d6fbe6f6c0c7b75}{get\-Bottom\-Plate\-Y\-Max} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ae461baa28fdfa09bad07b3f1073a46b7}{get\-Bottom\-Plate\-Left\-Cut\-X\-Min} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aae1849792395fccc12e921450a29980b}{get\-Bottom\-Plate\-Left\-Cut\-Y\-Min} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a2f7b75e47a238defa63e04c75e0be016}{get\-Bottom\-Plate\-Left\-Cut\-Y\-Max} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a9e59fed4e9829bac60edbd38195cdd90}{get\-Bottom\-Plate\-Right\-Cut\-X\-Min} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a0e362c0f80ab5a70fa3e4139d0009ef1}{get\-Bottom\-Plate\-Right\-Cut\-Y\-Min} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ae31425a5f9b3d7a0829c1abc454e2834}{get\-Bottom\-Plate\-Right\-Cut\-Y\-Max} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ae3887820ee80da10f77b451e5f068635}{get\-Bot\-Plate\-Left\-R\-Layer\-X\-Max} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a2d9186515736c9fd74725eca251f6e2b}{get\-Bottom\-Plate\-Right\-Cut\-Y\-Center} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a52e8ea7265119216e234eab32bc542ef}{get\-Bot\-Plate\-Left\-R\-Layer\-X\-Min} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a2f87580a615f6b0450d43a032adf81d5}{get\-Bot\-Plate\-R\-Layer\-Y\-Min} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aa6cb9e5f6ba2d4e4ce5f63ca1d785e7e}{get\-Bot\-Plate\-R\-Layer\-Y\-Max} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a3463504463c87fb7aab28ca04597c169}{get\-Bot\-Plate\-R\-Layer\-Width} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aff2f6d078abdcf0d679aa9b697928f34}{get\-Bot\-Plate\-Right\-R\-Layer\-X\-Center} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a7440876afb0ff33ba0ee5cea4e9e0aed}{get\-Bot\-Plate\-Left\-R\-Layer\-X\-Center} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a836a7c11713aa3a08504a498b90fb5ee}{get\-Top\-Plate\-R\-Layer\-Y\-Min} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aea137748a99552369414fc5ffec3a41d}{get\-Top\-Plate\-R\-Layer\-Y\-Max} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a9c1452c170eeb58d060bb5fe72fae5a9}{get\-Top\-Plate\-R\-Layer\-Width} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a295a807958d27c156f87102762d353d6}{get\-Top\-Plate\-R\-Layer\-X\-Center} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a28208011c71e1712625c1148a67d943c}{get\-Top\-Plate\-R\-Layer\-X\-Min} -\item -def \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a9788696eb8f1cffde53de39c7f2ffcaa}{get\-Top\-Plate\-R\-Layer\-X\-Max} -\end{DoxyCompactItemize} - - -\subsection{Detailed Description} -Draws a capacitor of type Poly-\/\-Poly or Metal-\/\-Metal in 350 nm A\-M\-S C\-M\-O\-S technology. - -P\-I\-P and M\-I\-M capacitors are the result of surface superposition between poly1 and poly2 or metal2 and metalcap layers, respectively. Given the capacitor value, layout dimensions are computed, then, capacitor layers are drawn. Capacitor value, $C$, is given in the expression below, where $ C_{a}, C_{p}, A $ and $ P $ are, area capacitance, perimeter capacitance, area and permiter of the capacitor, respectively \-: \[ C = C_{a}A + C_{p}P \] The drawn layout shape is square. Thus, metcap or poly2 length and width are equal and are computed using the capacitor expression. Furthermore, given $ C_{a} $, $ C_{p} $ and enclosure technological rules, dimensions and positions of the abutment box as well as the bottom plate are computed. Layouts with dimensions that exceed technological limits cannot be drawn. - -\subsection{Constructor \& Destructor Documentation} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ac775ee34451fdfa742b318538164070e}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!\-\_\-\-\_\-init\-\_\-\-\_\-@{\-\_\-\-\_\-init\-\_\-\-\_\-}} -\index{\-\_\-\-\_\-init\-\_\-\-\_\-@{\-\_\-\-\_\-init\-\_\-\-\_\-}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{\-\_\-\-\_\-init\-\_\-\-\_\-}]{\setlength{\rightskip}{0pt plus 5cm}def \-\_\-\-\_\-init\-\_\-\-\_\- ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{device, } -\item[{}]{capacitor\-Type, } -\item[{}]{abutment\-Box\-Position, } -\item[{}]{capacitance = {\ttfamily 0}, } -\item[{}]{cap\-Dim = {\ttfamily \{\}}} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ac775ee34451fdfa742b318538164070e} - - -This is the class constructor. - -Few of the class attributes final values are computed in this level. Most of attributes are only initialized to zero or empty values. Then, it is computed in dedicated class method. Input parameters are \-: -\begin{DoxyParams}{Parameters} -{\em device} & {\bf Hurricane} A\-M\-S device into which layout is drawn. \\ -\hline -{\em capacitance} & Capacitor value, expressed in $ femto Farad (fF) $. \\ -\hline -{\em abutment\-Box\-Position} & A list containing abscissa and ordinate of the bottom left corner of the abutment box.\\ -\hline -\end{DoxyParams} -Class attributes are described in the list below. Most of class attributes refer to layout dimensions. Dictionaries are used to group attributes related to the same layout varibale. Layout dimensions and variables are described in Figure 1. - - -\begin{DoxyParams}{Parameters} -{\em device} & {\bf Hurricane} A\-M\-S device into which layout is drawn. \\ -\hline -{\em capacitance} & Capacitor value, expressed in $ femto Farad (fF) $. \\ -\hline -{\em capacitor\-Type} & Can be 'M\-I\-M\-Cap' or 'P\-I\-P\-Cap' as capacitor type. \\ -\hline -{\em abutment\-Box\-Dict} & A dictionary containing abscissa and ordinate of the bottom left corner of the abutment box, (X\-Min) and (Y\-Min), respectively. \\ -\hline -{\em abutment\-Box} & Abutment box drawn square. It is an object of type {\ttfamily Box}. \\ -\hline -{\em bottom\-Plate\-Box} & Bottom plate drawn square. It is an object of type {\ttfamily Box}. \\ -\hline -{\em top\-Plate\-Box} & Top plate drawn square. It is an object of type {\ttfamily Box}. \\ -\hline -{\em cut2\-Matrix\-Dict} & A dictionary containing center position of the left bottom, which is cut the first to be drawn in the matrix of cuts. Initially, the dictionary is empty. It is only updated when {\ttfamily self.\-capacitor\-Type} is equal to {\ttfamily 'M\-I\-M\-Cap'}.\\ -\hline -{\em cut\-Left\-Line\-Dict} & A dictionary containing abcissa and ordinate of the bottom cut in the left line of cuts to be drawn on bottom plate's layer. \\ -\hline -{\em cut\-Right\-Line\-Dict} & A dictionary containing abcissa and ordinate of the bottom cut in the right line of cuts to be drawn on bottom plate's layer. \\ -\hline -{\em top\-Cut\-Line\-Dict} & A dictionary containing abcissa and ordinate of the bottom cut in the right line of cuts to be drawn on top plate's layer. Initially, the dictionary is empty. It is only updated when {\ttfamily self.\-capacitor\-Type} is equal to {\ttfamily 'P\-I\-P\-Cap'}.\\ -\hline -{\em top\-Plate\-R\-Layer\-Dict} & A dictionary containing position information of the top plate's routing layer. The dictionary includes ordinates of the layer's top and bottom extremities, {\ttfamily 'X\-Min'} and {\ttfamily 'Y\-Min'}, respectively, the abcissa of it's center, {\ttfamily 'X\-Center'} and its width, {\ttfamily 'width'}.\\ -\hline -{\em bottom\-Plate\-R\-Layer\-Dict} & A dictionary containing \\ -\hline -{\em enclosure\-\_\-bot\-Plate\-\_\-top\-Plate} & Top plate's layer encolusre in bottom plate's layer. \\ -\hline -{\em minheight\-\_\-top\-Platecut} & Minimum height of cuts for top plate connection to other metal layer. \\ -\hline -{\em top\-Cut\-Line\-Number} & Maximum possible number cuts to be drawn for top plate's connection. \\ -\hline -{\em bottom\-Cut\-Line\-Number} & Maximum possible number cuts to be drawn for top plate's connection.\\ -\hline -\end{DoxyParams} -\begin{DoxyParagraph}{Remark\-:} -Abutment box must be defined as an attribute because the position of dummy capacitor in {\ttfamily Non\-Unit\-Capacitor} class must be precisely defined. -\end{DoxyParagraph} - - -References Capacitor\-Unit.\-\_\-\-\_\-compute\-Capacitance\-\_\-\-\_\-(), Capacitor\-Unit.\-\_\-\-\_\-compute\-Cap\-Dim\-\_\-\-\_\-(), Capacitor\-Unit.\-\_\-\-\_\-init\-Cap\-Dim\-\_\-\-\_\-(), Capacitor\-Unit.\-abutment\-Box, Capacitor\-Unit.\-abutment\-Box\-Dict, Capacitor\-Unit.\-bottom\-Cut\-Line\-Number, Capacitor\-Unit.\-bottom\-Plate\-Box, Capacitor\-Unit.\-bottom\-Plate\-Box\-Dict, Capacitor\-Unit.\-bottom\-Plate\-R\-Layer\-Dict, Capacitor\-Unit.\-capacitor\-Type, Capacitor\-Unit.\-cap\-Dim, Capacitor\-Unit.\-cut2\-Matrix\-Dict, Capacitor\-Unit.\-cut\-Left\-Line\-Dict, Capacitor\-Unit.\-cut\-Right\-Line\-Dict, Capacitor\-Unit.\-device, Stack.\-device, Capacitor\-Unit.\-enclosure\-\_\-bot\-Plate\-\_\-abt\-Box, Capacitor\-Unit.\-enclosure\-\_\-bot\-Plate\-\_\-top\-Plate, Capacitor\-Unit.\-minheight\-\_\-top\-Platecut, Capacitor\-Unit.\-top\-Cut\-Line\-Dict, Capacitor\-Unit.\-top\-Cut\-Line\-Number, Capacitor\-Unit.\-top\-Plate\-Box, Capacitor\-Unit.\-top\-Plate\-Box\-Dict, and Capacitor\-Unit.\-top\-Plate\-R\-Layer\-Dict. - - - -\subsection{Member Function Documentation} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a217d8871ff92e0ad45001492875261e1}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!\-\_\-\-\_\-set\-Capacitor\-Per\-Unit\-\_\-\-\_\-@{\-\_\-\-\_\-set\-Capacitor\-Per\-Unit\-\_\-\-\_\-}} -\index{\-\_\-\-\_\-set\-Capacitor\-Per\-Unit\-\_\-\-\_\-@{\-\_\-\-\_\-set\-Capacitor\-Per\-Unit\-\_\-\-\_\-}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{\-\_\-\-\_\-set\-Capacitor\-Per\-Unit\-\_\-\-\_\-}]{\setlength{\rightskip}{0pt plus 5cm}def \-\_\-\-\_\-set\-Capacitor\-Per\-Unit\-\_\-\-\_\- ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{capacitor\-Type} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a217d8871ff92e0ad45001492875261e1} - - -Sets the area and perimeter capacitances as specified in 350 nm A\-M\-S technology and according to {\ttfamily capacitor\-Type} (M\-I\-M or P\-I\-P). - -\begin{DoxyReturn}{Returns} -a list containing the area and perimeter capacitances. -\end{DoxyReturn} -\begin{DoxyRemark}{Remarks} -An exception is raised if the entered capacitor type is unknown. -\end{DoxyRemark} - - -Referenced by Capacitor\-Unit.\-\_\-\-\_\-compute\-Cap\-Dim\-\_\-\-\_\-(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a914a2dadb095ebca95a60ee5c8ddd7a0}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!\-\_\-\-\_\-compute\-Cap\-Dim\-\_\-\-\_\-@{\-\_\-\-\_\-compute\-Cap\-Dim\-\_\-\-\_\-}} -\index{\-\_\-\-\_\-compute\-Cap\-Dim\-\_\-\-\_\-@{\-\_\-\-\_\-compute\-Cap\-Dim\-\_\-\-\_\-}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{\-\_\-\-\_\-compute\-Cap\-Dim\-\_\-\-\_\-}]{\setlength{\rightskip}{0pt plus 5cm}def \-\_\-\-\_\-compute\-Cap\-Dim\-\_\-\-\_\- ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{capacitance, } -\item[{}]{capacitor\-Type} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a914a2dadb095ebca95a60ee5c8ddd7a0} - - -Computes width and length of the capacitor. - -Given {\ttfamily capacitance} value as well as the permiter and area capacitances, a quadratic equation is solved where the unknown parameter is the width (also equivalent to the length). \begin{DoxyReturn}{Returns} -a dictionary containing width and length. -\end{DoxyReturn} -\begin{DoxyParagraph}{Remark\-:} -The capacitor is square. Thus, length and width are equal. -\end{DoxyParagraph} - - -References Capacitor\-Unit.\-\_\-\-\_\-set\-Capacitor\-Per\-Unit\-\_\-\-\_\-(). - - - -Referenced by Capacitor\-Stack.\-\_\-\-\_\-init\-\_\-\-\_\-(), and Capacitor\-Unit.\-\_\-\-\_\-init\-\_\-\-\_\-(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ac114a243874b413707b6fa7d30529d76}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!\-\_\-\-\_\-is\-Capacitor\-Unit\-O\-K\-\_\-\-\_\-@{\-\_\-\-\_\-is\-Capacitor\-Unit\-O\-K\-\_\-\-\_\-}} -\index{\-\_\-\-\_\-is\-Capacitor\-Unit\-O\-K\-\_\-\-\_\-@{\-\_\-\-\_\-is\-Capacitor\-Unit\-O\-K\-\_\-\-\_\-}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{\-\_\-\-\_\-is\-Capacitor\-Unit\-O\-K\-\_\-\-\_\-}]{\setlength{\rightskip}{0pt plus 5cm}def \-\_\-\-\_\-is\-Capacitor\-Unit\-O\-K\-\_\-\-\_\- ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{cap\-Dim} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ac114a243874b413707b6fa7d30529d76} - - -Checks if the computed capacitor dimensions exceed or are less than maximum and minimum limits, respectively, as specified in technology rules. - -\begin{DoxyReturn}{Returns} -{\ttfamily True} if all rules are respected. -\end{DoxyReturn} -\begin{DoxyParagraph}{Remark\-:} -Maximum poly2 layer dimensions for P\-I\-P capacitor are not specified in technology rules. Thus, only minimum limit condition is checked. -\end{DoxyParagraph} - - -References Capacitor\-Unit.\-capacitor\-Type, Capacitor\-Unit.\-get\-Maximum\-Cap\-Width(), and Capacitor\-Unit.\-get\-Minimum\-Cap\-Width(). - - - -Referenced by Capacitor\-Stack.\-\_\-\-\_\-init\-\_\-\-\_\-(), and Capacitor\-Unit.\-create(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a3b578035b1559391931dade7c2508105}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!set\-Rules@{set\-Rules}} -\index{set\-Rules@{set\-Rules}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{set\-Rules}]{\setlength{\rightskip}{0pt plus 5cm}def set\-Rules ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a3b578035b1559391931dade7c2508105} - - -Selects technological rules according to the capacitor type. - -\begin{DoxyReturn}{Returns} -a dictionary with rules labels as keys and rules as values. Example of technology rules are \-: -\begin{DoxyItemize} -\item minimum spacing between cuts or metals, -\item minimum width of a plate, a cut or a routing metal. -\item etc. Every rule takes two possible value according to the capacitor type (M\-I\-M or P\-I\-P). Therefore, dictionary keys are generic and its values are specific to the capacitor type. -\end{DoxyItemize} -\end{DoxyReturn} -\begin{DoxyParagraph}{Remark\-:} -An exception is raised if the entered capacitor type is unknown. -\end{DoxyParagraph} - - -References Capacitor\-Unit.\-capacitor\-Type, Capacitor\-Unit.\-hpitch, Capacitor\-Unit.\-is\-V\-H, Stack.\-is\-V\-H, Capacitor\-Unit.\-M\-E\-T\-A\-L2\-Pitch, Capacitor\-Unit.\-metal2\-Width, Capacitor\-Unit.\-M\-E\-T\-A\-L3\-Pitch, Capacitor\-Unit.\-metal3\-Width, Capacitor\-Unit.\-min\-Enclo\-\_\-bot\-Plate\-\_\-bot\-Plate\-Cut, Capacitor\-Unit.\-min\-Enclo\-\_\-bot\-Plate\-R\-Metal\-\_\-bot\-Plate\-Cut, Capacitor\-Unit.\-min\-Enclo\-\_\-routing\-Track\-Metal\-\_\-cut, Capacitor\-Unit.\-min\-Enclo\-\_\-top\-Plate\-\_\-top\-Plate\-Cut, Capacitor\-Unit.\-min\-Enclo\-\_\-top\-Plate\-R\-Metal\-\_\-top\-Plate\-Cut, Capacitor\-Unit.\-minheight\-\_\-top\-Platecut, Capacitor\-Unit.\-min\-Spacing\-\_\-bot\-Plate, Capacitor\-Unit.\-min\-Spacing\-\_\-bot\-Plate\-Cut\-\_\-top\-Plate, Capacitor\-Unit.\-min\-Spacing\-On\-Bot\-Plate\-\_\-cut, Capacitor\-Unit.\-min\-Spacing\-On\-Top\-Plate\-\_\-cut, Capacitor\-Unit.\-min\-Width\-\_\-bot\-Platecut, Capacitor\-Unit.\-min\-Width\-\_\-bot\-R\-Metal, Capacitor\-Unit.\-min\-Width\-\_\-routing\-Trackcut, Capacitor\-Unit.\-min\-Width\-\_\-top\-Plate, Capacitor\-Unit.\-min\-Width\-\_\-top\-Platecut, Capacitor\-Unit.\-min\-Width\-\_\-top\-R\-Metal, and Capacitor\-Unit.\-vpitch. - - - -Referenced by Capacitor\-Stack.\-create(), Capacitor\-Unit.\-create(), Rout\-Matched\-Capacitor.\-route(), and Vertical\-Routing\-Tracks.\-set\-Rules(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a127dcda66d458f9320e541649101607e}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Capacitor\-Type@{get\-Capacitor\-Type}} -\index{get\-Capacitor\-Type@{get\-Capacitor\-Type}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Capacitor\-Type}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Capacitor\-Type ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a127dcda66d458f9320e541649101607e} -\begin{DoxyReturn}{Returns} -capacitor type {\ttfamily 'M\-I\-M\-Cap'} or {\ttfamily 'P\-I\-P\-Cap'}. -\end{DoxyReturn} -\begin{DoxyRemark}{Remarks} -{\ttfamily \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a127dcda66d458f9320e541649101607e}{get\-Capacitor\-Type()}} is especially useful when an instance of {\ttfamily \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit}{Capacitor\-Unit}} class is called in another classes instances to identify the capacitor's type. -\end{DoxyRemark} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a7afefaf3a15d637ffe979bc54d57c6c2}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Maximum\-Cap\-Width@{get\-Maximum\-Cap\-Width}} -\index{get\-Maximum\-Cap\-Width@{get\-Maximum\-Cap\-Width}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Maximum\-Cap\-Width}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Maximum\-Cap\-Width ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a7afefaf3a15d637ffe979bc54d57c6c2} - - -maximum size of capacitor's top plate. - -{\ttfamily \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a7afefaf3a15d637ffe979bc54d57c6c2}{get\-Maximum\-Cap\-Width()}} is called to check if capacitor dimensions are within acceptable technological limits. An exception is raised if the entered capacitor type is unknown. \begin{DoxyRemark}{Remarks} -1. This function is especially usefull in drawing the layout of a unity capacitor, where it is important to garantee that the capacitor size does not exeed the maximum possible value. It is also useful when drawing a matrix of capacitors to make sure that also the unity capacitor respects the maximal values specified. - -2. The maximum value of the poly2 size in P\-I\-P capacitor is not specified. Thus, it is not considered in {\ttfamily \hyperlink{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a7afefaf3a15d637ffe979bc54d57c6c2}{get\-Maximum\-Cap\-Width()}} -\end{DoxyRemark} - - -References Capacitor\-Unit.\-capacitor\-Type. - - - -Referenced by Capacitor\-Unit.\-\_\-\-\_\-is\-Capacitor\-Unit\-O\-K\-\_\-\-\_\-(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aacb6369181aa03823cb1ce42adb0ee25}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Minimum\-Cap\-Width@{get\-Minimum\-Cap\-Width}} -\index{get\-Minimum\-Cap\-Width@{get\-Minimum\-Cap\-Width}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Minimum\-Cap\-Width}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Minimum\-Cap\-Width ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aacb6369181aa03823cb1ce42adb0ee25} -\begin{DoxyReturn}{Returns} -The minimum size of the capacitor's top plate. An exception is raised if the entered capacitor type is unknown. -\end{DoxyReturn} -\begin{DoxyRemark}{Remarks} -This function is especially usefull in drawing the layout of a matrix of capacitors where it is important to ensure that the unity capacitor respects the minimal values specified. - -An exception is raised if the entered capacitor type is unknown. -\end{DoxyRemark} - - -References Capacitor\-Unit.\-capacitor\-Type. - - - -Referenced by Capacitor\-Unit.\-\_\-\-\_\-is\-Capacitor\-Unit\-O\-K\-\_\-\-\_\-(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a7be694eb909dc1e49326e3b5dd1e6887}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Layers@{get\-Layers}} -\index{get\-Layers@{get\-Layers}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Layers}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Layers ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a7be694eb909dc1e49326e3b5dd1e6887} - - -Loads the technology file then extracts the adequate layers according to the capacitor type (M\-I\-M or P\-I\-P). - -\begin{DoxyReturn}{Returns} -a dictionary containing the layer labels as attributes and its values. -\end{DoxyReturn} -\begin{DoxyRemark}{Remarks} -An exception is raised if the entered capacitor type is unknown. -\end{DoxyRemark} - - -References Capacitor\-Unit.\-capacitor\-Type. - - - -Referenced by Capacitor\-Unit.\-create(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a5b7ef0221e471e99fa7f0a87a28ba1ea}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!create@{create}} -\index{create@{create}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{create}]{\setlength{\rightskip}{0pt plus 5cm}def create ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{t, } -\item[{}]{b, } -\item[{}]{bb\-Mode = {\ttfamily False}, } -\item[{}]{v\-Enclosure\-\_\-bot\-Plate\-\_\-abt\-Box = {\ttfamily None}, } -\item[{}]{h\-Enclosure\-\_\-bot\-Plate\-\_\-abt\-Box = {\ttfamily None}} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a5b7ef0221e471e99fa7f0a87a28ba1ea} - - -When bonding box mode is activated, the function draws all layout physical layers of the capacitor after checking its dimensions. - -All functions are excecuted in a new Update Session. In the contrary, only an exact estimation of layout dimensions is given. An error is raised when dimensions reach technological limits for M\-I\-M and P\-I\-P capacitors or when {\ttfamily bb\-Mode} parameters is other than {\ttfamily True} or {\ttfamily False}. - - -\begin{DoxyParams}{Parameters} -{\em (} & t , b ) nets of top and bottom plates, respectively \\ -\hline -{\em bb\-Mode} & activates bonding box dimensions computing when set to {\ttfamily True} \\ -\hline -\end{DoxyParams} - - -References Capacitor\-Unit.\-\_\-\-\_\-is\-Capacitor\-Unit\-O\-K\-\_\-\-\_\-(), Capacitor\-Unit.\-abutment\-Box\-Dict, Capacitor\-Unit.\-cap\-Dim, Capacitor\-Unit.\-compute\-Dimensions(), Stack.\-compute\-Dimensions(), Capacitor\-Unit.\-draw\-Abutment\-Box(), Capacitor\-Unit.\-draw\-Capacitor(), Technology.\-get\-Layers(), Capacitor\-Unit.\-get\-Layers(), and Capacitor\-Unit.\-set\-Rules(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ae2ec4683c7f6c30fbb1687934673410c}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!draw\-Capacitor@{draw\-Capacitor}} -\index{draw\-Capacitor@{draw\-Capacitor}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{draw\-Capacitor}]{\setlength{\rightskip}{0pt plus 5cm}def draw\-Capacitor ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{layer\-Dict, } -\item[{}]{t, } -\item[{}]{b} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ae2ec4683c7f6c30fbb1687934673410c} - - -Draws all layout physicial layers of the capacitor. - - -\begin{DoxyParams}{Parameters} -{\em layer\-Dict} & a dictionary containing a description of the required physical layers according to capacitor type \\ -\hline -{\em (} & t , b ) nets of top and bottom plates, respectively \\ -\hline -\end{DoxyParams} - - -References Capacitor\-Unit.\-bottom\-Plate\-Box, Capacitor\-Unit.\-bottom\-Plate\-Box\-Dict, Capacitor\-Unit.\-draw\-Bottom\-Plate\-Cut(), Capacitor\-Unit.\-draw\-One\-Plate(), Capacitor\-Unit.\-draw\-Routing\-Layers(), Capacitor\-Unit.\-draw\-Top\-Plate\-Cut(), Capacitor\-Unit.\-top\-Plate\-Box, and Capacitor\-Unit.\-top\-Plate\-Box\-Dict. - - - -Referenced by Capacitor\-Unit.\-create(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a8f71111f71d084f05742fadf134cb87e}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!compute\-Bottom\-Plate\-Cuts@{compute\-Bottom\-Plate\-Cuts}} -\index{compute\-Bottom\-Plate\-Cuts@{compute\-Bottom\-Plate\-Cuts}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{compute\-Bottom\-Plate\-Cuts}]{\setlength{\rightskip}{0pt plus 5cm}def compute\-Bottom\-Plate\-Cuts ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a8f71111f71d084f05742fadf134cb87e} - - -Computes needed parameters to draw bottom plate cuts in its exact position, including \-: - - -\begin{DoxyItemize} -\item maximum number of cuts to draw on both sides of bottom plate, -\item adjusted enclosure of -\item abcissas of the two bottom cuts on left and right sides of bottom plate, -\item ordinate of the same two cuts. -\end{DoxyItemize} - -Given parameters described above, it is possible to draw the entire lines of cuts on both sides of bottom plate using {\ttfamily cut\-Line} function. - -References Capacitor\-Unit.\-bottom\-Cut\-Line\-Number, Capacitor\-Unit.\-bottom\-Plate\-Box\-Dict, Capacitor\-Unit.\-cut\-Left\-Line\-Dict, Capacitor\-Unit.\-cut\-Max\-Number(), Capacitor\-Unit.\-cut\-Right\-Line\-Dict, Capacitor\-Unit.\-min\-Enclo\-\_\-bot\-Plate\-\_\-bot\-Plate\-Cut, Capacitor\-Unit.\-minheight\-\_\-top\-Platecut, Capacitor\-Unit.\-min\-Spacing\-\_\-bot\-Plate\-Cut\-\_\-top\-Plate, Capacitor\-Unit.\-min\-Spacing\-On\-Bot\-Plate\-\_\-cut, Capacitor\-Unit.\-min\-Width\-\_\-top\-Platecut, and Capacitor\-Unit.\-top\-Plate\-Box\-Dict. - - - -Referenced by Capacitor\-Unit.\-draw\-Abutment\-Box(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aceb634d48d79f2079c690297c820da0b}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!compute\-Top\-Plate\-Cuts@{compute\-Top\-Plate\-Cuts}} -\index{compute\-Top\-Plate\-Cuts@{compute\-Top\-Plate\-Cuts}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{compute\-Top\-Plate\-Cuts}]{\setlength{\rightskip}{0pt plus 5cm}def compute\-Top\-Plate\-Cuts ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aceb634d48d79f2079c690297c820da0b} - - -Computes needed parameters to draw top plate cuts in its exact position, including \-: - - -\begin{DoxyItemize} -\item maximum number of cuts to draw on both sides of top plate, -\item adjusted enclosure of -\item abcissas of the two top cuts on left and right sides of top plate, -\item ordinate of the same two cuts. -\end{DoxyItemize} - -Given parameters described above, it is possible to draw the entire lines of cuts on both sides of bottom plate using {\ttfamily cut\-Line} function. - -References Capacitor\-Unit.\-abutment\-Box\-Dict, Capacitor\-Unit.\-bottom\-Plate\-Box\-Dict, Capacitor\-Unit.\-bottom\-Plate\-R\-Layer\-Dict, Capacitor\-Unit.\-capacitor\-Type, Capacitor\-Unit.\-cut2\-Matrix\-Dict, Capacitor\-Unit.\-cut\-Left\-Line\-Dict, Capacitor\-Unit.\-cut\-Max\-Number(), Capacitor\-Unit.\-cut\-Right\-Line\-Dict, Capacitor\-Unit.\-enclosure\-\_\-bot\-Plate\-\_\-top\-Plate, Capacitor\-Unit.\-h\-Enclosure\-\_\-bot\-Plate\-\_\-abt\-Box, Capacitor\-Unit.\-min\-Enclo\-\_\-bot\-Plate\-\_\-bot\-Plate\-Cut, Capacitor\-Unit.\-min\-Enclo\-\_\-bot\-Plate\-R\-Metal\-\_\-bot\-Plate\-Cut, Capacitor\-Unit.\-min\-Enclo\-\_\-routing\-Track\-Metal\-\_\-cut, Capacitor\-Unit.\-min\-Enclo\-\_\-top\-Plate\-\_\-top\-Plate\-Cut, Capacitor\-Unit.\-min\-Enclo\-\_\-top\-Plate\-R\-Metal\-\_\-top\-Plate\-Cut, Capacitor\-Unit.\-minheight\-\_\-top\-Platecut, Capacitor\-Unit.\-min\-Spacing\-\_\-bot\-Plate, Capacitor\-Unit.\-min\-Spacing\-\_\-bot\-Plate\-Cut\-\_\-top\-Plate, Capacitor\-Unit.\-min\-Spacing\-On\-Top\-Plate\-\_\-cut, Capacitor\-Unit.\-min\-Width\-\_\-bot\-Platecut, Capacitor\-Unit.\-min\-Width\-\_\-bot\-R\-Metal, Capacitor\-Unit.\-min\-Width\-\_\-routing\-Trackcut, Capacitor\-Unit.\-min\-Width\-\_\-top\-Platecut, Capacitor\-Unit.\-set\-Bottom\-Plate\-Abt\-Box\-Enclosure(), Capacitor\-Unit.\-top\-Cut\-Line\-Dict, Capacitor\-Unit.\-top\-Cut\-Line\-Number, Capacitor\-Unit.\-top\-Plate\-Box\-Dict, Capacitor\-Unit.\-top\-Plate\-R\-Layer\-Dict, and Capacitor\-Unit.\-v\-Enclosure\-\_\-bot\-Plate\-\_\-abt\-Box. - - - -Referenced by Capacitor\-Unit.\-draw\-Abutment\-Box(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ac5cd73be473bc321a29a75311f808835}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!draw\-Abutment\-Box@{draw\-Abutment\-Box}} -\index{draw\-Abutment\-Box@{draw\-Abutment\-Box}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{draw\-Abutment\-Box}]{\setlength{\rightskip}{0pt plus 5cm}def draw\-Abutment\-Box ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ac5cd73be473bc321a29a75311f808835} - - -Draws the abutment box of the capacitor in position {\ttfamily $<$}(abutment\-Box\-X\-Min, abutment\-Box\-Y\-Min)$>$. - -First, the minimum enclosure of the top plate inside the bottom plate is computed. Second, using this parameters as well as the capacitor dimensions, the width and height of the abutment box are computed. The box is finally drawn. - -References Capacitor\-Unit.\-abutment\-Box, Capacitor\-Unit.\-abutment\-Box\-Dict, Capacitor\-Unit.\-bottom\-Plate\-Box\-Dict, Capacitor\-Unit.\-compute\-Abutment\-Box\-Dimensions(), Capacitor\-Unit.\-compute\-Bottom\-Plate\-Cuts(), Capacitor\-Unit.\-compute\-One\-Plate\-Box\-Dimensions(), Capacitor\-Unit.\-compute\-Routing\-Layers\-Dimensions(), Capacitor\-Unit.\-compute\-Top\-Plate\-Cuts(), Capacitor\-Unit.\-enclosure\-\_\-bot\-Plate\-\_\-top\-Plate, Capacitor\-Unit.\-h\-Enclosure\-\_\-bot\-Plate\-\_\-abt\-Box, Capacitor\-Unit.\-top\-Plate\-Box\-Dict, and Capacitor\-Unit.\-v\-Enclosure\-\_\-bot\-Plate\-\_\-abt\-Box. - - - -Referenced by Capacitor\-Stack.\-create(), and Capacitor\-Unit.\-create(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a7b4116e4696b869f462d86b1ddf00246}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!draw\-One\-Plate@{draw\-One\-Plate}} -\index{draw\-One\-Plate@{draw\-One\-Plate}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{draw\-One\-Plate}]{\setlength{\rightskip}{0pt plus 5cm}def draw\-One\-Plate ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{layer, } -\item[{}]{net, } -\item[{}]{box\-Dimensions} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a7b4116e4696b869f462d86b1ddf00246} - - -Draws the top or bottom plate through inflation of the Box under it. - -These boxes are the abutment box in the case of the bottom plate and the bottom plate's box in the case of the top plate. This function also creates a a net for the drawn plate and sets it as external. \begin{DoxyReturn}{Returns} -The drawn box. -\end{DoxyReturn} - - -Referenced by Capacitor\-Unit.\-draw\-Capacitor(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a1a998a3072560eaee998c9e5531a5f5b}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!draw\-Bottom\-Plate\-Cut@{draw\-Bottom\-Plate\-Cut}} -\index{draw\-Bottom\-Plate\-Cut@{draw\-Bottom\-Plate\-Cut}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{draw\-Bottom\-Plate\-Cut}]{\setlength{\rightskip}{0pt plus 5cm}def draw\-Bottom\-Plate\-Cut ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{layer, } -\item[{}]{b} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a1a998a3072560eaee998c9e5531a5f5b} - - -Draws the required cuts to connect the bottom plate. - -First, the maximal possible number of cuts that can be drawn is computed. Second, using the computed number, the enclosure of this cuts in the bottom plate's layer is adjusted while the minimal enclosure is respected. Third, the relative positions of the cuts on both sides of the plate are computed. Finally, two vertical lines of cuts are drawns. \begin{DoxyParagraph}{Remark\-:} -The relative positions describe the cordinates of the first bottom cut in every line of cuts. Then, knowing the spacing and width specifications of these cuts the rest of the line is easilly constructed. -\end{DoxyParagraph} - - -References Capacitor\-Unit.\-bottom\-Cut\-Line\-Number, Capacitor\-Unit.\-cut\-Left\-Line\-Dict, Capacitor\-Unit.\-cut\-Line(), Capacitor\-Unit.\-cut\-Right\-Line\-Dict, Capacitor\-Unit.\-minheight\-\_\-top\-Platecut, Capacitor\-Unit.\-min\-Spacing\-On\-Bot\-Plate\-\_\-cut, and Capacitor\-Unit.\-min\-Width\-\_\-bot\-Platecut. - - - -Referenced by Capacitor\-Unit.\-draw\-Capacitor(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a8d4cd239412ffde81f0cda52123b9c1d}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!draw\-Top\-Plate\-Cut@{draw\-Top\-Plate\-Cut}} -\index{draw\-Top\-Plate\-Cut@{draw\-Top\-Plate\-Cut}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{draw\-Top\-Plate\-Cut}]{\setlength{\rightskip}{0pt plus 5cm}def draw\-Top\-Plate\-Cut ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{layer, } -\item[{}]{t} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a8d4cd239412ffde81f0cda52123b9c1d} - - -Draws the top plate's cuts after computing the maximal number of cuts that can be placed and its exact enclosure in the top plate. - - - -References Capacitor\-Unit.\-capacitor\-Type, Capacitor\-Unit.\-cut2\-Matrix\-Dict, Capacitor\-Unit.\-cut\-Line(), Capacitor\-Unit.\-cut\-Matrix(), Capacitor\-Unit.\-minheight\-\_\-top\-Platecut, Capacitor\-Unit.\-min\-Spacing\-On\-Top\-Plate\-\_\-cut, Capacitor\-Unit.\-min\-Width\-\_\-top\-Platecut, Capacitor\-Unit.\-top\-Cut\-Line\-Dict, and Capacitor\-Unit.\-top\-Cut\-Line\-Number. - - - -Referenced by Capacitor\-Unit.\-draw\-Capacitor(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a444cc6c0ee175ba22b5092d0706bc0d6}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!draw\-Routing\-Layers@{draw\-Routing\-Layers}} -\index{draw\-Routing\-Layers@{draw\-Routing\-Layers}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{draw\-Routing\-Layers}]{\setlength{\rightskip}{0pt plus 5cm}def draw\-Routing\-Layers ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{bottom\-Plate\-Layer, } -\item[{}]{top\-Plate\-Layer, } -\item[{}]{t, } -\item[{}]{b} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a444cc6c0ee175ba22b5092d0706bc0d6} - - -Draws the routing layers of both bottom and top plates after computing widths and the exact position of these layers. - -Also computes positions if rlayers that are crucial for routing. - -References Capacitor\-Unit.\-bottom\-Plate\-R\-Layer\-Dict, Capacitor\-Unit.\-cut\-Left\-Line\-Dict, Capacitor\-Unit.\-cut\-Right\-Line\-Dict, and Capacitor\-Unit.\-top\-Plate\-R\-Layer\-Dict. - - - -Referenced by Capacitor\-Unit.\-draw\-Capacitor(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a5c03a894501e69f2e6a6d40e93df8ef2}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!cut\-Max\-Number@{cut\-Max\-Number}} -\index{cut\-Max\-Number@{cut\-Max\-Number}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{cut\-Max\-Number}]{\setlength{\rightskip}{0pt plus 5cm}def cut\-Max\-Number ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{width\-\_\-layer, } -\item[{}]{width\-\_\-cut, } -\item[{}]{spacing\-\_\-cut, } -\item[{}]{enclosure\-\_\-cut} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a5c03a894501e69f2e6a6d40e93df8ef2} - - -Computes the maximal number of cuts to be placed on a layer of width {\ttfamily width\-\_\-layer} considering specifications such as the spacing between the cuts, its width and its enclosure in the layer. - - - -Referenced by Capacitor\-Unit.\-compute\-Bottom\-Plate\-Cuts(), and Capacitor\-Unit.\-compute\-Top\-Plate\-Cuts(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a95ebae95cc0be711de5adbb1faa85f98}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!cut\-Line@{cut\-Line}} -\index{cut\-Line@{cut\-Line}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{cut\-Line}]{\setlength{\rightskip}{0pt plus 5cm}def cut\-Line ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{net, } -\item[{}]{layer, } -\item[{}]{first\-Cut\-X\-Center, } -\item[{}]{first\-Cut\-Y\-Center, } -\item[{}]{width\-\_\-cut, } -\item[{}]{height\-\_\-cut, } -\item[{}]{spacing\-\_\-cut, } -\item[{}]{cut\-Number, } -\item[{}]{direction} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a95ebae95cc0be711de5adbb1faa85f98} - - -Creates a horizontal or vertical line of contacts according to the specified direction. - - - -Referenced by Capacitor\-Unit.\-cut\-Matrix(), Capacitor\-Unit.\-draw\-Bottom\-Plate\-Cut(), and Capacitor\-Unit.\-draw\-Top\-Plate\-Cut(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a4b8fe45cf122a2682cd8120bcbc5e5fd}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!cut\-Matrix@{cut\-Matrix}} -\index{cut\-Matrix@{cut\-Matrix}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{cut\-Matrix}]{\setlength{\rightskip}{0pt plus 5cm}def cut\-Matrix ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{net, } -\item[{}]{layer, } -\item[{}]{first\-Cut\-X\-Center, } -\item[{}]{first\-Cut\-Y\-Center, } -\item[{}]{width\-\_\-cut, } -\item[{}]{height\-\_\-cut, } -\item[{}]{spacing\-\_\-cut, } -\item[{}]{cut\-Column\-Number, } -\item[{}]{cut\-Row\-Number} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a4b8fe45cf122a2682cd8120bcbc5e5fd} - - -Creates a matrix of cuts by vertically stacking horizontal lines of identical cuts. - - -\begin{DoxyParams}{Parameters} -{\em net} & net to which the cuts belong \\ -\hline -{\em layer} & cuts physical layer \\ -\hline -{\em first\-Cut\-X\-Center} & center's abcissa of the bottom left cut ( that is the first cut to be drawn in the matrix ) \\ -\hline -{\em first\-Cut\-Y\-Center} & center's abcissa of the bottom left cut \\ -\hline -{\em (width\-\_\-cut,height\-\_\-cut,spacing\-\_\-cut)} & cuts dimenions \\ -\hline -{\em (cut\-Column\-Number,cut\-Row\-Number)} & matrix dimensions\\ -\hline -\end{DoxyParams} -\begin{DoxyRemark}{Remarks} -The matrix can have any dimensions zero or negative one. -\end{DoxyRemark} - - -References Capacitor\-Unit.\-cut\-Line(). - - - -Referenced by Capacitor\-Unit.\-draw\-Top\-Plate\-Cut(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a876d31edaaabe0716d6fbe6f6c0c7b75}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Bottom\-Plate\-Y\-Max@{get\-Bottom\-Plate\-Y\-Max}} -\index{get\-Bottom\-Plate\-Y\-Max@{get\-Bottom\-Plate\-Y\-Max}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Bottom\-Plate\-Y\-Max}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Bottom\-Plate\-Y\-Max ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a876d31edaaabe0716d6fbe6f6c0c7b75} -\begin{DoxyReturn}{Returns} -the ordinate of the bottom plate's highest end-\/point ( that is equivalent to {\ttfamily dy\-Source} of the bottom plate's box ) . -\end{DoxyReturn} - - -References Capacitor\-Unit.\-bottom\-Plate\-Box\-Dict. - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ae461baa28fdfa09bad07b3f1073a46b7}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Bottom\-Plate\-Left\-Cut\-X\-Min@{get\-Bottom\-Plate\-Left\-Cut\-X\-Min}} -\index{get\-Bottom\-Plate\-Left\-Cut\-X\-Min@{get\-Bottom\-Plate\-Left\-Cut\-X\-Min}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Bottom\-Plate\-Left\-Cut\-X\-Min}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Bottom\-Plate\-Left\-Cut\-X\-Min ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ae461baa28fdfa09bad07b3f1073a46b7} -\begin{DoxyReturn}{Returns} -the abcissa of the bottom plate's left line of cuts. -\end{DoxyReturn} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aae1849792395fccc12e921450a29980b}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Bottom\-Plate\-Left\-Cut\-Y\-Min@{get\-Bottom\-Plate\-Left\-Cut\-Y\-Min}} -\index{get\-Bottom\-Plate\-Left\-Cut\-Y\-Min@{get\-Bottom\-Plate\-Left\-Cut\-Y\-Min}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Bottom\-Plate\-Left\-Cut\-Y\-Min}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Bottom\-Plate\-Left\-Cut\-Y\-Min ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aae1849792395fccc12e921450a29980b} -\begin{DoxyReturn}{Returns} -the ordinate of the first ( or bottom) cut in the left line of cuts on the bottom plate. -\end{DoxyReturn} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a2f7b75e47a238defa63e04c75e0be016}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Bottom\-Plate\-Left\-Cut\-Y\-Max@{get\-Bottom\-Plate\-Left\-Cut\-Y\-Max}} -\index{get\-Bottom\-Plate\-Left\-Cut\-Y\-Max@{get\-Bottom\-Plate\-Left\-Cut\-Y\-Max}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Bottom\-Plate\-Left\-Cut\-Y\-Max}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Bottom\-Plate\-Left\-Cut\-Y\-Max ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a2f7b75e47a238defa63e04c75e0be016} -\begin{DoxyReturn}{Returns} -the ordinate of the highest cut of the bottom plate's left line of cuts. -\end{DoxyReturn} - - -References Capacitor\-Unit.\-bottom\-Cut\-Line\-Number, Capacitor\-Unit.\-min\-Spacing\-On\-Bot\-Plate\-\_\-cut, and Capacitor\-Unit.\-min\-Width\-\_\-bot\-Platecut. - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a9e59fed4e9829bac60edbd38195cdd90}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Bottom\-Plate\-Right\-Cut\-X\-Min@{get\-Bottom\-Plate\-Right\-Cut\-X\-Min}} -\index{get\-Bottom\-Plate\-Right\-Cut\-X\-Min@{get\-Bottom\-Plate\-Right\-Cut\-X\-Min}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Bottom\-Plate\-Right\-Cut\-X\-Min}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Bottom\-Plate\-Right\-Cut\-X\-Min ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a9e59fed4e9829bac60edbd38195cdd90} -\begin{DoxyReturn}{Returns} -the absissa of the bottom plate's right line of cuts. -\end{DoxyReturn} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a0e362c0f80ab5a70fa3e4139d0009ef1}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Bottom\-Plate\-Right\-Cut\-Y\-Min@{get\-Bottom\-Plate\-Right\-Cut\-Y\-Min}} -\index{get\-Bottom\-Plate\-Right\-Cut\-Y\-Min@{get\-Bottom\-Plate\-Right\-Cut\-Y\-Min}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Bottom\-Plate\-Right\-Cut\-Y\-Min}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Bottom\-Plate\-Right\-Cut\-Y\-Min ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a0e362c0f80ab5a70fa3e4139d0009ef1} -\begin{DoxyReturn}{Returns} -the ordinate of the first ( or bottom) cut in the right line of cuts on the bottom plate. -\end{DoxyReturn} - - -Referenced by Capacitor\-Unit.\-get\-Bottom\-Plate\-Right\-Cut\-Y\-Center(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ae31425a5f9b3d7a0829c1abc454e2834}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Bottom\-Plate\-Right\-Cut\-Y\-Max@{get\-Bottom\-Plate\-Right\-Cut\-Y\-Max}} -\index{get\-Bottom\-Plate\-Right\-Cut\-Y\-Max@{get\-Bottom\-Plate\-Right\-Cut\-Y\-Max}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Bottom\-Plate\-Right\-Cut\-Y\-Max}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Bottom\-Plate\-Right\-Cut\-Y\-Max ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ae31425a5f9b3d7a0829c1abc454e2834} -\begin{DoxyReturn}{Returns} -the ordinate of the highest ( or top) cut in the right line of cuts on the bottom plate. -\end{DoxyReturn} - - -References Capacitor\-Unit.\-bottom\-Cut\-Line\-Number, Capacitor\-Unit.\-min\-Spacing\-On\-Bot\-Plate\-\_\-cut, and Capacitor\-Unit.\-min\-Width\-\_\-bot\-Platecut. - - - -Referenced by Capacitor\-Unit.\-get\-Bottom\-Plate\-Right\-Cut\-Y\-Center(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ae3887820ee80da10f77b451e5f068635}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Bot\-Plate\-Left\-R\-Layer\-X\-Max@{get\-Bot\-Plate\-Left\-R\-Layer\-X\-Max}} -\index{get\-Bot\-Plate\-Left\-R\-Layer\-X\-Max@{get\-Bot\-Plate\-Left\-R\-Layer\-X\-Max}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Bot\-Plate\-Left\-R\-Layer\-X\-Max}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Bot\-Plate\-Left\-R\-Layer\-X\-Max ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_ae3887820ee80da10f77b451e5f068635} -\begin{DoxyReturn}{Returns} -the center's ordinate of the bottom plate's left cut (the cut that is the first one in the line). -\end{DoxyReturn} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a2d9186515736c9fd74725eca251f6e2b}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Bottom\-Plate\-Right\-Cut\-Y\-Center@{get\-Bottom\-Plate\-Right\-Cut\-Y\-Center}} -\index{get\-Bottom\-Plate\-Right\-Cut\-Y\-Center@{get\-Bottom\-Plate\-Right\-Cut\-Y\-Center}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Bottom\-Plate\-Right\-Cut\-Y\-Center}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Bottom\-Plate\-Right\-Cut\-Y\-Center ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a2d9186515736c9fd74725eca251f6e2b} -\begin{DoxyReturn}{Returns} -the position of the bottom plate's right cuts on the horitontal axis (also applicable to left cuts). -\end{DoxyReturn} - - -References Capacitor\-Unit.\-get\-Bottom\-Plate\-Right\-Cut\-Y\-Max(), and Capacitor\-Unit.\-get\-Bottom\-Plate\-Right\-Cut\-Y\-Min(). - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a52e8ea7265119216e234eab32bc542ef}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Bot\-Plate\-Left\-R\-Layer\-X\-Min@{get\-Bot\-Plate\-Left\-R\-Layer\-X\-Min}} -\index{get\-Bot\-Plate\-Left\-R\-Layer\-X\-Min@{get\-Bot\-Plate\-Left\-R\-Layer\-X\-Min}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Bot\-Plate\-Left\-R\-Layer\-X\-Min}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Bot\-Plate\-Left\-R\-Layer\-X\-Min ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a52e8ea7265119216e234eab32bc542ef} -\begin{DoxyReturn}{Returns} -the position of the bottom plate's left cuts on the horitontal axis. -\end{DoxyReturn} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a2f87580a615f6b0450d43a032adf81d5}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Bot\-Plate\-R\-Layer\-Y\-Min@{get\-Bot\-Plate\-R\-Layer\-Y\-Min}} -\index{get\-Bot\-Plate\-R\-Layer\-Y\-Min@{get\-Bot\-Plate\-R\-Layer\-Y\-Min}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Bot\-Plate\-R\-Layer\-Y\-Min}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Bot\-Plate\-R\-Layer\-Y\-Min ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a2f87580a615f6b0450d43a032adf81d5} -\begin{DoxyReturn}{Returns} -the position of bottom plate's left cuts on the horitontal axis. -\end{DoxyReturn} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aa6cb9e5f6ba2d4e4ce5f63ca1d785e7e}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Bot\-Plate\-R\-Layer\-Y\-Max@{get\-Bot\-Plate\-R\-Layer\-Y\-Max}} -\index{get\-Bot\-Plate\-R\-Layer\-Y\-Max@{get\-Bot\-Plate\-R\-Layer\-Y\-Max}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Bot\-Plate\-R\-Layer\-Y\-Max}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Bot\-Plate\-R\-Layer\-Y\-Max ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aa6cb9e5f6ba2d4e4ce5f63ca1d785e7e} -\begin{DoxyReturn}{Returns} -the position of bottom plate's left cuts on the horitontal axis. -\end{DoxyReturn} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a3463504463c87fb7aab28ca04597c169}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Bot\-Plate\-R\-Layer\-Width@{get\-Bot\-Plate\-R\-Layer\-Width}} -\index{get\-Bot\-Plate\-R\-Layer\-Width@{get\-Bot\-Plate\-R\-Layer\-Width}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Bot\-Plate\-R\-Layer\-Width}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Bot\-Plate\-R\-Layer\-Width ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a3463504463c87fb7aab28ca04597c169} -\begin{DoxyReturn}{Returns} -the position of bottom plate's left cuts on the horitontal axis. -\end{DoxyReturn} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aff2f6d078abdcf0d679aa9b697928f34}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Bot\-Plate\-Right\-R\-Layer\-X\-Center@{get\-Bot\-Plate\-Right\-R\-Layer\-X\-Center}} -\index{get\-Bot\-Plate\-Right\-R\-Layer\-X\-Center@{get\-Bot\-Plate\-Right\-R\-Layer\-X\-Center}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Bot\-Plate\-Right\-R\-Layer\-X\-Center}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Bot\-Plate\-Right\-R\-Layer\-X\-Center ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aff2f6d078abdcf0d679aa9b697928f34} -\begin{DoxyReturn}{Returns} -the position of bottom plate's left cuts on the horitontal axis. -\end{DoxyReturn} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a7440876afb0ff33ba0ee5cea4e9e0aed}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Bot\-Plate\-Left\-R\-Layer\-X\-Center@{get\-Bot\-Plate\-Left\-R\-Layer\-X\-Center}} -\index{get\-Bot\-Plate\-Left\-R\-Layer\-X\-Center@{get\-Bot\-Plate\-Left\-R\-Layer\-X\-Center}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Bot\-Plate\-Left\-R\-Layer\-X\-Center}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Bot\-Plate\-Left\-R\-Layer\-X\-Center ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a7440876afb0ff33ba0ee5cea4e9e0aed} -\begin{DoxyReturn}{Returns} -the position of bottom plate's left cuts on the horitontal axis. -\end{DoxyReturn} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a836a7c11713aa3a08504a498b90fb5ee}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Top\-Plate\-R\-Layer\-Y\-Min@{get\-Top\-Plate\-R\-Layer\-Y\-Min}} -\index{get\-Top\-Plate\-R\-Layer\-Y\-Min@{get\-Top\-Plate\-R\-Layer\-Y\-Min}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Top\-Plate\-R\-Layer\-Y\-Min}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Top\-Plate\-R\-Layer\-Y\-Min ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a836a7c11713aa3a08504a498b90fb5ee} -\begin{DoxyReturn}{Returns} -the ordinate of the bottom end points of the top plate routing layer. -\end{DoxyReturn} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aea137748a99552369414fc5ffec3a41d}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Top\-Plate\-R\-Layer\-Y\-Max@{get\-Top\-Plate\-R\-Layer\-Y\-Max}} -\index{get\-Top\-Plate\-R\-Layer\-Y\-Max@{get\-Top\-Plate\-R\-Layer\-Y\-Max}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Top\-Plate\-R\-Layer\-Y\-Max}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Top\-Plate\-R\-Layer\-Y\-Max ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_aea137748a99552369414fc5ffec3a41d} -\begin{DoxyReturn}{Returns} -the ordinate of the higher end points of the top plate routing layer. -\end{DoxyReturn} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a9c1452c170eeb58d060bb5fe72fae5a9}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Top\-Plate\-R\-Layer\-Width@{get\-Top\-Plate\-R\-Layer\-Width}} -\index{get\-Top\-Plate\-R\-Layer\-Width@{get\-Top\-Plate\-R\-Layer\-Width}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Top\-Plate\-R\-Layer\-Width}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Top\-Plate\-R\-Layer\-Width ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a9c1452c170eeb58d060bb5fe72fae5a9} -\begin{DoxyReturn}{Returns} -the width of top plate's routing layer. -\end{DoxyReturn} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a295a807958d27c156f87102762d353d6}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Top\-Plate\-R\-Layer\-X\-Center@{get\-Top\-Plate\-R\-Layer\-X\-Center}} -\index{get\-Top\-Plate\-R\-Layer\-X\-Center@{get\-Top\-Plate\-R\-Layer\-X\-Center}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Top\-Plate\-R\-Layer\-X\-Center}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Top\-Plate\-R\-Layer\-X\-Center ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a295a807958d27c156f87102762d353d6} -\begin{DoxyReturn}{Returns} -the center's abcissa of the bottom plate routing layer. -\end{DoxyReturn} -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a28208011c71e1712625c1148a67d943c}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Top\-Plate\-R\-Layer\-X\-Min@{get\-Top\-Plate\-R\-Layer\-X\-Min}} -\index{get\-Top\-Plate\-R\-Layer\-X\-Min@{get\-Top\-Plate\-R\-Layer\-X\-Min}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Top\-Plate\-R\-Layer\-X\-Min}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Top\-Plate\-R\-Layer\-X\-Min ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a28208011c71e1712625c1148a67d943c} -\begin{DoxyReturn}{Returns} -the origin (bottom-\/left end point) abcissa of the top plate routing layers. -\end{DoxyReturn} - - -References Capacitor\-Unit.\-top\-Plate\-R\-Layer\-Dict. - -\hypertarget{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a9788696eb8f1cffde53de39c7f2ffcaa}{\index{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}!get\-Top\-Plate\-R\-Layer\-X\-Max@{get\-Top\-Plate\-R\-Layer\-X\-Max}} -\index{get\-Top\-Plate\-R\-Layer\-X\-Max@{get\-Top\-Plate\-R\-Layer\-X\-Max}!python::CapacitorUnit::CapacitorUnit@{python\-::\-Capacitor\-Unit\-::\-Capacitor\-Unit}} -\subsubsection[{get\-Top\-Plate\-R\-Layer\-X\-Max}]{\setlength{\rightskip}{0pt plus 5cm}def get\-Top\-Plate\-R\-Layer\-X\-Max ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1CapacitorUnit_1_1CapacitorUnit_a9788696eb8f1cffde53de39c7f2ffcaa} -\begin{DoxyReturn}{Returns} -the abscissa of the bottom-\/right end-\/point of the top plate routing layer. -\end{DoxyReturn} - - -References Capacitor\-Unit.\-top\-Plate\-R\-Layer\-Dict. - - - -The documentation for this class was generated from the following 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mode 100644 index 4c8b04cb..00000000 --- a/oroshi/doc/latex/classpython_1_1Stack_1_1Stack.tex +++ /dev/null @@ -1,222 +0,0 @@ -\hypertarget{classpython_1_1Stack_1_1Stack}{\section{Stack Class Reference} -\label{classpython_1_1Stack_1_1Stack}\index{Stack@{Stack}} -} - - -Draw a \hyperlink{classpython_1_1Stack_1_1Stack}{Stack} of Transistors. - - - - -Inherits object. - -\subsection*{Public Member Functions} -\begin{DoxyCompactItemize} -\item -def \hyperlink{classpython_1_1Stack_1_1Stack_ac775ee34451fdfa742b318538164070e}{\-\_\-\-\_\-init\-\_\-\-\_\-} -\begin{DoxyCompactList}\small\item\em {\bfseries \mbox{[}A\-P\-I\mbox{]}} Constructor \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1Stack_1_1Stack_ad7f0300aaad3ad8b2de70ae6c106c102}{set\-Wirings} -\begin{DoxyCompactList}\small\item\em {\bfseries \mbox{[}A\-P\-I\mbox{]}} Set the \hyperlink{classpython_1_1Stack_1_1Stack}{Stack} wiring specification. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1Stack_1_1Stack_a20b46b43488cc58c302b123a89299d85}{compute\-Dimensions} -\begin{DoxyCompactList}\small\item\em {\bfseries \mbox{[}internal\mbox{]}} Compute \hyperlink{classpython_1_1Stack_1_1Stack}{Stack} dimensions from the technological rules. \end{DoxyCompactList}\item -def \hyperlink{classpython_1_1Stack_1_1Stack_affc52c42a8c72dc1125ddce55647a6f9}{do\-Layout} -\begin{DoxyCompactList}\small\item\em {\bfseries \mbox{[}A\-P\-I\mbox{]}} Draw the complete layout. \end{DoxyCompactList}\end{DoxyCompactItemize} - - -\subsection{Detailed Description} -Draw a \hyperlink{classpython_1_1Stack_1_1Stack}{Stack} of Transistors. - -A \hyperlink{classpython_1_1Stack_1_1Stack}{Stack} of Transistors is a set of transistor put into a regular band and connected through their sources/drains. All share the exact same W \& L. The way they are connecteds defines what functionnality the \hyperlink{classpython_1_1Stack_1_1Stack}{Stack} implement. - -The abutment box of the stack is adjusted so that both height and width are even multiples of the track pitches, so the device can be easily placed and handled by the mixed router. The extra space needed for padding is added around the active area. Due to the presence of tracks at the top and bottom of the stack, the active area will be horizontally centered but {\bfseries not} vertically. - -The drawing of the stack is controlled through a set of variables (attributes) that allows to create it regardless of the technology. The technology is taken into account in the way those variables are computed and, obviously, their values. The following schematics details the main stack drawing variables along with their computations.\hypertarget{classpython_1_1Stack_1_1Stack_secStackLayout}{}\subsection{Stack Layout}\label{classpython_1_1Stack_1_1Stack_secStackLayout} -\hypertarget{classpython_1_1Stack_1_1Stack_secGatePitch}{}\subsubsection{Gate pitch}\label{classpython_1_1Stack_1_1Stack_secGatePitch} - -\begin{DoxyItemize} -\item {\ttfamily self.\-gate\-Pitch} \-: the pitch of transistors gates, inside the stack. It also applies to dummy transistors. -\end{DoxyItemize} - - -\begin{DoxyImage} -\includegraphics[width=.9\linewidth]{gate-pitch-1} -\caption{Gate Pitch} -\end{DoxyImage} -\hypertarget{classpython_1_1Stack_1_1Stack_secActiveSideWidth}{}\subsubsection{Active Side Width}\label{classpython_1_1Stack_1_1Stack_secActiveSideWidth} - -\begin{DoxyItemize} -\item {\ttfamily self.\-active\-Side\-Width} \-: the distance between the axis of the last transistor gate (on the left or right) and the edge of the active area ({\itshape not} the diffusion area). -\end{DoxyItemize} - - -\begin{DoxyImage} -\includegraphics[width=.9\linewidth]{active-side-width-1} -\caption{Active Side Width} -\end{DoxyImage} -\hypertarget{classpython_1_1Stack_1_1Stack_secHTrackDistance}{}\subsubsection{H-\/\-Track Distance}\label{classpython_1_1Stack_1_1Stack_secHTrackDistance} - -\begin{DoxyItemize} -\item {\ttfamily self.\-h\-Track\-Distance} \-: the minimal distance between either the top or bottom edge of the active area and the {\itshape axis} of the first track. -\end{DoxyItemize} - - -\begin{DoxyImage} -\includegraphics[width=.9\linewidth]{htrack-distance-1} -\caption{H-\/\-Track distance} -\end{DoxyImage} -\hypertarget{classpython_1_1Stack_1_1Stack_secOverallVariables}{}\subsubsection{Bounding\-Box \& Overall Variables}\label{classpython_1_1Stack_1_1Stack_secOverallVariables} - -\begin{DoxyItemize} -\item {\ttfamily self.\-xpitches} \-: the number of vertical track pitches needed to fully enclose the active area. -\item {\ttfamily self.\-ypitches} \-: the number of horizontal track pitches needed to fully enclose the active area. -\item {\ttfamily self.\-active\-Offset\-X} \& {\ttfamily self.\-active\-Offset\-Y} \-: the offsets of the active area from the bottom left corner of the abutment box. -\item {\ttfamily self.\-diffusion\-Width} \& {\ttfamily self.\-diffusion\-Height} are the minimun dimensions required to fit the active area. -\item {\ttfamily self.\-top\-Tracks\-Nb()} \-: the number of tracks at the top of the stack. -\item {\ttfamily self.\-bot\-Tracks\-Nb()} \-: the number of tracks at the bottom of the stack. -\end{DoxyItemize} - - -\begin{DoxyImage} -\includegraphics[width=.9\linewidth]{stack-layout-3} -\caption{General Stack Layout} -\end{DoxyImage} -\hypertarget{classpython_1_1Stack_1_1Stack_secWiringSpecs}{}\subsection{Wiring Specifications}\label{classpython_1_1Stack_1_1Stack_secWiringSpecs} -\hyperlink{classpython_1_1Stack_1_1Stack}{Stack} routing is done through vertical {\ttfamily metal1} wires coming from the gates and diffusions areas and {\ttfamily metal2} horizontal wires that can be either above or below the active area. {\ttfamily metal2} wires (or track) goes through the whole stack and are assigned to one net only. A net will have at least one track above or below and may have both. - -The connections to the diffusions areas and gates of the various fingers are specified through a list. The stack is made of a regular alternation of diffusions and gates. The list tells, for each one starting from the left, to which net and track they are connected. For a stack of $NFs$ transistor fingers, the must wiring specification must contains $ 3 + (NFs-1) \times 2$ elements. The list is given through one {\itshape string} with each elements separated by one or more whitespace. The syntax for {\itshape one} element is detailed \hyperlink{classpython_1_1Stack_1_1Stack_secAtomicWiring}{Atomic Wiring Specification}. - -{\bfseries Track numbering scheme} - -Tracks above (top) the active area and below (bottom) each have their own numbering. In both case, the count start {\itshape from} the active area. This, the top tracks will be numbered by increasing Y and the bottom tracks by {\itshape decreasing} Y. - -{\bfseries Track/\-Net assignement} - -The track/net assignement is deduced from the atomic wiring specifications. It also allows to compute the total number of tracks needed above and below the active area. - - -\begin{DoxyImage} -\includegraphics[width=.9\linewidth]{wiring-spec-2} -\caption{Wiring Specification} -\end{DoxyImage} -\hypertarget{classpython_1_1Stack_1_1Stack_secAtomicWiring}{}\subsubsection{Atomic Wiring Specification}\label{classpython_1_1Stack_1_1Stack_secAtomicWiring} -An atomic wiring specification has the same syntax for either diffusions or gates. It {\itshape must} not comprise any whitespaces. it is made of the following parts\-: -\begin{DoxyItemize} -\item The net name to connect to. -\item Whether the track is above the active area ({\ttfamily \char`\"{}t\char`\"{}}) or below ({\ttfamily \char`\"{}b\char`\"{}}). The special case ({\ttfamily \char`\"{}z\char`\"{}}) means that this element must be left unconnected (is such case possible?). -\item The number of the track. -\end{DoxyItemize} - - -\begin{DoxyImage} -\includegraphics[width=.4\linewidth]{wiring-spec-1} -\caption{Atomic Wiring Specification} -\end{DoxyImage} -\hypertarget{classpython_1_1Stack_1_1Stack_secStackImplDetails}{}\subsection{Stack Implementation Details}\label{classpython_1_1Stack_1_1Stack_secStackImplDetails} -The {\ttfamily \-\_\-\-\_\-setattr\-\_\-\-\_\-()} and {\ttfamily \-\_\-\-\_\-getattr\-\_\-\-\_\-} functions have been redefined so that the technological values (rules) can be accessed has normal attributes of the \hyperlink{classpython_1_1Stack_1_1Stack}{Stack} class, in addition to the regular ones. - -\subsection{Constructor \& Destructor Documentation} -\hypertarget{classpython_1_1Stack_1_1Stack_ac775ee34451fdfa742b318538164070e}{\index{python\-::\-Stack\-::\-Stack@{python\-::\-Stack\-::\-Stack}!\-\_\-\-\_\-init\-\_\-\-\_\-@{\-\_\-\-\_\-init\-\_\-\-\_\-}} -\index{\-\_\-\-\_\-init\-\_\-\-\_\-@{\-\_\-\-\_\-init\-\_\-\-\_\-}!python::Stack::Stack@{python\-::\-Stack\-::\-Stack}} -\subsubsection[{\-\_\-\-\_\-init\-\_\-\-\_\-}]{\setlength{\rightskip}{0pt plus 5cm}def \-\_\-\-\_\-init\-\_\-\-\_\- ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{device, } -\item[{}]{N\-E\-R\-C, } -\item[{}]{N\-I\-R\-C} -\end{DoxyParamCaption} -)}}\label{classpython_1_1Stack_1_1Stack_ac775ee34451fdfa742b318538164070e} - - -{\bfseries \mbox{[}A\-P\-I\mbox{]}} Constructor - -param rules The physical rule set. -\begin{DoxyParams}{Parameters} -{\em device} & The {\bf Hurricane} A\-M\-S device into which the layout will be drawn. \\ -\hline -{\em N\-E\-R\-C} & Number of contact rows in external (first \& last) diffusion connectors. \\ -\hline -{\em N\-I\-R\-C} & Number of contact rows in middle diffusion connectors. param w The {\bfseries width} of every transistor of the stack (aka {\itshape fingers}). param L The {\bfseries length} of every transistor. param N\-Fs The total number of fingers (dummies includeds). param N\-Ds The number of dummies to put on each side of the stack. \\ -\hline -\end{DoxyParams} - - -References Stack.\-b\-Implant\-Layer, Stack.\-bot\-Tracks, Stack.\-bot\-W\-Tracks, Stack.\-bulk\-Net, Stack.\-bulks, Stack.\-device, Stack.\-dimensioned, Bulk.\-flags, Stack.\-flags, Stack.\-is\-Nmos(), Stack.\-L, Stack.\-meta\-Tnb(), Stack.\-meta\-Transistors, Stack.\-N\-Ds, Stack.\-N\-E\-R\-C, Stack.\-N\-Fs, Stack.\-N\-I\-R\-C, Stack.\-t\-Implant\-Layer, Stack.\-top\-Tracks, Stack.\-top\-W\-Tracks, Stack.\-w, Stack.\-well\-Layer, and Stack.\-wirings. - - - -\subsection{Member Function Documentation} -\hypertarget{classpython_1_1Stack_1_1Stack_ad7f0300aaad3ad8b2de70ae6c106c102}{\index{python\-::\-Stack\-::\-Stack@{python\-::\-Stack\-::\-Stack}!set\-Wirings@{set\-Wirings}} -\index{set\-Wirings@{set\-Wirings}!python::Stack::Stack@{python\-::\-Stack\-::\-Stack}} -\subsubsection[{set\-Wirings}]{\setlength{\rightskip}{0pt plus 5cm}def set\-Wirings ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{wiring\-Spec} -\end{DoxyParamCaption} -)}}\label{classpython_1_1Stack_1_1Stack_ad7f0300aaad3ad8b2de70ae6c106c102} - - -{\bfseries \mbox{[}A\-P\-I\mbox{]}} Set the \hyperlink{classpython_1_1Stack_1_1Stack}{Stack} wiring specification. - - -\begin{DoxyParams}{Parameters} -{\em wiring\-Spec} & A string defining the connections for the gates and diffusion areas.\\ -\hline -\end{DoxyParams} -For a comprehensive explanation of the wiring specification, refers to \hyperlink{classpython_1_1Stack_1_1Stack_secWiringSpecs}{Wiring Specifications} . - -References Stack.\-bot\-Tracks, Stack.\-bot\-Tracks\-Nb(), Stack.\-bot\-W\-Tracks, Stack.\-bulk\-Net, Stack.\-compute\-Dimensions(), Stack.\-device, Stack.\-dimensioned, Stack.\-e\-Diff\-Metal1\-Width, Bulk.\-flags, Stack.\-flags, Stack.\-gate\-Pitch, Stack.\-get\-Bot\-Track\-Y(), Stack.\-get\-Horizontal\-Width(), Stack.\-hor\-Pitch, Stack.\-L, Stack.\-metal1\-To\-Gate, Stack.\-meta\-Transistors, Stack.\-side\-Active\-Width, Stack.\-top\-Tracks, Stack.\-top\-Tracks\-Nb(), Stack.\-top\-W\-Tracks, Stack.\-wirings, and Stack.\-ypitches. - -\hypertarget{classpython_1_1Stack_1_1Stack_a20b46b43488cc58c302b123a89299d85}{\index{python\-::\-Stack\-::\-Stack@{python\-::\-Stack\-::\-Stack}!compute\-Dimensions@{compute\-Dimensions}} -\index{compute\-Dimensions@{compute\-Dimensions}!python::Stack::Stack@{python\-::\-Stack\-::\-Stack}} -\subsubsection[{compute\-Dimensions}]{\setlength{\rightskip}{0pt plus 5cm}def compute\-Dimensions ( -\begin{DoxyParamCaption} -\item[{}]{self} -\end{DoxyParamCaption} -)}}\label{classpython_1_1Stack_1_1Stack_a20b46b43488cc58c302b123a89299d85} - - -{\bfseries \mbox{[}internal\mbox{]}} Compute \hyperlink{classpython_1_1Stack_1_1Stack}{Stack} dimensions from the technological rules. - -{\bfseries Internal function.} Perform the computation of\-: -\begin{DoxyItemize} -\item {\ttfamily self.\-metal1\-Pitch} -\item {\ttfamily self.\-min\-Width\-\_\-metal1} -\item {\ttfamily self.\-metal2\-Pitch} -\item {\ttfamily self.\-min\-Width\-\_\-metal2} -\item {\ttfamily self.\-gate\-Pitch} -\item {\ttfamily self.\-side\-Active\-Width} -\item {\ttfamily self.\-h\-Track\-Distance} -\item {\ttfamily self.\-xpitches} -\item {\ttfamily self.\-ypitches} -\item {\ttfamily self.\-active\-Offset\-X} -\item {\ttfamily self.\-active\-Offset\-Y} -\item {\ttfamily self.\-bounding\-Box} -\end{DoxyItemize} - -References Stack.\-active\-Box, Stack.\-active\-Offset\-X, Stack.\-active\-Offset\-Y, Stack.\-bb\-Height, Stack.\-bb\-Width, Stack.\-bot\-W\-Tracks, Stack.\-bounding\-Box, Stack.\-bulks, Stack.\-bulk\-Width, Stack.\-compute\-Layout\-Parasitics(), Stack.\-compute\-Stress\-Effect(), Stack.\-contact\-Diff\-Pitch, Stack.\-contact\-Diff\-Side, Stack.\-D\-G\-G, Stack.\-D\-G\-I, Stack.\-dimensioned, Stack.\-D\-M\-C\-G, Stack.\-D\-M\-C\-G\-T, Stack.\-D\-M\-C\-I, Stack.\-e\-Diff\-Metal1\-Width, Bulk.\-flags, Stack.\-flags, Stack.\-gate\-Pitch, Stack.\-gate\-Via1\-Pitch, Stack.\-get\-Bot\-Track\-Y(), Stack.\-get\-Horizontal\-Width(), Stack.\-get\-Last\-Top\-Track\-Y(), Stack.\-hor\-Pitch, Stack.\-h\-Track\-Distance, Stack.\-i\-Diff\-Metal1\-Width, Stack.\-is\-V\-H, Stack.\-L, Stack.\-metal1\-To\-Gate, Stack.\-metal2\-Pitch, Stack.\-metal2\-Techno\-Pitch, Stack.\-metal3\-Pitch, Stack.\-N\-E\-R\-C, Stack.\-N\-Fs, Stack.\-N\-I\-R\-C, Stack.\-side\-Active\-Width, Stack.\-tracks\-Nb\-Pitch(), Stack.\-v\-Bulk\-Distance, Stack.\-ver\-Pitch, Stack.\-w, Stack.\-wire1\-Width, Stack.\-wire2\-Width, Stack.\-wire3\-Width, Stack.\-wirings, Stack.\-xpitches, and Stack.\-ypitches. - - - -Referenced by Capacitor\-Unit.\-create(), Stack.\-do\-Layout(), Rout\-Matched\-Capacitor.\-route(), and Stack.\-set\-Wirings(). - -\hypertarget{classpython_1_1Stack_1_1Stack_affc52c42a8c72dc1125ddce55647a6f9}{\index{python\-::\-Stack\-::\-Stack@{python\-::\-Stack\-::\-Stack}!do\-Layout@{do\-Layout}} -\index{do\-Layout@{do\-Layout}!python::Stack::Stack@{python\-::\-Stack\-::\-Stack}} -\subsubsection[{do\-Layout}]{\setlength{\rightskip}{0pt plus 5cm}def do\-Layout ( -\begin{DoxyParamCaption} -\item[{}]{self, } -\item[{}]{bb\-Mode} -\end{DoxyParamCaption} -)}}\label{classpython_1_1Stack_1_1Stack_affc52c42a8c72dc1125ddce55647a6f9} - - -{\bfseries \mbox{[}A\-P\-I\mbox{]}} Draw the complete layout. - -Draw the commplete layout of the \hyperlink{classpython_1_1Stack_1_1Stack}{Stack}. - -References Stack.\-active\-Offset\-X, Stack.\-active\-Offset\-Y, Stack.\-bb\-Width, Stack.\-bot\-Tracks, Stack.\-bot\-W\-Tracks, Stack.\-bounding\-Box, Stack.\-bulk\-Net, Stack.\-bulks, Stack.\-bulk\-Width, Stack.\-compute\-Dimensions(), Stack.\-contact\-Diff\-Pitch, Stack.\-device, Stack.\-D\-G\-G, Stack.\-D\-G\-I, Stack.\-D\-M\-C\-G, Stack.\-D\-M\-C\-G\-T, Stack.\-D\-M\-C\-I, Stack.\-draw\-Active(), Stack.\-draw\-Gate(), Stack.\-draw\-Source\-Drain(), Stack.\-draw\-Well(), Stack.\-e\-Diff\-Metal1\-Width, Bulk.\-flags, Stack.\-flags, Stack.\-gate\-Pitch, Stack.\-gate\-Via1\-Pitch, Stack.\-get\-Bot\-Track\-Y(), Stack.\-get\-Horizontal\-Axis(), Stack.\-get\-Horizontal\-Width(), Stack.\-get\-Top\-Track\-Y(), Stack.\-get\-Wiring\-Width(), Stack.\-hor\-Pitch, Stack.\-i\-Diff\-Metal1\-Width, Stack.\-is\-Bot\-Track(), Stack.\-is\-V\-H, Stack.\-L, Stack.\-metal1\-To\-Gate, Stack.\-N\-E\-R\-C, Stack.\-N\-Fs, Stack.\-N\-I\-R\-C, Stack.\-side\-Active\-Width, Stack.\-t\-Implant\-Layer, Stack.\-top\-Tracks, Stack.\-top\-W\-Tracks, Stack.\-w, Stack.\-well\-Layer, Stack.\-wire1\-Width, Stack.\-wire2\-Width, Stack.\-wire3\-Width, and Stack.\-wirings. - - - -The documentation for this class was generated from the following file\-:\begin{DoxyCompactItemize} -\item -Stack.\-py\end{DoxyCompactItemize} diff --git a/oroshi/doc/man/man3/python_CapacitorMatrix_CapacitorStack.3 b/oroshi/doc/man/man3/python_CapacitorMatrix_CapacitorStack.3 deleted file mode 100644 index ae08977d..00000000 --- a/oroshi/doc/man/man3/python_CapacitorMatrix_CapacitorStack.3 +++ /dev/null @@ -1,262 +0,0 @@ -.TH "CapacitorStack" 3 "Thu Mar 19 2020" "Version 1.0" "Oroshi - Analog Devices Layout" \" -*- nroff -*- -.ad l -.nh -.SH NAME -CapacitorStack \- -Draws the layout of a compact capacitor or a matrix of adjacent identical capacitors\&. - -.SH SYNOPSIS -.br -.PP -.PP -Inherits CapacitorUnit\&. -.SS "Public Member Functions" - -.in +1c -.ti -1c -.RI "def \fB__init__\fP" -.br -.RI "\fIThis is the class constructor\&. \fP" -.ti -1c -.RI "def \fB__isUnitCap__\fP" -.br -.ti -1c -.RI "def \fB__isMatchingSchemeOK__\fP" -.br -.ti -1c -.RI "def \fBcapacitorIdOccurence\fP" -.br -.ti -1c -.RI "def \fBcreate\fP" -.br -.RI "\fIDraw the compact or matrix of capacitors\&. \fP" -.ti -1c -.RI "def \fBcapacitorLine\fP" -.br -.RI "\fIIteratively draws a horizontal or vertical line of capacitors according to the \fCdirection\fP parameter\&. \fP" -.ti -1c -.RI "def \fBcapacitorMatrix\fP" -.br -.RI "\fIDraws a matrix of identical capacitors\&. \fP" -.ti -1c -.RI "def \fBdrawAbutmentBox\fP" -.br -.RI "\fIDraws the abutment box of the matrix or campact capacitor\&. \fP" -.ti -1c -.RI "def \fBdrawBottomPlatesRLayers\fP" -.br -.RI "\fIDraws the routing layers connecting the bottom plate in the matrix of capacitors\&. \fP" -.ti -1c -.RI "def \fBdrawTopPlatesRLayers\fP" -.br -.RI "\fIDraws the routing layers connecting the top plates in the matrix of capacitors\&. \fP" -.ti -1c -.RI "def \fBgetVerticalRoutingTrack_width\fP" -.br -.ti -1c -.RI "def \fBgetMatrixDim\fP" -.br -.ti -1c -.RI "def \fBgetMatchingScheme\fP" -.br -.in -1c -.SH "Detailed Description" -.PP -Draws the layout of a compact capacitor or a matrix of adjacent identical capacitors\&. - -The matrix can be composed of one type of capacitors, either Poly-Poly or Metal-Metal in 350 nm AMS CMOS technology\&. When matching mode is off, every adjacent plates of any consecutive elementary capacitors are connected to each other using vertical routing layers\&. Otherwise, when matching mode is on, any of elementary capacitors can belong to, $ C_1 $ or $ C_2 $ according to the entered matching scheme\&. Thus, routing is not done in this class\&. In both modes, the complete routing process is done using the \fCRoutCapacitor\fP class\&. -.SH "Constructor & Destructor Documentation" -.PP -.SS "def __init__ (self, device, capacitance, capacitorType, abutmentBoxPosition, nets, unitCap = \fC0\fP, matrixDim = \fC[1\fP, matchingMode = \fCFalse\fP, matchingScheme = \fC[]\fP, dummyRing = \fCFalse\fP, dummyElement = \fCFalse\fP)" - -.PP -This is the class constructor\&. Basically, the class there are three categories of attributes\&. There are the ones related to the capacitor caracteristics, its type, dimensions\&. Also, there are attributes to parametrize the class into matching mode or not and there are other attributes realted to the layout varibales\&. The class has defaut input values, thus, in this constructor, there are two 'sub-constructors' according to the entered input parameters\&. The class attributes are : -.PP -\fBParameters:\fP -.RS 4 -\fIdevice\fP The \fBHurricane\fP AMS device into which the layout is drawn\&. -.br -\fIcapacitance\fP The value of the capacitor, expressed in femto Farad (fF)\&. -.br -\fIcapacitorType\fP Can be MIM or PIP type capacitor\&. -.br -\fIabutmentPosition\fP Refers to the abscissa (XMin) of the bottom left corner of the abutment Box\&. -.br -\fIabutmentBoxYMin\fP Refers to the ordinate (YMin) of the bottom left corner of the abutment Box\&. -.RE -.PP -Except the two last arguments, all the parameters are common with the CapacitorUnit class because the \fC\fBCapacitorStack\fP\fP constructor calls the mother class constructor to create either a compact capacitor of \fCcapacitance\fP value or \fCrowNumber*\fP \fCcolumnNumber\fP unity capacitors\&. -.PP -\fBParameters:\fP -.RS 4 -\fIrowNumber\fP Number of rows in the matrix of capacitors\&. -.br -\fIcolumnNumber\fP Number of columns in the matrix of capacitors\&. -.RE -.PP - -.PP -References CapacitorStack\&.__areInputDataOK__(), CapacitorUnit\&.__computeCapDim__(), CapacitorStack\&.__initGivenNonZeroUnitCap__(), CapacitorStack\&.__initGivenNonZeroUnitCapInMatchingMode__(), CapacitorStack\&.__initGivenZeroUnitCap__(), CapacitorStack\&.__initGivenZeroUnitCapInMatchingMode__(), CapacitorStack\&.__initMatrixMode__(), CapacitorUnit\&.__isCapacitorUnitOK__(), CapacitorStack\&.abutmentBox, CapacitorUnit\&.abutmentBox, CapacitorStack\&.abutmentBox_spacing, CapacitorStack\&.abutmentBoxPosition, CapacitorStack\&.capacitance, CapacitorStack\&.capacitorIdOccurence(), CapacitorStack\&.capacitorsNumber, CapacitorStack\&.capacitorType, CapacitorUnit\&.capacitorType, CapacitorStack\&.compactCapDim, CapacitorStack\&.computeUnitCap(), CapacitorStack\&.device, CapacitorUnit\&.device, Stack\&.device, CapacitorStack\&.doMatrix, CapacitorStack\&.dummyElement, CapacitorStack\&.dummyRing, CapacitorStack\&.dummyRingPosition, CapacitorStack\&.evaluateUnitCap(), CapacitorStack\&.matchingMode, CapacitorStack\&.matchingScheme, CapacitorStack\&.matrixDim, CapacitorStack\&.minEnclosure_hRoutingLayer_topPlate_cut, CapacitorStack\&.minEnclosure_vRoutingTrackCut, CapacitorStack\&.minSpacing_vRoutingTrack, CapacitorStack\&.minSpacing_vRoutingTrackCut, CapacitorStack\&.minWidth_hRoutingLayer_topPlate_cut, CapacitorStack\&.minWidth_vRoutingTrack, CapacitorStack\&.minWidth_vRoutingTrackCut, CapacitorStack\&.nets, CapacitorStack\&.unitCapacitance, CapacitorStack\&.unitCapDim, and CapacitorStack\&.vRoutingTrack_width\&. -.SH "Member Function Documentation" -.PP -.SS "def __isUnitCap__ (self)" - -.PP -\fBReturns:\fP -.RS 4 -True if the drawn capacitor is a compact one\&. This function is useful when an instance is called in another class\&. \fBExample\fP : when the matrix or the compact capacitors are to be fully routed\&. -.RE -.PP - -.SS "def __isMatchingSchemeOK__ (self)" - -.PP -\fBReturns:\fP -.RS 4 -\fCTrue\fP if the matching scheme specifications are correct\&. Specifications are : -.IP "\(bu" 2 -Similar number of elements as total number of elementary capacitor in the matrix\&. -.IP "\(bu" 2 -Equal number of affected capacitors to C1 as to C2\&. -.IP "\(bu" 2 -Capacitor identifiers equal to '1' or '2' only\&. -.IP "\(bu" 2 -Otherwise, the function returns \fCFalse\fP\&. -.PP -.RE -.PP - -.PP -References CapacitorStack\&.matchingScheme, and CapacitorStack\&.matrixDim\&. -.PP -Referenced by CapacitorStack\&.capacitorIdOccurence()\&. -.SS "def capacitorIdOccurence (self, capacitorIdentifier)" - -.PP -\fBReturns:\fP -.RS 4 -occurence of capacitor identifier in the entered matching scheme\&. This is useful to verify that \fCself\&.matchingScheme\fP is correct\&. -.RE -.PP - -.PP -References CapacitorStack\&.__areMatrixDimOK__(), CapacitorStack\&.__isMatchingSchemeOK__(), CapacitorStack\&.capacitorsNumber, CapacitorStack\&.dummyElement, CapacitorStack\&.dummyRing, CapacitorStack\&.matchingMode, CapacitorStack\&.matchingScheme, and CapacitorStack\&.nets\&. -.PP -Referenced by CapacitorStack\&.__init__()\&. -.SS "def create (self, bbMode = \fCFalse\fP)" - -.PP -Draw the compact or matrix of capacitors\&. First, \&. Second, \&. Finally, \&. -.PP -References CapacitorStack\&.__initMatchingMode__(), CapacitorStack\&.abutmentBox_spacing, CapacitorStack\&.abutmentBoxPosition, CapacitorStack\&.capacitance, CapacitorStack\&.capacitorMatrix(), CapacitorStack\&.capacitorType, CapacitorUnit\&.capacitorType, CapacitorStack\&.computeBondingBoxDimensions(), CapacitorStack\&.device, CapacitorUnit\&.device, Stack\&.device, CapacitorStack\&.doMatrix, CapacitorStack\&.drawAbutmentBox(), CapacitorUnit\&.drawAbutmentBox(), CapacitorStack\&.drawBottomPlatesRLayers(), CapacitorStack\&.drawCapacitorStack(), CapacitorStack\&.drawTopPlatesRLayers(), CapacitorStack\&.dummyRing, CapacitorStack\&.matchingMode, CapacitorStack\&.matrixDim, CapacitorStack\&.nets, CapacitorStack\&.setRules(), and CapacitorUnit\&.setRules()\&. -.PP -Referenced by CapacitorStack\&.capacitorLine(), and CapacitorStack\&.capacitorMatrix()\&. -.SS "def capacitorLine (self, dy, abutmentBox_spacing, matchingSchemeRowIndex = \fC0\fP)" - -.PP -Iteratively draws a horizontal or vertical line of capacitors according to the \fCdirection\fP parameter\&. An exception is raised if the specified direction is different from \fC{'horizontal'\fP,'vertical'}\&. At every iteration, an instance of the CapacitorUnit class is created and its layout is drawn\&. -.PP -\fBReturns:\fP -.RS 4 -a list containing the drawn capacitors\&. -.RE -.PP -\fBParameters:\fP -.RS 4 -\fIdy\fP the vertical position of the first cut in cut line\&. -.RE -.PP -\fBRemarks:\fP -.RS 4 -An exception is raised if the specified direction is different from \fC{'horizontal'\fP,'vertical'} -.RE -.PP - -.PP -References CapacitorStack\&.abutmentBoxPosition, CapacitorStack\&.capacitorType, CapacitorUnit\&.capacitorType, CapacitorStack\&.create(), CapacitorStack\&.createElementInCapacitorLine(), CapacitorStack\&.device, CapacitorUnit\&.device, Stack\&.device, CapacitorStack\&.dummyRing, CapacitorStack\&.matchingMode, CapacitorStack\&.matchingScheme, CapacitorStack\&.matrixDim, CapacitorStack\&.nets, and CapacitorStack\&.unitCapacitance\&. -.PP -Referenced by CapacitorStack\&.capacitorMatrix()\&. -.SS "def capacitorMatrix (self, abutmentBox_spacing = \fC0\fP)" - -.PP -Draws a matrix of identical capacitors\&. The matrix is iterativelly constructed\&. At every iteration, a new horizontal line of capacitors is drawn\&. -.PP -\fBReturns:\fP -.RS 4 -a nested list of elementary capacitors\&. -.RE -.PP - -.PP -References CapacitorStack\&.abutmentBox_spacing, CapacitorStack\&.abutmentBoxPosition, CapacitorStack\&.capacitorLine(), CapacitorStack\&.capacitorType, CapacitorUnit\&.capacitorType, CapacitorStack\&.create(), CapacitorStack\&.device, CapacitorUnit\&.device, Stack\&.device, CapacitorStack\&.dummyRing, CapacitorStack\&.getCapDim(), CapacitorStack\&.matrixDim, CapacitorStack\&.nets, and CapacitorStack\&.unitCapacitance\&. -.PP -Referenced by CapacitorStack\&.create()\&. -.SS "def drawAbutmentBox (self, abutmentBox_spacing = \fC0\fP)" - -.PP -Draws the abutment box of the matrix or campact capacitor\&. -.PP -References CapacitorStack\&.abutmentBox, CapacitorUnit\&.abutmentBox, CapacitorStack\&.abutmentBox_spacing, CapacitorStack\&.abutmentBoxPosition, CapacitorStack\&.computeAbutmentBoxDimensions(), and CapacitorUnit\&.computeAbutmentBoxDimensions()\&. -.PP -Referenced by CapacitorStack\&.create()\&. -.SS "def drawBottomPlatesRLayers (self, bottomPlateRLayer, drawnCapacitor)" - -.PP -Draws the routing layers connecting the bottom plate in the matrix of capacitors\&. First, the relative positions of the routing layer is of the is extracted from the elementary capacitor instance\&. Then, its width is computed in a way to connect adjacent plates\&. Then, the routing layers are iterativelly drawn\&. The two borders are \&. -.PP -References CapacitorStack\&.matrixDim, and CapacitorStack\&.nets\&. -.PP -Referenced by CapacitorStack\&.create()\&. -.SS "def drawTopPlatesRLayers (self, topPlateRLayer, drawnCapacitor)" - -.PP -Draws the routing layers connecting the top plates in the matrix of capacitors\&. First, the relative positions of the routing layers is of the is extracted from the elementary capacitor instance\&. Then, its width is computed in a way to connect adjacent plates\&. Then, the routing layers are iterativelly drawn\&. The two borders are \&. -.PP -\fBRemarks:\fP -.RS 4 -An exception is raised if the number of rows in the matrix is lower than 2\&. -.RE -.PP - -.PP -References CapacitorStack\&.matrixDim, and CapacitorStack\&.nets\&. -.PP -Referenced by CapacitorStack\&.create()\&. -.SS "def getVerticalRoutingTrack_width (self)" - -.PP -\fBReturns:\fP -.RS 4 -The width of the vertical routing tracks in matching mode\&. -.RE -.PP -\fBRemark:\fP -.RS 4 -This function is useful in matching mode, ie\&., in RoutCapacitor class, when routing the two capacitors\&. -.RE -.PP - -.SS "def getMatrixDim (self)" - -.PP -\fBReturns:\fP -.RS 4 -A dictionary contaning capacitor matrix's dimensions -.RE -.PP - -.PP -References CapacitorStack\&.compactCapDim, and CapacitorStack\&.doMatrix\&. -.SS "def getMatchingScheme (self)" - -.PP -\fBReturns:\fP -.RS 4 -the matching scheme\&. The function is useful in \fCRoutMatchedCapacitor\fP class to load \fCself\&.matchingScheme\fP attribute\&. -.RE -.PP - - -.SH "Author" -.PP -Generated automatically by Doxygen for Oroshi - Analog Devices Layout from the source code\&. diff --git a/oroshi/doc/man/man3/python_CapacitorRouted_RoutMatchedCapacitor.3 b/oroshi/doc/man/man3/python_CapacitorRouted_RoutMatchedCapacitor.3 deleted file mode 100644 index e21b2f46..00000000 --- a/oroshi/doc/man/man3/python_CapacitorRouted_RoutMatchedCapacitor.3 +++ /dev/null @@ -1,362 +0,0 @@ -.TH "RoutMatchedCapacitor" 3 "Thu Mar 19 2020" "Version 1.0" "Oroshi - Analog Devices Layout" \" -*- nroff -*- -.ad l -.nh -.SH NAME -RoutMatchedCapacitor \- -.PP -Routs two matched capacitors, C1 and C2, drawn in a capacitor matrix\&. - -.SH SYNOPSIS -.br -.PP -.PP -Inherits CapacitorUnit, CapacitorStack, and VerticalRoutingTracks\&. -.SS "Public Member Functions" - -.in +1c -.ti -1c -.RI "def \fB__init__\fP" -.br -.RI "\fIA special method used to customize the class instance to an initial state in which : \fP" -.ti -1c -.RI "def \fBroute\fP" -.br -.RI "\fIDraws the complete layout given the capacitor matrix\&. \fP" -.ti -1c -.RI "def \fBsetRules\fP" -.br -.RI "\fIDefines technology rules used to draw the layout\&. \fP" -.ti -1c -.RI "def \fBsetLayers\fP" -.br -.RI "\fIDefines all physical layers used to draw the layout\&. \fP" -.ti -1c -.RI "def \fBcomputeDimensions\fP" -.br -.RI "\fIComputes, through simple instructions and functions calls, layout variables detailed in Figure 2\&. \fP" -.ti -1c -.RI "def \fBcomputeHRoutingTrackYCenter\fP" -.br -.RI "\fIComputes centers' ordinates of the eight horizontal routing tracks\&. \fP" -.ti -1c -.RI "def \fBcomputeHRLayerYCenter\fP" -.br -.RI "\fISets the stretching value of top plates\&. \fP" -.ti -1c -.RI "def \fBdrawHRoutingTracks\fP" -.br -.RI "\fIIteratively draws horizontal routing tracks on top and bottom positions of the matrix using physical layer \fCroutingTracksLayer\fP\&. \fP" -.ti -1c -.RI "def \fBdrawHRLayers\fP" -.br -.RI "\fIIteratively draws the horizontal routing layers starting with bottom left elementary capacitor $ C_{00} $\&. \fP" -.ti -1c -.RI "def \fBdrawCuts\fP" -.br -.RI "\fIDraws all required cuts using physical layers : \fP" -.ti -1c -.RI "def \fBdrawOneCut_vRoutingTrack_HRLayer\fP" -.br -.RI "\fIDraws one cut, in layer \fCcutLayer\fP, in order to connect a vertical routing track, at position \fCcutXMin\fP in metal 2, and a horizontal routing track, at position \fCcutYMin\fP in metal 3\&. \fP" -.ti -1c -.RI "def \fBdrawCuts_vRoutingTrack_hRoutingTrack\fP" -.br -.RI "\fIDraws cuts to connect vertical routing tracks in metal 2 and horizontal routing tracks in metal 3\&. \fP" -.ti -1c -.RI "def \fB__stretchTopPlates__\fP" -.br -.RI "\fIIteratively performs top plates stretching for the capacitor matrix\&. \fP" -.ti -1c -.RI "def \fB__stretchTopPlateCompactCap__\fP" -.br -.RI "\fIDraws vertical stretched layers for a given elementary capacitor\&. \fP" -.ti -1c -.RI "def \fB__setStretchingDySourceDyTarget__\fP" -.br -.RI "\fISets the abcissas of the extremities of the vertical stretching to be applied to capacitor's top plates for a given elementary capacitor in the matrix\&. \fP" -.ti -1c -.RI "def \fB__computeConnections__\fP" -.br -.RI "\fIComputes horizontal routing layers source and target abcissas for top and bottom plates connections to its associated routing track\&. \fP" -.in -1c -.SH "Detailed Description" -.PP -Routs two matched capacitors, C1 and C2, drawn in a capacitor matrix\&. - -Connections are put in place with reference to a given matching scheme\&. Elementary capacitor units are connected to horizontal and vertical routing tracks that represent top plates and bottom plates nets of C1 and C2 \&. Supported types of capacitors are Poly-Poly and Metal-Metal\&. Technologycal rules are provided by 350 nm AMS CMOS technology with three-four metal layers\&. Metal layers that are used for routing are placed similarly to horziontal-vertical (HV) symbolic Alliance CAD tool router, where horizontal metal channels are drawn in metal 2 and the vertical ones are in metal 3\&. Given a matrix of dimensions $ R*C $, the total number of vertical tracks is $ 2C+2 $ equivalent to $ C+1 $ couples, ensuring that every elementary capacitor is positioned between four vertical tracks, two from each side\&. In fact, every adjacent couple of these tracks represent top plates and bottom plates of C1 or C2 as shown in Figure 1\&. Layout An elementary capacitor unit can be a part of C1 or C2 according to the matching scheme\&. However, to respect common-centroid layout specifications, for C1 and C2 to be equal, the matrix number of colums and number of rows must be both even\&. Addionnally, the number of elementary capacitors dedicated to C1 must be equal to those dedicated to C2\&. These two conditions are tested in one of the class methods\&. An exception is raised if at least one of the two is not respected\&. -.SH "Constructor & Destructor Documentation" -.PP -.SS "def __init__ (self, vRTInstance)" - -.PP -A special method used to customize the class instance to an initial state in which : -.IP "\(bu" 2 -the class attirbutes describing positions and dimensions of the layout are computed in dedicated class methods, -.IP "\(bu" 2 -the attributes related to the capacitor matrix are copied from the \fCCapacitorStack\fP instance\&. -.PP -.PP -Position and dimensions attributes, also refered by layout variables, in Figure 2, are defined below : -.PP -\fBParameters:\fP -.RS 4 -\fIdevice\fP The \fBHurricane\fP AMS device onto which the layout is drawn\&. -.br -\fIcapacitorInstance\fP Instance of \fCCapacitorStack\fP class\&. -.br -\fIcapacitor\fP A nested list containing the matrix elements, which are \fCCapacitorUnit\fP objects\&. -.br -\fImatchingScheme\fP A nested list, with equal dimensions as \fCcapacitor\fP attribute, containing assignements of matrix elementary units to C1 and C2, identified by 1 and 2, respectively\&. Therefore, \fCself\&.matchingScheme\fP content is a succession of 1 and 2 values, defined as \\ capacitor identifiers\&. For example, given a matrix of dimensions 2x2, the matching scheme can be $ [ [1,2], [1,2] ] or [ [2,1], [2,1] ] $\&. The first sub-list dictates that the first elementary capacitor, $ C_{00} $\&. The second element $ C_{01} $ is affected to C2 and so on\&. An immediate and obvious consequence to this, is that an error is raised if \fCself\&.matchingSchem\fP and \fCself\&.capacitor\fP dimensions are not identical or if \fCself\&.matchingScheme\fP content is different from supported capacitor identifiers, '1' and '2'\&. -.br -\fIcapacitorType\fP Supported types of capacitors are MIM and PIP only\&. An exception is raised otherwise\&. -.br -\fIabutmentBox\fP The matrix's abutment box\&. -.br -\fImatrxiDim\fP The matrix dimensions, also equal to \fCself\&.matchingScheme\fP nested list dimensions\&. -.br -\fIabutmentBox_spacing\fP The spacing between elementary units in the matrix\&. It is computed in \fCCapacitorStack\fP and is reloaded in \fC\fBRoutMatchedCapacitor\fP\fP\&. \fCself\&.abutmentBox_spacing\fP includes, vertical routing tracks width and minimum allowed spacing between two adjacent ones\&. -.br -\fIhRoutingLayer_width\fP The width of horizontal routing layers in metal 2, which connect capacitors plates to vertical routing tracks\&. -.br -\fIvRoutingTrack_width\fP The width of vertical routing tracks in metal 3, which connects identical nets together ( ie : bottom plates of C1, top plates of C2, bottom plates of C2 and top plates of C2 )\&. -.br -\fIhRoutingTrack_width\fP The width of horizontal routing tracks in metal 2, which connect identical vertical routing tracks together\&. -.br -\fIminSpacing_hRoutingTrack\fP Minimum spacing between horizontal routing tracks\&. Wide metal 2 specifications are considered since metal 2 dimensions may exceed 10 $ m$\&. -.RE -.PP -\fBRemark:\fP -.RS 4 -For more information about wide metal specifications, refer to ENG-183_rev8\&.pdf technology manual\&. -.RE -.PP -\fBParameters:\fP -.RS 4 -\fIminimumPosition\fP The ordinate of the top plate's routing layer's bottom extremity after stretching\&. -.br -\fImaximumPosition\fP The ordinate of the top plate's routing layer's top extremity, also equivalent to the top plate's top extremity\&. -.br -\fIvRoutingTrackXCenter\fP A nested list of ordered dictionaries, with dimensions equal to \fCself\&.matrixDim\fP, containing abcissas of vertical routing tracks\&. All sub-lists' lengths are identical and are equal to 2\&. The first and second elements describe position of top plate track and bottom plate track, respectively\&. For example, given a matrix of dimensions 2x2, \fCself\&.vRoutingTrackXCenter\fP can be [[0, 2], [4,6], [8,10]] $ \mu m$\&. Elements of this nested list have particular indexing as described in Figure 2\&. -.br -\fIhRoutingtrackYCenter\fP A nested dictonary containing two keys, \fCtopTracks\fP and \fCbottomTracks\fP\&. Each key contains as value a dictionary describing centers' ordinates of four parallel horizontal tracks\&. The reason why four tracks are needed on top and bottom positions of the matrix is that four nets are used, two for every capacitor \fCCi\fP, were \fCi\fP is in [1,2]\&. -.br -\fIhRoutingLayerYCenter\fP A nested dicitonary containing two keys, \fCtop\fP and \fCbottom\fP\&. Each key contains as value a dictionary describing centers' ordinates of horizontal routing layers\&. -.br -\fIvRoutingTrackDict\fP A dictionary of routing tracks top and bottom extremities ordinates\&. -.br -\fItopPlateStretching\fP Since not only the same metal 2 layer is used to draw top/bottom plates connections to vertical tracks but also the two plates are superimposed, the top plate's routing tracks is stretched\&. \fCself\&.topPlateStretching\fP is therefore the length added to top plate's routing layer in order to avoid short circuits between top and bottom plates routing to vertical tracks since the same metal is used for both\&. -.RE -.PP - -.PP -References RoutMatchedCapacitor\&.capacitor, CapacitorStack\&.dummyRing, RoutMatchedCapacitor\&.dummyRing, RoutMatchedCapacitor\&.dummyRingCapacitor, RoutMatchedCapacitor\&.hRoutingLayer_width, RoutMatchedCapacitor\&.hRoutingLayerYCenter, RoutMatchedCapacitor\&.hRoutingTrack_width, RoutMatchedCapacitor\&.hRoutingtrackYCenter, CapacitorStack\&.matrixDim, VerticalRoutingTracks\&.matrixDim, RoutMatchedCapacitor\&.maximumPosition, RoutMatchedCapacitor\&.minimumPosition, RoutMatchedCapacitor\&.minSpacing_hRoutingTrack, RoutMatchedCapacitor\&.topPlateStretching, and RoutMatchedCapacitor\&.vRTInstance\&. -.SH "Member Function Documentation" -.PP -.SS "def route (self, bbMode = \fCFalse\fP)" - -.PP -Draws the complete layout given the capacitor matrix\&. \fCroute\fP method is succession of calls to user-defined methods inside a newly created \fCUpdatesession\fP\&. The following tasks are excecuted : -.IP "1." 4 -A nex \fCUpdateSession\fP is created, -.IP "2." 4 -all required physical layers are loaded, -.IP "3." 4 -technology rules are defined according to capacitor type, -.IP "4." 4 -layout dimension parameters are computed, -.IP "5." 4 -routing tracks and layers are drawn, -.IP "6." 4 -top plates are stretched, -.IP "7." 4 -all required cuts are drawn, -.IP "8." 4 -The \fCUpdateSession\fP is closed\&. -.PP -.PP -Meanwhile, an exception is raised when the entered \fCcapacitor\fP is not a capacitor matrix or if the capacitor type is unsupported\&. -.PP -References RoutMatchedCapacitor\&.__stretchTopPlates__(), RoutMatchedCapacitor\&.capacitor, RoutMatchedCapacitor\&.computeDimensions(), CapacitorUnit\&.computeDimensions(), Stack\&.computeDimensions(), RoutMatchedCapacitor\&.drawCuts(), RoutMatchedCapacitor\&.drawDummyRing_hRTracks_Cuts(), RoutMatchedCapacitor\&.drawHRLayers(), RoutMatchedCapacitor\&.drawHRoutingTracks(), CapacitorStack\&.dummyRing, RoutMatchedCapacitor\&.dummyRing, RoutMatchedCapacitor\&.dummyRingCapacitor, VerticalRoutingTracks\&.getVTrackYMax(), VerticalRoutingTracks\&.getVTrackYMin(), CapacitorUnit\&.hpitch, RoutMatchedCapacitor\&.hRoutingtrackYCenter, VerticalRoutingTracks\&.matchingScheme, CapacitorStack\&.matchingScheme, CapacitorStack\&.matrixDim, VerticalRoutingTracks\&.matrixDim, RoutMatchedCapacitor\&.maximumPosition, CapacitorUnit\&.metal3Width, RoutMatchedCapacitor\&.minimumPosition, VerticalRoutingTracks\&.nets, CapacitorStack\&.nets, RoutMatchedCapacitor\&.routeDummyRing(), RoutMatchedCapacitor\&.routeLeftAndRightSides(), RoutMatchedCapacitor\&.routeTopOrBottomSide(), RoutMatchedCapacitor\&.setLayers(), CapacitorStack\&.setRules(), CapacitorUnit\&.setRules(), RoutMatchedCapacitor\&.setRules(), CapacitorUnit\&.vpitch, VerticalRoutingTracks\&.vRoutingTrack_width, CapacitorStack\&.vRoutingTrack_width, and RoutMatchedCapacitor\&.vRoutingTrackXCenter\&. -.SS "def setRules (self)" - -.PP -Defines technology rules used to draw the layout\&. Some of the rules, namely those describing routing layers and tracks are applicable for both MIM and PIP capacitors\&. However, cuts rules are different\&. -.PP -\fBRemark:\fP -.RS 4 -All \fCCapacitorStack\fP class rules are also reloaded in this class\&. An exception is raised if the entered capacitor type is unsupported\&. -.RE -.PP -\fBReturns:\fP -.RS 4 -a dictionary with rules labels as keys and rules content as values\&. -.RE -.PP - -.PP -References CapacitorStack\&.capacitorType, CapacitorUnit\&.capacitorType, RoutMatchedCapacitor\&.capacitorType, CapacitorStack\&.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor\&.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor\&.minSpacing_hRoutingLayer, RoutMatchedCapacitor\&.minSpacing_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor\&.minSpacing_hRoutingLayer_vRoutingTrack_cut, RoutMatchedCapacitor\&.minSpacing_hRoutingTrackCut, CapacitorStack\&.minSpacing_vRoutingTrackCut, RoutMatchedCapacitor\&.minSpacing_vRoutingTrackCut, CapacitorStack\&.minWidth_hRoutingLayer_topPlate_cut, and RoutMatchedCapacitor\&.minWidth_hRoutingLayer_topPlate_cut\&. -.PP -Referenced by RoutMatchedCapacitor\&.route(), and VerticalRoutingTracks\&.setRules()\&. -.SS "def setLayers (self)" - -.PP -Defines all physical layers used to draw the layout\&. Layers are loaded using \fCDataBase\fP API\&. The same routing layers are used for both capacitor types except cuts layers that connect top plates to vertical routing tracks\&. Basicaly, metal 2, meta 3, cut 1 and cut 2 are the ones defined\&. -.PP -\fBReturns:\fP -.RS 4 -a dictionary composed of layers labels as keys and layers as values\&. -.RE -.PP - -.PP -References CapacitorStack\&.capacitorType, CapacitorUnit\&.capacitorType, RoutMatchedCapacitor\&.capacitorType, CapacitorStack\&.dummyRing, and RoutMatchedCapacitor\&.dummyRing\&. -.PP -Referenced by RoutMatchedCapacitor\&.route()\&. -.SS "def computeDimensions (self, bbMode)" - -.PP -Computes, through simple instructions and functions calls, layout variables detailed in Figure 2\&. -.PP -References CapacitorStack\&.abutmentBox_spacing, RoutMatchedCapacitor\&.abutmentBox_spacing, VerticalRoutingTracks\&.capacitorsNumber, CapacitorStack\&.capacitorsNumber, RoutMatchedCapacitor\&.computeBondingBoxDimInbbMode(), RoutMatchedCapacitor\&.computeHRLayerYCenter(), RoutMatchedCapacitor\&.computeHRoutingTrackYCenter(), RoutMatchedCapacitor\&.hRoutingLayer_width, CapacitorStack\&.matrixDim, VerticalRoutingTracks\&.matrixDim, RoutMatchedCapacitor\&.maximumPosition, CapacitorStack\&.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor\&.minEnclosure_hRoutingLayer_topPlate_cut, VerticalRoutingTracks\&.minEnclosure_hRoutingLayer_vRoutingTrack_cut, RoutMatchedCapacitor\&.minimumPosition, VerticalRoutingTracks\&.minWidth_hRoutingLayer, CapacitorStack\&.minWidth_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor\&.minWidth_hRoutingLayer_topPlate_cut, VerticalRoutingTracks\&.minWidth_hRoutingLayer_vRoutingTrack_cut, RoutMatchedCapacitor\&.vRoutingTrack_spacing, VerticalRoutingTracks\&.vRoutingTrack_width, CapacitorStack\&.vRoutingTrack_width, RoutMatchedCapacitor\&.vRoutingTrackDict, and RoutMatchedCapacitor\&.vRoutingTrackXCenter\&. -.PP -Referenced by RoutMatchedCapacitor\&.route()\&. -.SS "def computeHRoutingTrackYCenter (self)" - -.PP -Computes centers' ordinates of the eight horizontal routing tracks\&. The tracks include four on top and four on bottom of the matrix\&. To do the computations, fist, center of the first bottom or top track, given in Figure 2, is computed\&. Then, all adjacent three centers are deduced by simples translation of the first one\&. Translation quantity is equal to the sum of distance between adjacent routing tracks, self\&.hRoutingTracks_spacing, and half width of the routing track itself, \fCself\&.hRoutingTrack_width\fP\&. -.PP -References RoutMatchedCapacitor\&.__setPlatesIds__(), CapacitorUnit\&.hpitch, RoutMatchedCapacitor\&.hRoutingtrackYCenter, RoutMatchedCapacitor\&.maximumPosition, and RoutMatchedCapacitor\&.minimumPosition\&. -.PP -Referenced by RoutMatchedCapacitor\&.computeDimensions()\&. -.SS "def computeHRLayerYCenter (self)" - -.PP -Sets the stretching value of top plates\&. Then iteratively computes the centers of horizontal routing layer regarding top and bottom plates\&. -.PP -References RoutMatchedCapacitor\&.__findPossibleShortCircuits__(), VerticalRoutingTracks\&.__setStretching__(), RoutMatchedCapacitor\&.__setStretchingDySourceDyTarget__(), RoutMatchedCapacitor\&.bondingBox, RoutMatchedCapacitor\&.capacitor, RoutMatchedCapacitor\&.hRoutingLayer_width, RoutMatchedCapacitor\&.hRoutingLayerYCenter, RoutMatchedCapacitor\&.hRoutingTrack_width, RoutMatchedCapacitor\&.hRoutingtrackYCenter, CapacitorStack\&.matrixDim, VerticalRoutingTracks\&.matrixDim, RoutMatchedCapacitor\&.minSpacing_hRoutingLayer, RoutMatchedCapacitor\&.topPlateStretching, VerticalRoutingTracks\&.vRoutingTrack_width, CapacitorStack\&.vRoutingTrack_width, and RoutMatchedCapacitor\&.vRoutingTrackXCenter\&. -.PP -Referenced by RoutMatchedCapacitor\&.computeDimensions()\&. -.SS "def drawHRoutingTracks (self, routingTracksLayer)" - -.PP -Iteratively draws horizontal routing tracks on top and bottom positions of the matrix using physical layer \fCroutingTracksLayer\fP\&. -.PP -References RoutMatchedCapacitor\&.hRoutingTrack_width, RoutMatchedCapacitor\&.hRoutingtrackYCenter, VerticalRoutingTracks\&.nets, CapacitorStack\&.nets, and RoutMatchedCapacitor\&.vRoutingTrackXCenter\&. -.PP -Referenced by RoutMatchedCapacitor\&.route()\&. -.SS "def drawHRLayers (self, xPlateRLayer)" - -.PP -Iteratively draws the horizontal routing layers starting with bottom left elementary capacitor $ C_{00} $\&. -.PP -References RoutMatchedCapacitor\&.__computeConnections__(), RoutMatchedCapacitor\&.hRoutingLayer_width, RoutMatchedCapacitor\&.hRoutingLayerYCenter, VerticalRoutingTracks\&.matchingScheme, CapacitorStack\&.matchingScheme, VerticalRoutingTracks\&.matrixDim, CapacitorStack\&.matrixDim, VerticalRoutingTracks\&.nets, and CapacitorStack\&.nets\&. -.PP -Referenced by RoutMatchedCapacitor\&.route()\&. -.SS "def drawCuts (self, layer_hRTrack_hRLayer, layer_tracksCut, layer_topPlateCut)" - -.PP -Draws all required cuts using physical layers : -.IP "\(bu" 2 -\fClayer_hRTrack_hRLayer\fP to connect bottom plates to vertical routing tracks, -.IP "\(bu" 2 -\fClayer_tracksCut\fP to connect vertical routing tracks to horizontal ones, -.IP "\(bu" 2 -\fClayer_topPlateCut\fP to connect top plates to vertical routing tracks\&. ALso in \fCdrawCuts\fP, nUmber of maximum cuts number on every layer is computed and cuts enclosure is adjusted according to layer's width\&. -.PP - -.PP -References RoutMatchedCapacitor\&.__setPlatesLabels__(), VerticalRoutingTracks\&.capacitorIds, VerticalRoutingTracks\&.capacitorsNumber, CapacitorStack\&.capacitorsNumber, RoutMatchedCapacitor\&.drawCuts_stretchedTopPlate(), RoutMatchedCapacitor\&.drawCuts_vRoutingTrack_HRLayer(), RoutMatchedCapacitor\&.drawCuts_vRoutingTrack_hRoutingTrack(), RoutMatchedCapacitor\&.drawOneCut_vRoutingTrack_HRLayer(), RoutMatchedCapacitor\&.hRoutingLayerYCenter, VerticalRoutingTracks\&.matchingScheme, CapacitorStack\&.matchingScheme, VerticalRoutingTracks\&.matrixDim, CapacitorStack\&.matrixDim, CapacitorStack\&.minEnclosure_vRoutingTrackCut, RoutMatchedCapacitor\&.minSpacing_hRoutingTrackCut, CapacitorStack\&.minSpacing_vRoutingTrackCut, RoutMatchedCapacitor\&.minSpacing_vRoutingTrackCut, VerticalRoutingTracks\&.minWidth_hRoutingTrackCut, CapacitorStack\&.minWidth_vRoutingTrackCut, VerticalRoutingTracks\&.nets, CapacitorStack\&.nets, VerticalRoutingTracks\&.vRoutingTrack_width, CapacitorStack\&.vRoutingTrack_width, and RoutMatchedCapacitor\&.vRoutingTrackXCenter\&. -.PP -Referenced by RoutMatchedCapacitor\&.route()\&. -.SS "def drawOneCut_vRoutingTrack_HRLayer (self, net, cutLayer, cutXMin, cutYMin, cutNumber)" - -.PP -Draws one cut, in layer \fCcutLayer\fP, in order to connect a vertical routing track, at position \fCcutXMin\fP in metal 2, and a horizontal routing track, at position \fCcutYMin\fP in metal 3\&. -.PP -References RoutMatchedCapacitor\&.minSpacing_hRoutingLayer_vRoutingTrack_cut, and VerticalRoutingTracks\&.minWidth_hRoutingLayer_vRoutingTrack_cut\&. -.PP -Referenced by RoutMatchedCapacitor\&.drawCuts()\&. -.SS "def drawCuts_vRoutingTrack_hRoutingTrack (self, cutLayer, cutNumber, enclosure_cut)" - -.PP -Draws cuts to connect vertical routing tracks in metal 2 and horizontal routing tracks in metal 3\&. -.PP -References RoutMatchedCapacitor\&.__setPlatesIds__(), RoutMatchedCapacitor\&.capacitor, RoutMatchedCapacitor\&.dummyRingCapacitor, RoutMatchedCapacitor\&.hRoutingLayerYCenter, RoutMatchedCapacitor\&.hRoutingtrackYCenter, VerticalRoutingTracks\&.matchingScheme, CapacitorStack\&.matchingScheme, VerticalRoutingTracks\&.matrixDim, CapacitorStack\&.matrixDim, CapacitorStack\&.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor\&.minEnclosure_hRoutingLayer_topPlate_cut, CapacitorStack\&.minEnclosure_vRoutingTrackCut, RoutMatchedCapacitor\&.minSpacing_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor\&.minSpacing_hRoutingTrackCut, CapacitorStack\&.minSpacing_vRoutingTrackCut, RoutMatchedCapacitor\&.minSpacing_vRoutingTrackCut, CapacitorStack\&.minWidth_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor\&.minWidth_hRoutingLayer_topPlate_cut, VerticalRoutingTracks\&.minWidth_hRoutingTrackCut, CapacitorStack\&.minWidth_vRoutingTrackCut, VerticalRoutingTracks\&.nets, CapacitorStack\&.nets, VerticalRoutingTracks\&.vRoutingTrack_width, CapacitorStack\&.vRoutingTrack_width, and RoutMatchedCapacitor\&.vRoutingTrackXCenter\&. -.PP -Referenced by RoutMatchedCapacitor\&.drawCuts()\&. -.SS "def __stretchTopPlates__ (self, capacitor, rlayer)" - -.PP -Iteratively performs top plates stretching for the capacitor matrix\&. Vertical segments are connected to top plate routing layer\&. -.PP -\fBParameters:\fP -.RS 4 -\fIcapacitor\fP Capacitor matrix\&. -.br -\fIrlayer\fP Layer of the drawn vertical rectangle\&. -.RE -.PP - -.PP -References RoutMatchedCapacitor\&.__stretchTopPlateCompactCap__(), VerticalRoutingTracks\&.matchingScheme, CapacitorStack\&.matchingScheme, VerticalRoutingTracks\&.matrixDim, CapacitorStack\&.matrixDim, VerticalRoutingTracks\&.nets, and CapacitorStack\&.nets\&. -.PP -Referenced by RoutMatchedCapacitor\&.route()\&. -.SS "def __stretchTopPlateCompactCap__ (self, net, capacitor, routingLayer, j = \fC0\fP)" - -.PP -Draws vertical stretched layers for a given elementary capacitor\&. -.PP -References RoutMatchedCapacitor\&.__setStretchingDySourceDyTarget__(), and RoutMatchedCapacitor\&.topPlateStretching\&. -.PP -Referenced by RoutMatchedCapacitor\&.__stretchTopPlates__()\&. -.SS "def __setStretchingDySourceDyTarget__ (self, capacitor, deltay)" - -.PP -Sets the abcissas of the extremities of the vertical stretching to be applied to capacitor's top plates for a given elementary capacitor in the matrix\&. -.PP -\fBParameters:\fP -.RS 4 -\fIcapacitor\fP \&.values() Elementary unit capacitor\&. -.br -\fIdeltay\fP Stretching value\&. -.RE -.PP -\fBReturns:\fP -.RS 4 -A list that contains \fCdySource\fP and as top extremity and bottom extermity, respectively\&. -.RE -.PP - -.PP -Referenced by RoutMatchedCapacitor\&.__stretchTopPlateCompactCap__(), and RoutMatchedCapacitor\&.computeHRLayerYCenter()\&. -.SS "def __computeConnections__ (self, i, j, capacitorIdentifier)" - -.PP -Computes horizontal routing layers source and target abcissas for top and bottom plates connections to its associated routing track\&. -.PP -\fBParameters:\fP -.RS 4 -\fI(i,j)\fP row and column indexes, respectively, in the matrix which describe the elementary capacitor position in the matrix\&. -.br -\fIcapacitorIdentifier\fP equal to '1' if C1 and '2' if C2\&. -.RE -.PP -\fBReturns:\fP -.RS 4 -A nested dicitionary\&. The overal dictionary is composed of keys equal to \fCtopPlate\fP and bottomPlate and values equal to sub-dictionaries\&. The sub-dictionaries, are in their turn composed of two keys standing for the abcissa of the source and the abcissa of the target\&. -.RE -.PP -\fBRemark:\fP -.RS 4 -Naturally, an exception is raised if an unsupported capacitor identifier is given\&. -.RE -.PP - -.PP -References RoutMatchedCapacitor\&.__findHRLDyTrarget__(), RoutMatchedCapacitor\&.__isCapacitorAdummy__(), RoutMatchedCapacitor\&.__setPlatesLabels__(), RoutMatchedCapacitor\&.capacitor, VerticalRoutingTracks\&.capacitorIds, VerticalRoutingTracks\&.capacitorsNumber, CapacitorStack\&.capacitorsNumber, CapacitorStack\&.dummyElement, RoutMatchedCapacitor\&.dummyElement, CapacitorStack\&.dummyRing, RoutMatchedCapacitor\&.dummyRing, VerticalRoutingTracks\&.matchingScheme, CapacitorStack\&.matchingScheme, VerticalRoutingTracks\&.matrixDim, CapacitorStack\&.matrixDim, VerticalRoutingTracks\&.nets, CapacitorStack\&.nets, VerticalRoutingTracks\&.vRoutingTrack_width, CapacitorStack\&.vRoutingTrack_width, RoutMatchedCapacitor\&.vRoutingTrackXCenter, and RoutMatchedCapacitor\&.vRTsDistribution\&. -.PP -Referenced by RoutMatchedCapacitor\&.drawHRLayers()\&. - -.SH "Author" -.PP -Generated automatically by Doxygen for Oroshi - Analog Devices Layout from the source code\&. diff --git a/oroshi/doc/man/man3/python_CapacitorUnit_CapacitorUnit.3 b/oroshi/doc/man/man3/python_CapacitorUnit_CapacitorUnit.3 deleted file mode 100644 index d284446b..00000000 --- a/oroshi/doc/man/man3/python_CapacitorUnit_CapacitorUnit.3 +++ /dev/null @@ -1,759 +0,0 @@ -.TH "CapacitorUnit" 3 "Thu Mar 19 2020" "Version 1.0" "Oroshi - Analog Devices Layout" \" -*- nroff -*- -.ad l -.nh -.SH NAME -CapacitorUnit \- -.PP -Draws a capacitor of type Poly-Poly or Metal-Metal in 350 nm AMS CMOS technology\&. - -.SH SYNOPSIS -.br -.PP -.SS "Public Member Functions" - -.in +1c -.ti -1c -.RI "def \fB__init__\fP" -.br -.RI "\fIThis is the class constructor\&. \fP" -.ti -1c -.RI "def \fB__setCapacitorPerUnit__\fP" -.br -.RI "\fISets the area and perimeter capacitances as specified in 350 nm AMS technology and according to \fCcapacitorType\fP (MIM or PIP)\&. \fP" -.ti -1c -.RI "def \fB__computeCapDim__\fP" -.br -.RI "\fIComputes width and length of the capacitor\&. \fP" -.ti -1c -.RI "def \fB__isCapacitorUnitOK__\fP" -.br -.RI "\fIChecks if the computed capacitor dimensions exceed or are less than maximum and minimum limits, respectively, as specified in technology rules\&. \fP" -.ti -1c -.RI "def \fBsetRules\fP" -.br -.RI "\fISelects technological rules according to the capacitor type\&. \fP" -.ti -1c -.RI "def \fBgetCapacitorType\fP" -.br -.ti -1c -.RI "def \fBgetMaximumCapWidth\fP" -.br -.RI "\fImaximum size of capacitor's top plate\&. \fP" -.ti -1c -.RI "def \fBgetMinimumCapWidth\fP" -.br -.ti -1c -.RI "def \fBgetLayers\fP" -.br -.RI "\fILoads the technology file then extracts the adequate layers according to the capacitor type (MIM or PIP)\&. \fP" -.ti -1c -.RI "def \fBcreate\fP" -.br -.RI "\fIWhen bonding box mode is activated, the function draws all layout physical layers of the capacitor after checking its dimensions\&. \fP" -.ti -1c -.RI "def \fBdrawCapacitor\fP" -.br -.RI "\fIDraws all layout physicial layers of the capacitor\&. \fP" -.ti -1c -.RI "def \fBcomputeBottomPlateCuts\fP" -.br -.RI "\fIComputes needed parameters to draw bottom plate cuts in its exact position, including : \fP" -.ti -1c -.RI "def \fBcomputeTopPlateCuts\fP" -.br -.RI "\fIComputes needed parameters to draw top plate cuts in its exact position, including : \fP" -.ti -1c -.RI "def \fBdrawAbutmentBox\fP" -.br -.RI "\fIDraws the abutment box of the capacitor in position \fC<\fP(abutmentBoxXMin, abutmentBoxYMin)>\&. \fP" -.ti -1c -.RI "def \fBdrawOnePlate\fP" -.br -.RI "\fIDraws the top or bottom plate through inflation of the Box under it\&. \fP" -.ti -1c -.RI "def \fBdrawBottomPlateCut\fP" -.br -.RI "\fIDraws the required cuts to connect the bottom plate\&. \fP" -.ti -1c -.RI "def \fBdrawTopPlateCut\fP" -.br -.RI "\fIDraws the top plate's cuts after computing the maximal number of cuts that can be placed and its exact enclosure in the top plate\&. \fP" -.ti -1c -.RI "def \fBdrawRoutingLayers\fP" -.br -.RI "\fIDraws the routing layers of both bottom and top plates after computing widths and the exact position of these layers\&. \fP" -.ti -1c -.RI "def \fBcutMaxNumber\fP" -.br -.RI "\fIComputes the maximal number of cuts to be placed on a layer of width \fCwidth_layer\fP considering specifications such as the spacing between the cuts, its width and its enclosure in the layer\&. \fP" -.ti -1c -.RI "def \fBcutLine\fP" -.br -.RI "\fICreates a horizontal or vertical line of contacts according to the specified direction\&. \fP" -.ti -1c -.RI "def \fBcutMatrix\fP" -.br -.RI "\fICreates a matrix of cuts by vertically stacking horizontal lines of identical cuts\&. \fP" -.ti -1c -.RI "def \fBgetBottomPlateYMax\fP" -.br -.ti -1c -.RI "def \fBgetBottomPlateLeftCutXMin\fP" -.br -.ti -1c -.RI "def \fBgetBottomPlateLeftCutYMin\fP" -.br -.ti -1c -.RI "def \fBgetBottomPlateLeftCutYMax\fP" -.br -.ti -1c -.RI "def \fBgetBottomPlateRightCutXMin\fP" -.br -.ti -1c -.RI "def \fBgetBottomPlateRightCutYMin\fP" -.br -.ti -1c -.RI "def \fBgetBottomPlateRightCutYMax\fP" -.br -.ti -1c -.RI "def \fBgetBotPlateLeftRLayerXMax\fP" -.br -.ti -1c -.RI "def \fBgetBottomPlateRightCutYCenter\fP" -.br -.ti -1c -.RI "def \fBgetBotPlateLeftRLayerXMin\fP" -.br -.ti -1c -.RI "def \fBgetBotPlateRLayerYMin\fP" -.br -.ti -1c -.RI "def \fBgetBotPlateRLayerYMax\fP" -.br -.ti -1c -.RI "def \fBgetBotPlateRLayerWidth\fP" -.br -.ti -1c -.RI "def \fBgetBotPlateRightRLayerXCenter\fP" -.br -.ti -1c -.RI "def \fBgetBotPlateLeftRLayerXCenter\fP" -.br -.ti -1c -.RI "def \fBgetTopPlateRLayerYMin\fP" -.br -.ti -1c -.RI "def \fBgetTopPlateRLayerYMax\fP" -.br -.ti -1c -.RI "def \fBgetTopPlateRLayerWidth\fP" -.br -.ti -1c -.RI "def \fBgetTopPlateRLayerXCenter\fP" -.br -.ti -1c -.RI "def \fBgetTopPlateRLayerXMin\fP" -.br -.ti -1c -.RI "def \fBgetTopPlateRLayerXMax\fP" -.br -.in -1c -.SH "Detailed Description" -.PP -Draws a capacitor of type Poly-Poly or Metal-Metal in 350 nm AMS CMOS technology\&. - -PIP and MIM capacitors are the result of surface superposition between poly1 and poly2 or metal2 and metalcap layers, respectively\&. Given the capacitor value, layout dimensions are computed, then, capacitor layers are drawn\&. Capacitor value, $C$, is given in the expression below, where $ C_{a}, C_{p}, A $ and $ P $ are, area capacitance, perimeter capacitance, area and permiter of the capacitor, respectively : \[ C = C_{a}A + C_{p}P \] The drawn layout shape is square\&. Thus, metcap or poly2 length and width are equal and are computed using the capacitor expression\&. Furthermore, given $ C_{a} $, $ C_{p} $ and enclosure technological rules, dimensions and positions of the abutment box as well as the bottom plate are computed\&. Layouts with dimensions that exceed technological limits cannot be drawn\&. -.SH "Constructor & Destructor Documentation" -.PP -.SS "def __init__ (self, device, capacitorType, abutmentBoxPosition, capacitance = \fC0\fP, capDim = \fC{}\fP)" - -.PP -This is the class constructor\&. Few of the class attributes final values are computed in this level\&. Most of attributes are only initialized to zero or empty values\&. Then, it is computed in dedicated class method\&. Input parameters are : -.PP -\fBParameters:\fP -.RS 4 -\fIdevice\fP \fBHurricane\fP AMS device into which layout is drawn\&. -.br -\fIcapacitance\fP Capacitor value, expressed in $ femto Farad (fF) $\&. -.br -\fIabutmentBoxPosition\fP A list containing abscissa and ordinate of the bottom left corner of the abutment box\&. -.RE -.PP -Class attributes are described in the list below\&. Most of class attributes refer to layout dimensions\&. Dictionaries are used to group attributes related to the same layout varibale\&. Layout dimensions and variables are described in Figure 1\&. -.PP -\fBParameters:\fP -.RS 4 -\fIdevice\fP \fBHurricane\fP AMS device into which layout is drawn\&. -.br -\fIcapacitance\fP Capacitor value, expressed in $ femto Farad (fF) $\&. -.br -\fIcapacitorType\fP Can be 'MIMCap' or 'PIPCap' as capacitor type\&. -.br -\fIabutmentBoxDict\fP A dictionary containing abscissa and ordinate of the bottom left corner of the abutment box, (XMin) and (YMin), respectively\&. -.br -\fIabutmentBox\fP Abutment box drawn square\&. It is an object of type \fCBox\fP\&. -.br -\fIbottomPlateBox\fP Bottom plate drawn square\&. It is an object of type \fCBox\fP\&. -.br -\fItopPlateBox\fP Top plate drawn square\&. It is an object of type \fCBox\fP\&. -.br -\fIcut2MatrixDict\fP A dictionary containing center position of the left bottom, which is cut the first to be drawn in the matrix of cuts\&. Initially, the dictionary is empty\&. It is only updated when \fCself\&.capacitorType\fP is equal to \fC'MIMCap'\fP\&. -.br -\fIcutLeftLineDict\fP A dictionary containing abcissa and ordinate of the bottom cut in the left line of cuts to be drawn on bottom plate's layer\&. -.br -\fIcutRightLineDict\fP A dictionary containing abcissa and ordinate of the bottom cut in the right line of cuts to be drawn on bottom plate's layer\&. -.br -\fItopCutLineDict\fP A dictionary containing abcissa and ordinate of the bottom cut in the right line of cuts to be drawn on top plate's layer\&. Initially, the dictionary is empty\&. It is only updated when \fCself\&.capacitorType\fP is equal to \fC'PIPCap'\fP\&. -.br -\fItopPlateRLayerDict\fP A dictionary containing position information of the top plate's routing layer\&. The dictionary includes ordinates of the layer's top and bottom extremities, \fC'XMin'\fP and \fC'YMin'\fP, respectively, the abcissa of it's center, \fC'XCenter'\fP and its width, \fC'width'\fP\&. -.br -\fIbottomPlateRLayerDict\fP A dictionary containing -.br -\fIenclosure_botPlate_topPlate\fP Top plate's layer encolusre in bottom plate's layer\&. -.br -\fIminheight_topPlatecut\fP Minimum height of cuts for top plate connection to other metal layer\&. -.br -\fItopCutLineNumber\fP Maximum possible number cuts to be drawn for top plate's connection\&. -.br -\fIbottomCutLineNumber\fP Maximum possible number cuts to be drawn for top plate's connection\&. -.RE -.PP -\fBRemark:\fP -.RS 4 -Abutment box must be defined as an attribute because the position of dummy capacitor in \fCNonUnitCapacitor\fP class must be precisely defined\&. -.RE -.PP - -.PP -References CapacitorUnit\&.__computeCapacitance__(), CapacitorUnit\&.__computeCapDim__(), CapacitorUnit\&.__initCapDim__(), CapacitorUnit\&.abutmentBox, CapacitorUnit\&.abutmentBoxDict, CapacitorUnit\&.bottomCutLineNumber, CapacitorUnit\&.bottomPlateBox, CapacitorUnit\&.bottomPlateBoxDict, CapacitorUnit\&.bottomPlateRLayerDict, CapacitorUnit\&.capacitorType, CapacitorUnit\&.capDim, CapacitorUnit\&.cut2MatrixDict, CapacitorUnit\&.cutLeftLineDict, CapacitorUnit\&.cutRightLineDict, CapacitorUnit\&.device, Stack\&.device, CapacitorUnit\&.enclosure_botPlate_abtBox, CapacitorUnit\&.enclosure_botPlate_topPlate, CapacitorUnit\&.minheight_topPlatecut, CapacitorUnit\&.topCutLineDict, CapacitorUnit\&.topCutLineNumber, CapacitorUnit\&.topPlateBox, CapacitorUnit\&.topPlateBoxDict, and CapacitorUnit\&.topPlateRLayerDict\&. -.SH "Member Function Documentation" -.PP -.SS "def __setCapacitorPerUnit__ (self, capacitorType)" - -.PP -Sets the area and perimeter capacitances as specified in 350 nm AMS technology and according to \fCcapacitorType\fP (MIM or PIP)\&. -.PP -\fBReturns:\fP -.RS 4 -a list containing the area and perimeter capacitances\&. -.RE -.PP -\fBRemarks:\fP -.RS 4 -An exception is raised if the entered capacitor type is unknown\&. -.RE -.PP - -.PP -Referenced by CapacitorUnit\&.__computeCapDim__()\&. -.SS "def __computeCapDim__ (self, capacitance, capacitorType)" - -.PP -Computes width and length of the capacitor\&. Given \fCcapacitance\fP value as well as the permiter and area capacitances, a quadratic equation is solved where the unknown parameter is the width (also equivalent to the length)\&. -.PP -\fBReturns:\fP -.RS 4 -a dictionary containing width and length\&. -.RE -.PP -\fBRemark:\fP -.RS 4 -The capacitor is square\&. Thus, length and width are equal\&. -.RE -.PP - -.PP -References CapacitorUnit\&.__setCapacitorPerUnit__()\&. -.PP -Referenced by CapacitorStack\&.__init__(), and CapacitorUnit\&.__init__()\&. -.SS "def __isCapacitorUnitOK__ (self, capDim)" - -.PP -Checks if the computed capacitor dimensions exceed or are less than maximum and minimum limits, respectively, as specified in technology rules\&. -.PP -\fBReturns:\fP -.RS 4 -\fCTrue\fP if all rules are respected\&. -.RE -.PP -\fBRemark:\fP -.RS 4 -Maximum poly2 layer dimensions for PIP capacitor are not specified in technology rules\&. Thus, only minimum limit condition is checked\&. -.RE -.PP - -.PP -References CapacitorUnit\&.capacitorType, CapacitorUnit\&.getMaximumCapWidth(), and CapacitorUnit\&.getMinimumCapWidth()\&. -.PP -Referenced by CapacitorStack\&.__init__(), and CapacitorUnit\&.create()\&. -.SS "def setRules (self)" - -.PP -Selects technological rules according to the capacitor type\&. -.PP -\fBReturns:\fP -.RS 4 -a dictionary with rules labels as keys and rules as values\&. Example of technology rules are : -.IP "\(bu" 2 -minimum spacing between cuts or metals, -.IP "\(bu" 2 -minimum width of a plate, a cut or a routing metal\&. -.IP "\(bu" 2 -etc\&. Every rule takes two possible value according to the capacitor type (MIM or PIP)\&. Therefore, dictionary keys are generic and its values are specific to the capacitor type\&. -.PP -.RE -.PP -\fBRemark:\fP -.RS 4 -An exception is raised if the entered capacitor type is unknown\&. -.RE -.PP - -.PP -References CapacitorUnit\&.capacitorType, CapacitorUnit\&.hpitch, CapacitorUnit\&.isVH, Stack\&.isVH, CapacitorUnit\&.METAL2Pitch, CapacitorUnit\&.metal2Width, CapacitorUnit\&.METAL3Pitch, CapacitorUnit\&.metal3Width, CapacitorUnit\&.minEnclo_botPlate_botPlateCut, CapacitorUnit\&.minEnclo_botPlateRMetal_botPlateCut, CapacitorUnit\&.minEnclo_routingTrackMetal_cut, CapacitorUnit\&.minEnclo_topPlate_topPlateCut, CapacitorUnit\&.minEnclo_topPlateRMetal_topPlateCut, CapacitorUnit\&.minheight_topPlatecut, CapacitorUnit\&.minSpacing_botPlate, CapacitorUnit\&.minSpacing_botPlateCut_topPlate, CapacitorUnit\&.minSpacingOnBotPlate_cut, CapacitorUnit\&.minSpacingOnTopPlate_cut, CapacitorUnit\&.minWidth_botPlatecut, CapacitorUnit\&.minWidth_botRMetal, CapacitorUnit\&.minWidth_routingTrackcut, CapacitorUnit\&.minWidth_topPlate, CapacitorUnit\&.minWidth_topPlatecut, CapacitorUnit\&.minWidth_topRMetal, and CapacitorUnit\&.vpitch\&. -.PP -Referenced by CapacitorStack\&.create(), CapacitorUnit\&.create(), RoutMatchedCapacitor\&.route(), and VerticalRoutingTracks\&.setRules()\&. -.SS "def getCapacitorType (self)" - -.PP -\fBReturns:\fP -.RS 4 -capacitor type \fC'MIMCap'\fP or \fC'PIPCap'\fP\&. -.RE -.PP -\fBRemarks:\fP -.RS 4 -\fC\fBgetCapacitorType()\fP\fP is especially useful when an instance of \fC\fBCapacitorUnit\fP\fP class is called in another classes instances to identify the capacitor's type\&. -.RE -.PP - -.SS "def getMaximumCapWidth (self)" - -.PP -maximum size of capacitor's top plate\&. \fC\fBgetMaximumCapWidth()\fP\fP is called to check if capacitor dimensions are within acceptable technological limits\&. An exception is raised if the entered capacitor type is unknown\&. -.PP -\fBRemarks:\fP -.RS 4 -1\&. This function is especially usefull in drawing the layout of a unity capacitor, where it is important to garantee that the capacitor size does not exeed the maximum possible value\&. It is also useful when drawing a matrix of capacitors to make sure that also the unity capacitor respects the maximal values specified\&. -.PP -2\&. The maximum value of the poly2 size in PIP capacitor is not specified\&. Thus, it is not considered in \fC\fBgetMaximumCapWidth()\fP\fP -.RE -.PP - -.PP -References CapacitorUnit\&.capacitorType\&. -.PP -Referenced by CapacitorUnit\&.__isCapacitorUnitOK__()\&. -.SS "def getMinimumCapWidth (self)" - -.PP -\fBReturns:\fP -.RS 4 -The minimum size of the capacitor's top plate\&. An exception is raised if the entered capacitor type is unknown\&. -.RE -.PP -\fBRemarks:\fP -.RS 4 -This function is especially usefull in drawing the layout of a matrix of capacitors where it is important to ensure that the unity capacitor respects the minimal values specified\&. -.PP -An exception is raised if the entered capacitor type is unknown\&. -.RE -.PP - -.PP -References CapacitorUnit\&.capacitorType\&. -.PP -Referenced by CapacitorUnit\&.__isCapacitorUnitOK__()\&. -.SS "def getLayers (self)" - -.PP -Loads the technology file then extracts the adequate layers according to the capacitor type (MIM or PIP)\&. -.PP -\fBReturns:\fP -.RS 4 -a dictionary containing the layer labels as attributes and its values\&. -.RE -.PP -\fBRemarks:\fP -.RS 4 -An exception is raised if the entered capacitor type is unknown\&. -.RE -.PP - -.PP -References CapacitorUnit\&.capacitorType\&. -.PP -Referenced by CapacitorUnit\&.create()\&. -.SS "def create (self, t, b, bbMode = \fCFalse\fP, vEnclosure_botPlate_abtBox = \fCNone\fP, hEnclosure_botPlate_abtBox = \fCNone\fP)" - -.PP -When bonding box mode is activated, the function draws all layout physical layers of the capacitor after checking its dimensions\&. All functions are excecuted in a new Update Session\&. In the contrary, only an exact estimation of layout dimensions is given\&. An error is raised when dimensions reach technological limits for MIM and PIP capacitors or when \fCbbMode\fP parameters is other than \fCTrue\fP or \fCFalse\fP\&. -.PP -\fBParameters:\fP -.RS 4 -\fI(\fP t , b ) nets of top and bottom plates, respectively -.br -\fIbbMode\fP activates bonding box dimensions computing when set to \fCTrue\fP -.RE -.PP - -.PP -References CapacitorUnit\&.__isCapacitorUnitOK__(), CapacitorUnit\&.abutmentBoxDict, CapacitorUnit\&.capDim, CapacitorUnit\&.computeDimensions(), Stack\&.computeDimensions(), CapacitorUnit\&.drawAbutmentBox(), CapacitorUnit\&.drawCapacitor(), Technology\&.getLayers(), CapacitorUnit\&.getLayers(), and CapacitorUnit\&.setRules()\&. -.SS "def drawCapacitor (self, layerDict, t, b)" - -.PP -Draws all layout physicial layers of the capacitor\&. -.PP -\fBParameters:\fP -.RS 4 -\fIlayerDict\fP a dictionary containing a description of the required physical layers according to capacitor type -.br -\fI(\fP t , b ) nets of top and bottom plates, respectively -.RE -.PP - -.PP -References CapacitorUnit\&.bottomPlateBox, CapacitorUnit\&.bottomPlateBoxDict, CapacitorUnit\&.drawBottomPlateCut(), CapacitorUnit\&.drawOnePlate(), CapacitorUnit\&.drawRoutingLayers(), CapacitorUnit\&.drawTopPlateCut(), CapacitorUnit\&.topPlateBox, and CapacitorUnit\&.topPlateBoxDict\&. -.PP -Referenced by CapacitorUnit\&.create()\&. -.SS "def computeBottomPlateCuts (self)" - -.PP -Computes needed parameters to draw bottom plate cuts in its exact position, including : -.IP "\(bu" 2 -maximum number of cuts to draw on both sides of bottom plate, -.IP "\(bu" 2 -adjusted enclosure of -.IP "\(bu" 2 -abcissas of the two bottom cuts on left and right sides of bottom plate, -.IP "\(bu" 2 -ordinate of the same two cuts\&. -.PP -.PP -Given parameters described above, it is possible to draw the entire lines of cuts on both sides of bottom plate using \fCcutLine\fP function\&. -.PP -References CapacitorUnit\&.bottomCutLineNumber, CapacitorUnit\&.bottomPlateBoxDict, CapacitorUnit\&.cutLeftLineDict, CapacitorUnit\&.cutMaxNumber(), CapacitorUnit\&.cutRightLineDict, CapacitorUnit\&.minEnclo_botPlate_botPlateCut, CapacitorUnit\&.minheight_topPlatecut, CapacitorUnit\&.minSpacing_botPlateCut_topPlate, CapacitorUnit\&.minSpacingOnBotPlate_cut, CapacitorUnit\&.minWidth_topPlatecut, and CapacitorUnit\&.topPlateBoxDict\&. -.PP -Referenced by CapacitorUnit\&.drawAbutmentBox()\&. -.SS "def computeTopPlateCuts (self)" - -.PP -Computes needed parameters to draw top plate cuts in its exact position, including : -.IP "\(bu" 2 -maximum number of cuts to draw on both sides of top plate, -.IP "\(bu" 2 -adjusted enclosure of -.IP "\(bu" 2 -abcissas of the two top cuts on left and right sides of top plate, -.IP "\(bu" 2 -ordinate of the same two cuts\&. -.PP -.PP -Given parameters described above, it is possible to draw the entire lines of cuts on both sides of bottom plate using \fCcutLine\fP function\&. -.PP -References CapacitorUnit\&.abutmentBoxDict, CapacitorUnit\&.bottomPlateBoxDict, CapacitorUnit\&.bottomPlateRLayerDict, CapacitorUnit\&.capacitorType, CapacitorUnit\&.cut2MatrixDict, CapacitorUnit\&.cutLeftLineDict, CapacitorUnit\&.cutMaxNumber(), CapacitorUnit\&.cutRightLineDict, CapacitorUnit\&.enclosure_botPlate_topPlate, CapacitorUnit\&.hEnclosure_botPlate_abtBox, CapacitorUnit\&.minEnclo_botPlate_botPlateCut, CapacitorUnit\&.minEnclo_botPlateRMetal_botPlateCut, CapacitorUnit\&.minEnclo_routingTrackMetal_cut, CapacitorUnit\&.minEnclo_topPlate_topPlateCut, CapacitorUnit\&.minEnclo_topPlateRMetal_topPlateCut, CapacitorUnit\&.minheight_topPlatecut, CapacitorUnit\&.minSpacing_botPlate, CapacitorUnit\&.minSpacing_botPlateCut_topPlate, CapacitorUnit\&.minSpacingOnTopPlate_cut, CapacitorUnit\&.minWidth_botPlatecut, CapacitorUnit\&.minWidth_botRMetal, CapacitorUnit\&.minWidth_routingTrackcut, CapacitorUnit\&.minWidth_topPlatecut, CapacitorUnit\&.setBottomPlateAbtBoxEnclosure(), CapacitorUnit\&.topCutLineDict, CapacitorUnit\&.topCutLineNumber, CapacitorUnit\&.topPlateBoxDict, CapacitorUnit\&.topPlateRLayerDict, and CapacitorUnit\&.vEnclosure_botPlate_abtBox\&. -.PP -Referenced by CapacitorUnit\&.drawAbutmentBox()\&. -.SS "def drawAbutmentBox (self)" - -.PP -Draws the abutment box of the capacitor in position \fC<\fP(abutmentBoxXMin, abutmentBoxYMin)>\&. First, the minimum enclosure of the top plate inside the bottom plate is computed\&. Second, using this parameters as well as the capacitor dimensions, the width and height of the abutment box are computed\&. The box is finally drawn\&. -.PP -References CapacitorUnit\&.abutmentBox, CapacitorUnit\&.abutmentBoxDict, CapacitorUnit\&.bottomPlateBoxDict, CapacitorUnit\&.computeAbutmentBoxDimensions(), CapacitorUnit\&.computeBottomPlateCuts(), CapacitorUnit\&.computeOnePlateBoxDimensions(), CapacitorUnit\&.computeRoutingLayersDimensions(), CapacitorUnit\&.computeTopPlateCuts(), CapacitorUnit\&.enclosure_botPlate_topPlate, CapacitorUnit\&.hEnclosure_botPlate_abtBox, CapacitorUnit\&.topPlateBoxDict, and CapacitorUnit\&.vEnclosure_botPlate_abtBox\&. -.PP -Referenced by CapacitorStack\&.create(), and CapacitorUnit\&.create()\&. -.SS "def drawOnePlate (self, layer, net, boxDimensions)" - -.PP -Draws the top or bottom plate through inflation of the Box under it\&. These boxes are the abutment box in the case of the bottom plate and the bottom plate's box in the case of the top plate\&. This function also creates a a net for the drawn plate and sets it as external\&. -.PP -\fBReturns:\fP -.RS 4 -The drawn box\&. -.RE -.PP - -.PP -Referenced by CapacitorUnit\&.drawCapacitor()\&. -.SS "def drawBottomPlateCut (self, layer, b)" - -.PP -Draws the required cuts to connect the bottom plate\&. First, the maximal possible number of cuts that can be drawn is computed\&. Second, using the computed number, the enclosure of this cuts in the bottom plate's layer is adjusted while the minimal enclosure is respected\&. Third, the relative positions of the cuts on both sides of the plate are computed\&. Finally, two vertical lines of cuts are drawns\&. -.PP -\fBRemark:\fP -.RS 4 -The relative positions describe the cordinates of the first bottom cut in every line of cuts\&. Then, knowing the spacing and width specifications of these cuts the rest of the line is easilly constructed\&. -.RE -.PP - -.PP -References CapacitorUnit\&.bottomCutLineNumber, CapacitorUnit\&.cutLeftLineDict, CapacitorUnit\&.cutLine(), CapacitorUnit\&.cutRightLineDict, CapacitorUnit\&.minheight_topPlatecut, CapacitorUnit\&.minSpacingOnBotPlate_cut, and CapacitorUnit\&.minWidth_botPlatecut\&. -.PP -Referenced by CapacitorUnit\&.drawCapacitor()\&. -.SS "def drawTopPlateCut (self, layer, t)" - -.PP -Draws the top plate's cuts after computing the maximal number of cuts that can be placed and its exact enclosure in the top plate\&. -.PP -References CapacitorUnit\&.capacitorType, CapacitorUnit\&.cut2MatrixDict, CapacitorUnit\&.cutLine(), CapacitorUnit\&.cutMatrix(), CapacitorUnit\&.minheight_topPlatecut, CapacitorUnit\&.minSpacingOnTopPlate_cut, CapacitorUnit\&.minWidth_topPlatecut, CapacitorUnit\&.topCutLineDict, and CapacitorUnit\&.topCutLineNumber\&. -.PP -Referenced by CapacitorUnit\&.drawCapacitor()\&. -.SS "def drawRoutingLayers (self, bottomPlateLayer, topPlateLayer, t, b)" - -.PP -Draws the routing layers of both bottom and top plates after computing widths and the exact position of these layers\&. Also computes positions if rlayers that are crucial for routing\&. -.PP -References CapacitorUnit\&.bottomPlateRLayerDict, CapacitorUnit\&.cutLeftLineDict, CapacitorUnit\&.cutRightLineDict, and CapacitorUnit\&.topPlateRLayerDict\&. -.PP -Referenced by CapacitorUnit\&.drawCapacitor()\&. -.SS "def cutMaxNumber (self, width_layer, width_cut, spacing_cut, enclosure_cut)" - -.PP -Computes the maximal number of cuts to be placed on a layer of width \fCwidth_layer\fP considering specifications such as the spacing between the cuts, its width and its enclosure in the layer\&. -.PP -Referenced by CapacitorUnit\&.computeBottomPlateCuts(), and CapacitorUnit\&.computeTopPlateCuts()\&. -.SS "def cutLine (self, net, layer, firstCutXCenter, firstCutYCenter, width_cut, height_cut, spacing_cut, cutNumber, direction)" - -.PP -Creates a horizontal or vertical line of contacts according to the specified direction\&. -.PP -Referenced by CapacitorUnit\&.cutMatrix(), CapacitorUnit\&.drawBottomPlateCut(), and CapacitorUnit\&.drawTopPlateCut()\&. -.SS "def cutMatrix (self, net, layer, firstCutXCenter, firstCutYCenter, width_cut, height_cut, spacing_cut, cutColumnNumber, cutRowNumber)" - -.PP -Creates a matrix of cuts by vertically stacking horizontal lines of identical cuts\&. -.PP -\fBParameters:\fP -.RS 4 -\fInet\fP net to which the cuts belong -.br -\fIlayer\fP cuts physical layer -.br -\fIfirstCutXCenter\fP center's abcissa of the bottom left cut ( that is the first cut to be drawn in the matrix ) -.br -\fIfirstCutYCenter\fP center's abcissa of the bottom left cut -.br -\fI(width_cut,height_cut,spacing_cut)\fP cuts dimenions -.br -\fI(cutColumnNumber,cutRowNumber)\fP matrix dimensions -.RE -.PP -\fBRemarks:\fP -.RS 4 -The matrix can have any dimensions zero or negative one\&. -.RE -.PP - -.PP -References CapacitorUnit\&.cutLine()\&. -.PP -Referenced by CapacitorUnit\&.drawTopPlateCut()\&. -.SS "def getBottomPlateYMax (self)" - -.PP -\fBReturns:\fP -.RS 4 -the ordinate of the bottom plate's highest end-point ( that is equivalent to \fCdySource\fP of the bottom plate's box ) \&. -.RE -.PP - -.PP -References CapacitorUnit\&.bottomPlateBoxDict\&. -.SS "def getBottomPlateLeftCutXMin (self)" - -.PP -\fBReturns:\fP -.RS 4 -the abcissa of the bottom plate's left line of cuts\&. -.RE -.PP - -.SS "def getBottomPlateLeftCutYMin (self)" - -.PP -\fBReturns:\fP -.RS 4 -the ordinate of the first ( or bottom) cut in the left line of cuts on the bottom plate\&. -.RE -.PP - -.SS "def getBottomPlateLeftCutYMax (self)" - -.PP -\fBReturns:\fP -.RS 4 -the ordinate of the highest cut of the bottom plate's left line of cuts\&. -.RE -.PP - -.PP -References CapacitorUnit\&.bottomCutLineNumber, CapacitorUnit\&.minSpacingOnBotPlate_cut, and CapacitorUnit\&.minWidth_botPlatecut\&. -.SS "def getBottomPlateRightCutXMin (self)" - -.PP -\fBReturns:\fP -.RS 4 -the absissa of the bottom plate's right line of cuts\&. -.RE -.PP - -.SS "def getBottomPlateRightCutYMin (self)" - -.PP -\fBReturns:\fP -.RS 4 -the ordinate of the first ( or bottom) cut in the right line of cuts on the bottom plate\&. -.RE -.PP - -.PP -Referenced by CapacitorUnit\&.getBottomPlateRightCutYCenter()\&. -.SS "def getBottomPlateRightCutYMax (self)" - -.PP -\fBReturns:\fP -.RS 4 -the ordinate of the highest ( or top) cut in the right line of cuts on the bottom plate\&. -.RE -.PP - -.PP -References CapacitorUnit\&.bottomCutLineNumber, CapacitorUnit\&.minSpacingOnBotPlate_cut, and CapacitorUnit\&.minWidth_botPlatecut\&. -.PP -Referenced by CapacitorUnit\&.getBottomPlateRightCutYCenter()\&. -.SS "def getBotPlateLeftRLayerXMax (self)" - -.PP -\fBReturns:\fP -.RS 4 -the center's ordinate of the bottom plate's left cut (the cut that is the first one in the line)\&. -.RE -.PP - -.SS "def getBottomPlateRightCutYCenter (self)" - -.PP -\fBReturns:\fP -.RS 4 -the position of the bottom plate's right cuts on the horitontal axis (also applicable to left cuts)\&. -.RE -.PP - -.PP -References CapacitorUnit\&.getBottomPlateRightCutYMax(), and CapacitorUnit\&.getBottomPlateRightCutYMin()\&. -.SS "def getBotPlateLeftRLayerXMin (self)" - -.PP -\fBReturns:\fP -.RS 4 -the position of the bottom plate's left cuts on the horitontal axis\&. -.RE -.PP - -.SS "def getBotPlateRLayerYMin (self)" - -.PP -\fBReturns:\fP -.RS 4 -the position of bottom plate's left cuts on the horitontal axis\&. -.RE -.PP - -.SS "def getBotPlateRLayerYMax (self)" - -.PP -\fBReturns:\fP -.RS 4 -the position of bottom plate's left cuts on the horitontal axis\&. -.RE -.PP - -.SS "def getBotPlateRLayerWidth (self)" - -.PP -\fBReturns:\fP -.RS 4 -the position of bottom plate's left cuts on the horitontal axis\&. -.RE -.PP - -.SS "def getBotPlateRightRLayerXCenter (self)" - -.PP -\fBReturns:\fP -.RS 4 -the position of bottom plate's left cuts on the horitontal axis\&. -.RE -.PP - -.SS "def getBotPlateLeftRLayerXCenter (self)" - -.PP -\fBReturns:\fP -.RS 4 -the position of bottom plate's left cuts on the horitontal axis\&. -.RE -.PP - -.SS "def getTopPlateRLayerYMin (self)" - -.PP -\fBReturns:\fP -.RS 4 -the ordinate of the bottom end points of the top plate routing layer\&. -.RE -.PP - -.SS "def getTopPlateRLayerYMax (self)" - -.PP -\fBReturns:\fP -.RS 4 -the ordinate of the higher end points of the top plate routing layer\&. -.RE -.PP - -.SS "def getTopPlateRLayerWidth (self)" - -.PP -\fBReturns:\fP -.RS 4 -the width of top plate's routing layer\&. -.RE -.PP - -.SS "def getTopPlateRLayerXCenter (self)" - -.PP -\fBReturns:\fP -.RS 4 -the center's abcissa of the bottom plate routing layer\&. -.RE -.PP - -.SS "def getTopPlateRLayerXMin (self)" - -.PP -\fBReturns:\fP -.RS 4 -the origin (bottom-left end point) abcissa of the top plate routing layers\&. -.RE -.PP - -.PP -References CapacitorUnit\&.topPlateRLayerDict\&. -.SS "def getTopPlateRLayerXMax (self)" - -.PP -\fBReturns:\fP -.RS 4 -the abscissa of the bottom-right end-point of the top plate routing layer\&. -.RE -.PP - -.PP -References CapacitorUnit\&.topPlateRLayerDict\&. - -.SH "Author" -.PP -Generated automatically by Doxygen for Oroshi - Analog Devices Layout from the source code\&. diff --git a/oroshi/doc/man/man3/python_CapacitorVRTracks_VerticalRoutingTracks.3 b/oroshi/doc/man/man3/python_CapacitorVRTracks_VerticalRoutingTracks.3 deleted file mode 100644 index 3105c43e..00000000 --- a/oroshi/doc/man/man3/python_CapacitorVRTracks_VerticalRoutingTracks.3 +++ /dev/null @@ -1,87 +0,0 @@ -.TH "VerticalRoutingTracks" 3 "Thu Mar 19 2020" "Version 1.0" "Oroshi - Analog Devices Layout" \" -*- nroff -*- -.ad l -.nh -.SH NAME -VerticalRoutingTracks \- -.PP -Route two matched capacitors, C1 and C2, drawn in a capacitor matrix\&. - -.SH SYNOPSIS -.br -.PP -.PP -Inherits CapacitorUnit, and CapacitorStack\&. -.SS "Public Member Functions" - -.in +1c -.ti -1c -.RI "def \fB__setStretching__\fP" -.br -.RI "\fISets vertical stretching value considering spacing between elementary capacitors in the matrix\&. \fP" -.ti -1c -.RI "def \fBsetRules\fP" -.br -.RI "\fIDefines technology rules used to draw the layout\&. \fP" -.ti -1c -.RI "def \fBdrawVRoutingTracks\fP" -.br -.RI "\fIIteratively draws vertical routing tracks given the physical layer \fCvRoutingTracksLayer\fP\&. \fP" -.in -1c -.SH "Detailed Description" -.PP -Route two matched capacitors, C1 and C2, drawn in a capacitor matrix\&. - -Connections are put in place with reference to a given matching scheme\&. Elementary capacitor units are connected to horizontal and vertical routing tracks that represent top plates and bottom plates nets of C1 and C2\&. Supported types of capacitors are Poly-Poly and Metal-Metal\&. Technologycal rules are provided by 350 nm AMS CMOS technology with three-four metal layers\&. Metal layers that are used for routeing are placed similarly to horziontal-vertical (HV) symbolic Alliance CAD tool router, where horizontal metal channels are drawn in metal 2 and the vertical ones are in metal 3\&. Given a matrix of dimensions $ R*C $, the total number of vertical tracks is $ 2C+2 $ equivalent to $ C+1 $ couples, ensuring that every elementary capacitor is positioned between four vertical tracks, two from each side\&. In fact, every adjacent couple of these tracks represent top plates and bottom plates of C1 or C2 as shown in Figure 1\&. -.PP -Layout -.PP -An elementary capacitor unit can be a part of C1 or C2 according to the matching scheme\&. However, to respect common-centroid layout specifications, for C1 and C2 to be equal, the matrix number of colums and number of rows must be both even\&. Addionnally, the number of elementary capacitors dedicated to C1 must be equal to those dedicated to C2\&. These two conditions are tested in one of the class methods\&. An exception is raised if at least one of the two is not respected\&. -.SH "Member Function Documentation" -.PP -.SS "def __setStretching__ (self)" - -.PP -Sets vertical stretching value considering spacing between elementary capacitors in the matrix\&. -.PP -\fBReturns:\fP -.RS 4 -stratching value\&. -.RE -.PP - -.PP -References VerticalRoutingTracks\&.abutmentBox_spacing, CapacitorStack\&.abutmentBox_spacing, and RoutMatchedCapacitor\&.abutmentBox_spacing\&. -.PP -Referenced by RoutMatchedCapacitor\&.computeHRLayerYCenter(), and VerticalRoutingTracks\&.drawVRoutingTracks()\&. -.SS "def setRules (self)" - -.PP -Defines technology rules used to draw the layout\&. Some of the rules, namely those describing routeing layers and tracks are applicable for both MIM and PIP capacitors\&. However, cuts rules are different\&. -.PP -\fBRemark:\fP -.RS 4 -All \fCCapacitorStack\fP class rules are also reloaded in this class\&. An exception is raised if the entered capacitor type is unsupported\&. -.RE -.PP -\fBReturns:\fP -.RS 4 -a dictionary with rules labels as keys and rules content as values\&. -.RE -.PP - -.PP -References VerticalRoutingTracks\&.capacitorsNumber, CapacitorStack\&.capacitorsNumber, VerticalRoutingTracks\&.computeVRTDimensions(), VerticalRoutingTracks\&.drawVRoutingTracks(), VerticalRoutingTracks\&.minEnclosure_hRoutingLayer_vRoutingTrack_cut, VerticalRoutingTracks\&.minEnclosure_hRoutingTrackCut, VerticalRoutingTracks\&.minimizeVRTs(), VerticalRoutingTracks\&.minSpacing_hRoutingTrack, RoutMatchedCapacitor\&.minSpacing_hRoutingTrack, VerticalRoutingTracks\&.minWidth_hRoutingLayer, VerticalRoutingTracks\&.minWidth_hRoutingLayer_vRoutingTrack_cut, VerticalRoutingTracks\&.minWidth_hRoutingTrack, VerticalRoutingTracks\&.minWidth_hRoutingTrackCut, VerticalRoutingTracks\&.setRules(), CapacitorStack\&.setRules(), CapacitorUnit\&.setRules(), and RoutMatchedCapacitor\&.setRules()\&. -.PP -Referenced by VerticalRoutingTracks\&.setRules()\&. -.SS "def drawVRoutingTracks (self, vRoutingTracksLayer)" - -.PP -Iteratively draws vertical routing tracks given the physical layer \fCvRoutingTracksLayer\fP\&. Every elementary capacitor is consequently positioned between four routing tracks, two from each side\&. Each couple of adjacent routeing tracks represent top plate and bottom plate nets of Ci, where i is in [1,2]\&. As given in Figure 2, capacitor $ C_{ij} $ with an even j value situated in even columns have and inversely for odd columns numbers\&. -.PP -References VerticalRoutingTracks\&.__computeVRTsNumber__(), VerticalRoutingTracks\&.__findCapIdsToEliminate__(), VerticalRoutingTracks\&.__findCapIdsToEliminatePerColumn__(), VerticalRoutingTracks\&.__findUsedCapIdsPerColumn__(), VerticalRoutingTracks\&.__findVRTsToEliminate__(), VerticalRoutingTracks\&.__setNetsDistribution__(), VerticalRoutingTracks\&.__setPlatesDistribution__(), VerticalRoutingTracks\&.__setStretching__(), VerticalRoutingTracks\&.__setVRTsDistribution__(), VerticalRoutingTracks\&.abutmentBox_spacing, CapacitorStack\&.abutmentBox_spacing, RoutMatchedCapacitor\&.abutmentBox_spacing, VerticalRoutingTracks\&.capacitorIds, VerticalRoutingTracks\&.capacitorsNumber, CapacitorStack\&.capacitorsNumber, VerticalRoutingTracks\&.computeXCenters(), VerticalRoutingTracks\&.dummyElement, CapacitorStack\&.dummyElement, RoutMatchedCapacitor\&.dummyElement, VerticalRoutingTracks\&.dummyRing, CapacitorStack\&.dummyRing, RoutMatchedCapacitor\&.dummyRing, VerticalRoutingTracks\&.getVTrackYMax(), VerticalRoutingTracks\&.getVTrackYMin(), CapacitorUnit\&.hpitch, RoutMatchedCapacitor\&.hRoutingTrack_width, VerticalRoutingTracks\&.hRoutingTrack_width, VerticalRoutingTracks\&.matchingScheme, CapacitorStack\&.matchingScheme, CapacitorStack\&.matrixDim, VerticalRoutingTracks\&.matrixDim, RoutMatchedCapacitor\&.maximumPosition, VerticalRoutingTracks\&.maximumPosition, CapacitorUnit\&.metal2Width, VerticalRoutingTracks\&.minEnclosure_hRoutingTrackCut, VerticalRoutingTracks\&.minimizeVRT, RoutMatchedCapacitor\&.minimumPosition, VerticalRoutingTracks\&.minimumPosition, VerticalRoutingTracks\&.minWidth_hRoutingTrack, VerticalRoutingTracks\&.minWidth_hRoutingTrackCut, VerticalRoutingTracks\&.nets, CapacitorStack\&.nets, VerticalRoutingTracks\&.platesDistribution, VerticalRoutingTracks\&.vRoutingTrack_width, CapacitorStack\&.vRoutingTrack_width, VerticalRoutingTracks\&.vRoutingTrackDict, RoutMatchedCapacitor\&.vRoutingTrackDict, VerticalRoutingTracks\&.vRoutingTrackXCenter, RoutMatchedCapacitor\&.vRoutingTrackXCenter, VerticalRoutingTracks\&.vRTsDistribution, RoutMatchedCapacitor\&.vRTsDistribution, and VerticalRoutingTracks\&.vRTsToEliminate\&. -.PP -Referenced by VerticalRoutingTracks\&.setRules()\&. - -.SH "Author" -.PP -Generated automatically by Doxygen for Oroshi - Analog Devices Layout from the source code\&. diff --git a/oroshi/doc/man/man3/python_Stack_Stack.3 b/oroshi/doc/man/man3/python_Stack_Stack.3 deleted file mode 100644 index d0142196..00000000 --- a/oroshi/doc/man/man3/python_Stack_Stack.3 +++ /dev/null @@ -1,185 +0,0 @@ -.TH "Stack" 3 "Thu Mar 19 2020" "Version 1.0" "Oroshi - Analog Devices Layout" \" -*- nroff -*- -.ad l -.nh -.SH NAME -Stack \- -.PP -Draw a \fBStack\fP of Transistors\&. - -.SH SYNOPSIS -.br -.PP -.PP -Inherits object\&. -.SS "Public Member Functions" - -.in +1c -.ti -1c -.RI "def \fB__init__\fP" -.br -.RI "\fI\fB[API]\fP Constructor \fP" -.ti -1c -.RI "def \fBsetWirings\fP" -.br -.RI "\fI\fB[API]\fP Set the \fBStack\fP wiring specification\&. \fP" -.ti -1c -.RI "def \fBcomputeDimensions\fP" -.br -.RI "\fI\fB[internal]\fP Compute \fBStack\fP dimensions from the technological rules\&. \fP" -.ti -1c -.RI "def \fBdoLayout\fP" -.br -.RI "\fI\fB[API]\fP Draw the complete layout\&. \fP" -.in -1c -.SH "Detailed Description" -.PP -Draw a \fBStack\fP of Transistors\&. - -A \fBStack\fP of Transistors is a set of transistor put into a regular band and connected through their sources/drains\&. All share the exact same W & L\&. The way they are connecteds defines what functionnality the \fBStack\fP implement\&. -.PP -The abutment box of the stack is adjusted so that both height and width are even multiples of the track pitches, so the device can be easily placed and handled by the mixed router\&. The extra space needed for padding is added around the active area\&. Due to the presence of tracks at the top and bottom of the stack, the active area will be horizontally centered but \fBnot\fP vertically\&. -.PP -The drawing of the stack is controlled through a set of variables (attributes) that allows to create it regardless of the technology\&. The technology is taken into account in the way those variables are computed and, obviously, their values\&. The following schematics details the main stack drawing variables along with their computations\&. -.SH "Stack Layout" -.PP -.SS "Gate pitch" -.IP "\(bu" 2 -\fCself\&.gatePitch\fP : the pitch of transistors gates, inside the stack\&. It also applies to dummy transistors\&. -.PP -.PP -Gate Pitch Gate Pitch -.SS "Active Side Width" -.IP "\(bu" 2 -\fCself\&.activeSideWidth\fP : the distance between the axis of the last transistor gate (on the left or right) and the edge of the active area (\fInot\fP the diffusion area)\&. -.PP -.PP -Active Side Width Active Side Width -.SS "H-Track Distance" -.IP "\(bu" 2 -\fCself\&.hTrackDistance\fP : the minimal distance between either the top or bottom edge of the active area and the \fIaxis\fP of the first track\&. -.PP -.PP -H-Track distance H-Track distance -.SS "BoundingBox & Overall Variables" -.IP "\(bu" 2 -\fCself\&.xpitches\fP : the number of vertical track pitches needed to fully enclose the active area\&. -.IP "\(bu" 2 -\fCself\&.ypitches\fP : the number of horizontal track pitches needed to fully enclose the active area\&. -.IP "\(bu" 2 -\fCself\&.activeOffsetX\fP & \fCself\&.activeOffsetY\fP : the offsets of the active area from the bottom left corner of the abutment box\&. -.IP "\(bu" 2 -\fCself\&.diffusionWidth\fP & \fCself\&.diffusionHeight\fP are the minimun dimensions required to fit the active area\&. -.IP "\(bu" 2 -\fCself\&.topTracksNb()\fP : the number of tracks at the top of the stack\&. -.IP "\(bu" 2 -\fCself\&.botTracksNb()\fP : the number of tracks at the bottom of the stack\&. -.PP -.PP -General Stack Layout General Stack Layout -.SH "Wiring Specifications" -.PP -\fBStack\fP routing is done through vertical \fCmetal1\fP wires coming from the gates and diffusions areas and \fCmetal2\fP horizontal wires that can be either above or below the active area\&. \fCmetal2\fP wires (or track) goes through the whole stack and are assigned to one net only\&. A net will have at least one track above or below and may have both\&. -.PP -The connections to the diffusions areas and gates of the various fingers are specified through a list\&. The stack is made of a regular alternation of diffusions and gates\&. The list tells, for each one starting from the left, to which net and track they are connected\&. For a stack of $NFs$ transistor fingers, the must wiring specification must contains $ 3 + (NFs-1) \times 2$ elements\&. The list is given through one \fIstring\fP with each elements separated by one or more whitespace\&. The syntax for \fIone\fP element is detailed \fBAtomic Wiring Specification\fP\&. -.PP -\fBTrack numbering scheme\fP -.PP -Tracks above (top) the active area and below (bottom) each have their own numbering\&. In both case, the count start \fIfrom\fP the active area\&. This, the top tracks will be numbered by increasing Y and the bottom tracks by \fIdecreasing\fP Y\&. -.PP -\fBTrack/Net assignement\fP -.PP -The track/net assignement is deduced from the atomic wiring specifications\&. It also allows to compute the total number of tracks needed above and below the active area\&. -.PP -Wiring Specification Wiring Specification -.SS "Atomic Wiring Specification" -An atomic wiring specification has the same syntax for either diffusions or gates\&. It \fImust\fP not comprise any whitespaces\&. it is made of the following parts: -.IP "\(bu" 2 -The net name to connect to\&. -.IP "\(bu" 2 -Whether the track is above the active area (\fC't'\fP) or below (\fC'b'\fP)\&. The special case (\fC'z'\fP) means that this element must be left unconnected (is such case possible?)\&. -.IP "\(bu" 2 -The number of the track\&. -.PP -.PP -Atomic Wiring Specification Atomic Wiring Specification -.SH "Stack Implementation Details" -.PP -The \fC__setattr__()\fP and \fC__getattr__\fP functions have been redefined so that the technological values (rules) can be accessed has normal attributes of the \fBStack\fP class, in addition to the regular ones\&. -.SH "Constructor & Destructor Documentation" -.PP -.SS "def __init__ (self, device, NERC, NIRC)" - -.PP -\fB[API]\fP Constructor param rules The physical rule set\&. -.PP -\fBParameters:\fP -.RS 4 -\fIdevice\fP The \fBHurricane\fP AMS device into which the layout will be drawn\&. -.br -\fINERC\fP Number of contact rows in external (first & last) diffusion connectors\&. -.br -\fINIRC\fP Number of contact rows in middle diffusion connectors\&. param w The \fBwidth\fP of every transistor of the stack (aka \fIfingers\fP)\&. param L The \fBlength\fP of every transistor\&. param NFs The total number of fingers (dummies includeds)\&. param NDs The number of dummies to put on each side of the stack\&. -.RE -.PP - -.PP -References Stack\&.bImplantLayer, Stack\&.botTracks, Stack\&.botWTracks, Stack\&.bulkNet, Stack\&.bulks, Stack\&.device, Stack\&.dimensioned, Bulk\&.flags, Stack\&.flags, Stack\&.isNmos(), Stack\&.L, Stack\&.metaTnb(), Stack\&.metaTransistors, Stack\&.NDs, Stack\&.NERC, Stack\&.NFs, Stack\&.NIRC, Stack\&.tImplantLayer, Stack\&.topTracks, Stack\&.topWTracks, Stack\&.w, Stack\&.wellLayer, and Stack\&.wirings\&. -.SH "Member Function Documentation" -.PP -.SS "def setWirings (self, wiringSpec)" - -.PP -\fB[API]\fP Set the \fBStack\fP wiring specification\&. -.PP -\fBParameters:\fP -.RS 4 -\fIwiringSpec\fP A string defining the connections for the gates and diffusion areas\&. -.RE -.PP -For a comprehensive explanation of the wiring specification, refers to \fBWiring Specifications\fP \&. -.PP -References Stack\&.botTracks, Stack\&.botTracksNb(), Stack\&.botWTracks, Stack\&.bulkNet, Stack\&.computeDimensions(), Stack\&.device, Stack\&.dimensioned, Stack\&.eDiffMetal1Width, Bulk\&.flags, Stack\&.flags, Stack\&.gatePitch, Stack\&.getBotTrackY(), Stack\&.getHorizontalWidth(), Stack\&.horPitch, Stack\&.L, Stack\&.metal1ToGate, Stack\&.metaTransistors, Stack\&.sideActiveWidth, Stack\&.topTracks, Stack\&.topTracksNb(), Stack\&.topWTracks, Stack\&.wirings, and Stack\&.ypitches\&. -.SS "def computeDimensions (self)" - -.PP -\fB[internal]\fP Compute \fBStack\fP dimensions from the technological rules\&. \fBInternal function\&.\fP Perform the computation of: -.IP "\(bu" 2 -\fCself\&.metal1Pitch\fP -.IP "\(bu" 2 -\fCself\&.minWidth_metal1\fP -.IP "\(bu" 2 -\fCself\&.metal2Pitch\fP -.IP "\(bu" 2 -\fCself\&.minWidth_metal2\fP -.IP "\(bu" 2 -\fCself\&.gatePitch\fP -.IP "\(bu" 2 -\fCself\&.sideActiveWidth\fP -.IP "\(bu" 2 -\fCself\&.hTrackDistance\fP -.IP "\(bu" 2 -\fCself\&.xpitches\fP -.IP "\(bu" 2 -\fCself\&.ypitches\fP -.IP "\(bu" 2 -\fCself\&.activeOffsetX\fP -.IP "\(bu" 2 -\fCself\&.activeOffsetY\fP -.IP "\(bu" 2 -\fCself\&.boundingBox\fP -.PP - -.PP -References Stack\&.activeBox, Stack\&.activeOffsetX, Stack\&.activeOffsetY, Stack\&.bbHeight, Stack\&.bbWidth, Stack\&.botWTracks, Stack\&.boundingBox, Stack\&.bulks, Stack\&.bulkWidth, Stack\&.computeLayoutParasitics(), Stack\&.computeStressEffect(), Stack\&.contactDiffPitch, Stack\&.contactDiffSide, Stack\&.DGG, Stack\&.DGI, Stack\&.dimensioned, Stack\&.DMCG, Stack\&.DMCGT, Stack\&.DMCI, Stack\&.eDiffMetal1Width, Bulk\&.flags, Stack\&.flags, Stack\&.gatePitch, Stack\&.gateVia1Pitch, Stack\&.getBotTrackY(), Stack\&.getHorizontalWidth(), Stack\&.getLastTopTrackY(), Stack\&.horPitch, Stack\&.hTrackDistance, Stack\&.iDiffMetal1Width, Stack\&.isVH, Stack\&.L, Stack\&.metal1ToGate, Stack\&.metal2Pitch, Stack\&.metal2TechnoPitch, Stack\&.metal3Pitch, Stack\&.NERC, Stack\&.NFs, Stack\&.NIRC, Stack\&.sideActiveWidth, Stack\&.tracksNbPitch(), Stack\&.vBulkDistance, Stack\&.verPitch, Stack\&.w, Stack\&.wire1Width, Stack\&.wire2Width, Stack\&.wire3Width, Stack\&.wirings, Stack\&.xpitches, and Stack\&.ypitches\&. -.PP -Referenced by CapacitorUnit\&.create(), Stack\&.doLayout(), RoutMatchedCapacitor\&.route(), and Stack\&.setWirings()\&. -.SS "def doLayout (self, bbMode)" - -.PP -\fB[API]\fP Draw the complete layout\&. Draw the commplete layout of the \fBStack\fP\&. -.PP -References Stack\&.activeOffsetX, Stack\&.activeOffsetY, Stack\&.bbWidth, Stack\&.botTracks, Stack\&.botWTracks, Stack\&.boundingBox, Stack\&.bulkNet, Stack\&.bulks, Stack\&.bulkWidth, Stack\&.computeDimensions(), Stack\&.contactDiffPitch, Stack\&.device, Stack\&.DGG, Stack\&.DGI, Stack\&.DMCG, Stack\&.DMCGT, Stack\&.DMCI, Stack\&.drawActive(), Stack\&.drawGate(), Stack\&.drawSourceDrain(), Stack\&.drawWell(), Stack\&.eDiffMetal1Width, Bulk\&.flags, Stack\&.flags, Stack\&.gatePitch, Stack\&.gateVia1Pitch, Stack\&.getBotTrackY(), Stack\&.getHorizontalAxis(), Stack\&.getHorizontalWidth(), Stack\&.getTopTrackY(), Stack\&.getWiringWidth(), Stack\&.horPitch, Stack\&.iDiffMetal1Width, Stack\&.isBotTrack(), Stack\&.isVH, Stack\&.L, Stack\&.metal1ToGate, Stack\&.NERC, Stack\&.NFs, Stack\&.NIRC, Stack\&.sideActiveWidth, Stack\&.tImplantLayer, Stack\&.topTracks, Stack\&.topWTracks, Stack\&.w, Stack\&.wellLayer, Stack\&.wire1Width, Stack\&.wire2Width, Stack\&.wire3Width, and Stack\&.wirings\&. - -.SH "Author" -.PP -Generated automatically by Doxygen for Oroshi - Analog Devices Layout from the source code\&. diff --git a/oroshi/doc/rtf/classpython_1_1CapacitorMatrix_1_1CapacitorStack__inherit__graph.md5 b/oroshi/doc/rtf/classpython_1_1CapacitorMatrix_1_1CapacitorStack__inherit__graph.md5 deleted file mode 100644 index 9c2da9ab..00000000 --- a/oroshi/doc/rtf/classpython_1_1CapacitorMatrix_1_1CapacitorStack__inherit__graph.md5 +++ /dev/null @@ -1 +0,0 @@ -6d59f047aa372948d1fcd41f41b1f537 \ No newline at end of file diff --git a/oroshi/doc/rtf/classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor__inherit__graph.md5 b/oroshi/doc/rtf/classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor__inherit__graph.md5 deleted file mode 100644 index 2c43a5d2..00000000 --- a/oroshi/doc/rtf/classpython_1_1CapacitorRouted_1_1RoutMatchedCapacitor__inherit__graph.md5 +++ /dev/null @@ -1 +0,0 @@ -d6c9adda9bbd3f3b5faa5c7f1118343e \ No newline at end of file diff --git a/oroshi/doc/rtf/classpython_1_1CapacitorUnit_1_1CapacitorUnit__inherit__graph.md5 b/oroshi/doc/rtf/classpython_1_1CapacitorUnit_1_1CapacitorUnit__inherit__graph.md5 deleted file mode 100644 index a68c56c8..00000000 --- a/oroshi/doc/rtf/classpython_1_1CapacitorUnit_1_1CapacitorUnit__inherit__graph.md5 +++ /dev/null @@ -1 +0,0 @@ -50514444a4014c92a4db51e06796eaa6 \ No newline at end of file diff --git a/oroshi/doc/rtf/classpython_1_1CapacitorVRTracks_1_1VerticalRoutingTracks__inherit__graph.md5 b/oroshi/doc/rtf/classpython_1_1CapacitorVRTracks_1_1VerticalRoutingTracks__inherit__graph.md5 deleted file mode 100644 index f448ab6a..00000000 --- a/oroshi/doc/rtf/classpython_1_1CapacitorVRTracks_1_1VerticalRoutingTracks__inherit__graph.md5 +++ /dev/null @@ -1 +0,0 @@ -3d3cf14caaab2647a548eff0ca30853f \ No newline at end of file