diff --git a/oroshi/doc/html/classpython_1_1CapacitorMatrix_1_1CapacitorStack-members.html b/oroshi/doc/html/classpython_1_1CapacitorMatrix_1_1CapacitorStack-members.html deleted file mode 100644 index c8db4191..00000000 --- a/oroshi/doc/html/classpython_1_1CapacitorMatrix_1_1CapacitorStack-members.html +++ /dev/null @@ -1,84 +0,0 @@ - - -
- -This is the complete list of members for CapacitorStack, including all inherited members.
-Generated by doxygen 1.8.5 on Thu Mar 19 2020 | -Return to top of page | -
Oroshi - Analog Devices Layouts | -Copyright © 2018-2018 UPMC. All rights reserved | -
Draws the layout of a compact capacitor or a matrix of adjacent identical capacitors. - More...
- -Inherits CapacitorUnit.
--Public Member Functions | |
def | __init__ |
This is the class constructor. More... | |
def | __isUnitCap__ |
def | __isMatchingSchemeOK__ |
def | capacitorIdOccurence |
def | create |
Draw the compact or matrix of capacitors. More... | |
def | capacitorLine |
Iteratively draws a horizontal or vertical line of capacitors according to the direction parameter. More... | |
def | capacitorMatrix |
Draws a matrix of identical capacitors. More... | |
def | drawAbutmentBox |
Draws the abutment box of the matrix or campact capacitor. More... | |
def | drawBottomPlatesRLayers |
Draws the routing layers connecting the bottom plate in the matrix of capacitors. More... | |
def | drawTopPlatesRLayers |
Draws the routing layers connecting the top plates in the matrix of capacitors. More... | |
def | getVerticalRoutingTrack_width |
def | getMatrixDim |
def | getMatchingScheme |
Draws the layout of a compact capacitor or a matrix of adjacent identical capacitors.
-The matrix can be composed of one type of capacitors, either Poly-Poly or Metal-Metal in 350 nm AMS CMOS technology. When matching mode is off, every adjacent plates of any consecutive elementary capacitors are connected to each other using vertical routing layers. Otherwise, when matching mode is on, any of elementary capacitors can belong to, or
according to the entered matching scheme. Thus, routing is not done in this class. In both modes, the complete routing process is done using the
RoutCapacitor
class.
def __init__ | -( | -- | self, | -
- | - | - | device, | -
- | - | - | capacitance, | -
- | - | - | capacitorType, | -
- | - | - | abutmentBoxPosition, | -
- | - | - | nets, | -
- | - | - | unitCap = 0 , |
-
- | - | - | matrixDim = [1 , |
-
- | - | - | matchingMode = False , |
-
- | - | - | matchingScheme = [] , |
-
- | - | - | dummyRing = False , |
-
- | - | - | dummyElement = False |
-
- | ) | -- |
This is the class constructor.
-Basically, the class there are three categories of attributes. There are the ones related to the capacitor caracteristics, its type, dimensions. Also, there are attributes to parametrize the class into matching mode or not and there are other attributes realted to the layout varibales. The class has defaut input values, thus, in this constructor, there are two "sub-constructors" according to the entered input parameters. The class attributes are :
-device | The Hurricane AMS device into which the layout is drawn. |
capacitance | The value of the capacitor, expressed in femto Farad (fF). |
capacitorType | Can be MIM or PIP type capacitor. |
abutmentPosition | Refers to the abscissa (XMin) of the bottom left corner of the abutment Box. |
abutmentBoxYMin | Refers to the ordinate (YMin) of the bottom left corner of the abutment Box. |
Except the two last arguments, all the parameters are common with the CapacitorUnit class because the CapacitorStack
constructor calls the mother class constructor to create either a compact capacitor of capacitance
value or rowNumber*
columnNumber
unity capacitors.
rowNumber | Number of rows in the matrix of capacitors. |
columnNumber | Number of columns in the matrix of capacitors. |
References CapacitorStack.__areInputDataOK__(), CapacitorUnit.__computeCapDim__(), CapacitorStack.__initGivenNonZeroUnitCap__(), CapacitorStack.__initGivenNonZeroUnitCapInMatchingMode__(), CapacitorStack.__initGivenZeroUnitCap__(), CapacitorStack.__initGivenZeroUnitCapInMatchingMode__(), CapacitorStack.__initMatrixMode__(), CapacitorUnit.__isCapacitorUnitOK__(), CapacitorStack.abutmentBox, CapacitorUnit.abutmentBox, CapacitorStack.abutmentBox_spacing, CapacitorStack.abutmentBoxPosition, CapacitorStack.capacitance, CapacitorStack.capacitorIdOccurence(), CapacitorStack.capacitorsNumber, CapacitorStack.capacitorType, CapacitorUnit.capacitorType, CapacitorStack.compactCapDim, CapacitorStack.computeUnitCap(), CapacitorStack.device, CapacitorUnit.device, Stack.device, CapacitorStack.doMatrix, CapacitorStack.dummyElement, CapacitorStack.dummyRing, CapacitorStack.dummyRingPosition, CapacitorStack.evaluateUnitCap(), CapacitorStack.matchingMode, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, CapacitorStack.minEnclosure_hRoutingLayer_topPlate_cut, CapacitorStack.minEnclosure_vRoutingTrackCut, CapacitorStack.minSpacing_vRoutingTrack, CapacitorStack.minSpacing_vRoutingTrackCut, CapacitorStack.minWidth_hRoutingLayer_topPlate_cut, CapacitorStack.minWidth_vRoutingTrack, CapacitorStack.minWidth_vRoutingTrackCut, CapacitorStack.nets, CapacitorStack.unitCapacitance, CapacitorStack.unitCapDim, and CapacitorStack.vRoutingTrack_width.
- -def __isUnitCap__ | -( | -- | self | ) | -- |
def __isMatchingSchemeOK__ | -( | -- | self | ) | -- |
True
if the matching scheme specifications are correct. Specifications are :False
. References CapacitorStack.matchingScheme, and CapacitorStack.matrixDim.
- -Referenced by CapacitorStack.capacitorIdOccurence().
- -def capacitorIdOccurence | -( | -- | self, | -
- | - | - | capacitorIdentifier | -
- | ) | -- |
self.matchingScheme
is correct. References CapacitorStack.__areMatrixDimOK__(), CapacitorStack.__isMatchingSchemeOK__(), CapacitorStack.capacitorsNumber, CapacitorStack.dummyElement, CapacitorStack.dummyRing, CapacitorStack.matchingMode, CapacitorStack.matchingScheme, and CapacitorStack.nets.
- -Referenced by CapacitorStack.__init__().
- -def create | -( | -- | self, | -
- | - | - | bbMode = False |
-
- | ) | -- |
Draw the compact or matrix of capacitors.
-First, . Second, . Finally, .
- -References CapacitorStack.__initMatchingMode__(), CapacitorStack.abutmentBox_spacing, CapacitorStack.abutmentBoxPosition, CapacitorStack.capacitance, CapacitorStack.capacitorMatrix(), CapacitorStack.capacitorType, CapacitorUnit.capacitorType, CapacitorStack.computeBondingBoxDimensions(), CapacitorStack.device, CapacitorUnit.device, Stack.device, CapacitorStack.doMatrix, CapacitorStack.drawAbutmentBox(), CapacitorUnit.drawAbutmentBox(), CapacitorStack.drawBottomPlatesRLayers(), CapacitorStack.drawCapacitorStack(), CapacitorStack.drawTopPlatesRLayers(), CapacitorStack.dummyRing, CapacitorStack.matchingMode, CapacitorStack.matrixDim, CapacitorStack.nets, CapacitorStack.setRules(), and CapacitorUnit.setRules().
- -Referenced by CapacitorStack.capacitorLine(), and CapacitorStack.capacitorMatrix().
- -def capacitorLine | -( | -- | self, | -
- | - | - | dy, | -
- | - | - | abutmentBox_spacing, | -
- | - | - | matchingSchemeRowIndex = 0 |
-
- | ) | -- |
Iteratively draws a horizontal or vertical line of capacitors according to the direction
parameter.
An exception is raised if the specified direction is different from {'horizontal'
,'vertical'}. At every iteration, an instance of the CapacitorUnit class is created and its layout is drawn.
dy | the vertical position of the first cut in cut line. |
{'horizontal'
,'vertical'} References CapacitorStack.abutmentBoxPosition, CapacitorStack.capacitorType, CapacitorUnit.capacitorType, CapacitorStack.create(), CapacitorStack.createElementInCapacitorLine(), CapacitorStack.device, CapacitorUnit.device, Stack.device, CapacitorStack.dummyRing, CapacitorStack.matchingMode, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, CapacitorStack.nets, and CapacitorStack.unitCapacitance.
- -Referenced by CapacitorStack.capacitorMatrix().
- -def capacitorMatrix | -( | -- | self, | -
- | - | - | abutmentBox_spacing = 0 |
-
- | ) | -- |
Draws a matrix of identical capacitors.
-The matrix is iterativelly constructed. At every iteration, a new horizontal line of capacitors is drawn.
-References CapacitorStack.abutmentBox_spacing, CapacitorStack.abutmentBoxPosition, CapacitorStack.capacitorLine(), CapacitorStack.capacitorType, CapacitorUnit.capacitorType, CapacitorStack.create(), CapacitorStack.device, CapacitorUnit.device, Stack.device, CapacitorStack.dummyRing, CapacitorStack.getCapDim(), CapacitorStack.matrixDim, CapacitorStack.nets, and CapacitorStack.unitCapacitance.
- -Referenced by CapacitorStack.create().
- -def drawAbutmentBox | -( | -- | self, | -
- | - | - | abutmentBox_spacing = 0 |
-
- | ) | -- |
Draws the abutment box of the matrix or campact capacitor.
- -References CapacitorStack.abutmentBox, CapacitorUnit.abutmentBox, CapacitorStack.abutmentBox_spacing, CapacitorStack.abutmentBoxPosition, CapacitorStack.computeAbutmentBoxDimensions(), and CapacitorUnit.computeAbutmentBoxDimensions().
- -Referenced by CapacitorStack.create().
- -def drawBottomPlatesRLayers | -( | -- | self, | -
- | - | - | bottomPlateRLayer, | -
- | - | - | drawnCapacitor | -
- | ) | -- |
Draws the routing layers connecting the bottom plate in the matrix of capacitors.
-First, the relative positions of the routing layer is of the is extracted from the elementary capacitor instance. Then, its width is computed in a way to connect adjacent plates. Then, the routing layers are iterativelly drawn. The two borders are .
- -References CapacitorStack.matrixDim, and CapacitorStack.nets.
- -Referenced by CapacitorStack.create().
- -def drawTopPlatesRLayers | -( | -- | self, | -
- | - | - | topPlateRLayer, | -
- | - | - | drawnCapacitor | -
- | ) | -- |
Draws the routing layers connecting the top plates in the matrix of capacitors.
-First, the relative positions of the routing layers is of the is extracted from the elementary capacitor instance. Then, its width is computed in a way to connect adjacent plates. Then, the routing layers are iterativelly drawn. The two borders are .
-References CapacitorStack.matrixDim, and CapacitorStack.nets.
- -Referenced by CapacitorStack.create().
- -def getVerticalRoutingTrack_width | -( | -- | self | ) | -- |
def getMatrixDim | -( | -- | self | ) | -- |
References CapacitorStack.compactCapDim, and CapacitorStack.doMatrix.
- -def getMatchingScheme | -( | -- | self | ) | -- |
RoutMatchedCapacitor
class to load self.matchingScheme
attribute. Generated by doxygen 1.8.5 on Thu Mar 19 2020 | -Return to top of page | -
Oroshi - Analog Devices Layouts | -Copyright © 2018-2018 UPMC. All rights reserved | -
This is the complete list of members for RoutMatchedCapacitor, including all inherited members.
-Generated by doxygen 1.8.5 on Thu Mar 19 2020 | -Return to top of page | -
Oroshi - Analog Devices Layouts | -Copyright © 2018-2018 UPMC. All rights reserved | -
Routs two matched capacitors, C1 and C2, drawn in a capacitor matrix. - More...
- -Inherits CapacitorUnit, CapacitorStack, and VerticalRoutingTracks.
--Public Member Functions | |
def | __init__ |
A special method used to customize the class instance to an initial state in which : More... | |
def | route |
Draws the complete layout given the capacitor matrix. More... | |
def | setRules |
Defines technology rules used to draw the layout. More... | |
def | setLayers |
Defines all physical layers used to draw the layout. More... | |
def | computeDimensions |
Computes, through simple instructions and functions calls, layout variables detailed in Figure 2. More... | |
def | computeHRoutingTrackYCenter |
Computes centers' ordinates of the eight horizontal routing tracks. More... | |
def | computeHRLayerYCenter |
Sets the stretching value of top plates. More... | |
def | drawHRoutingTracks |
Iteratively draws horizontal routing tracks on top and bottom positions of the matrix using physical layer routingTracksLayer . More... | |
def | drawHRLayers |
Iteratively draws the horizontal routing layers starting with bottom left elementary capacitor ![]() | |
def | drawCuts |
Draws all required cuts using physical layers : More... | |
def | drawOneCut_vRoutingTrack_HRLayer |
Draws one cut, in layer cutLayer , in order to connect a vertical routing track, at position cutXMin in metal 2, and a horizontal routing track, at position cutYMin in metal 3. More... | |
def | drawCuts_vRoutingTrack_hRoutingTrack |
Draws cuts to connect vertical routing tracks in metal 2 and horizontal routing tracks in metal 3. More... | |
def | __stretchTopPlates__ |
Iteratively performs top plates stretching for the capacitor matrix. More... | |
def | __stretchTopPlateCompactCap__ |
Draws vertical stretched layers for a given elementary capacitor. More... | |
def | __setStretchingDySourceDyTarget__ |
Sets the abcissas of the extremities of the vertical stretching to be applied to capacitor's top plates for a given elementary capacitor in the matrix. More... | |
def | __computeConnections__ |
Computes horizontal routing layers source and target abcissas for top and bottom plates connections to its associated routing track. More... | |
Routs two matched capacitors, C1 and C2, drawn in a capacitor matrix.
-Connections are put in place with reference to a given matching scheme. Elementary capacitor units are connected to horizontal and vertical routing tracks that represent top plates and bottom plates nets of C1 and C2 . Supported types of capacitors are Poly-Poly and Metal-Metal. Technologycal rules are provided by 350 nm AMS CMOS technology with three-four metal layers. Metal layers that are used for routing are placed similarly to horziontal-vertical (HV) symbolic Alliance CAD tool router, where horizontal metal channels are drawn in metal 2 and the vertical ones are in metal 3. Given a matrix of dimensions , the total number of vertical tracks is
equivalent to
couples, ensuring that every elementary capacitor is positioned between four vertical tracks, two from each side. In fact, every adjacent couple of these tracks represent top plates and bottom plates of C1 or C2 as shown in Figure 1.
An elementary capacitor unit can be a part of C1 or C2 according to the matching scheme. However, to respect common-centroid layout specifications, for C1 and C2 to be equal, the matrix number of colums and number of rows must be both even. Addionnally, the number of elementary capacitors dedicated to C1 must be equal to those dedicated to C2. These two conditions are tested in one of the class methods. An exception is raised if at least one of the two is not respected.
-def __init__ | -( | -- | self, | -
- | - | - | vRTInstance | -
- | ) | -- |
A special method used to customize the class instance to an initial state in which :
-CapacitorStack
instance.Position and dimensions attributes, also refered by layout variables, in Figure 2, are defined below :
-device | The Hurricane AMS device onto which the layout is drawn. |
capacitorInstance | Instance of CapacitorStack class. |
capacitor | A nested list containing the matrix elements, which are CapacitorUnit objects. |
matchingScheme | A nested list, with equal dimensions as capacitor attribute, containing assignements of matrix elementary units to C1 and C2, identified by 1 and 2, respectively. Therefore, self.matchingScheme content is a succession of 1 and 2 values, defined as \ capacitor identifiers. For example, given a matrix of dimensions 2x2, the matching scheme can be ![]() ![]() ![]() self.matchingSchem and self.capacitor dimensions are not identical or if self.matchingScheme content is different from supported capacitor identifiers, '1' and '2'. |
capacitorType | Supported types of capacitors are MIM and PIP only. An exception is raised otherwise. |
abutmentBox | The matrix's abutment box. |
matrxiDim | The matrix dimensions, also equal to self.matchingScheme nested list dimensions. |
abutmentBox_spacing | The spacing between elementary units in the matrix. It is computed in CapacitorStack and is reloaded in RoutMatchedCapacitor . self.abutmentBox_spacing includes, vertical routing tracks width and minimum allowed spacing between two adjacent ones. |
hRoutingLayer_width | The width of horizontal routing layers in metal 2, which connect capacitors plates to vertical routing tracks. |
vRoutingTrack_width | The width of vertical routing tracks in metal 3, which connects identical nets together ( ie : bottom plates of C1, top plates of C2, bottom plates of C2 and top plates of C2 ). |
hRoutingTrack_width | The width of horizontal routing tracks in metal 2, which connect identical vertical routing tracks together. |
minSpacing_hRoutingTrack | Minimum spacing between horizontal routing tracks. Wide metal 2 specifications are considered since metal 2 dimensions may exceed 10 ![]() |
minimumPosition | The ordinate of the top plate's routing layer's bottom extremity after stretching. |
maximumPosition | The ordinate of the top plate's routing layer's top extremity, also equivalent to the top plate's top extremity. |
vRoutingTrackXCenter | A nested list of ordered dictionaries, with dimensions equal to self.matrixDim , containing abcissas of vertical routing tracks. All sub-lists' lengths are identical and are equal to 2. The first and second elements describe position of top plate track and bottom plate track, respectively. For example, given a matrix of dimensions 2x2, self.vRoutingTrackXCenter can be [[0, 2], [4,6], [8,10]] ![]() |
hRoutingtrackYCenter | A nested dictonary containing two keys, topTracks and bottomTracks . Each key contains as value a dictionary describing centers' ordinates of four parallel horizontal tracks. The reason why four tracks are needed on top and bottom positions of the matrix is that four nets are used, two for every capacitor Ci , were i is in [1,2]. |
hRoutingLayerYCenter | A nested dicitonary containing two keys, top and bottom . Each key contains as value a dictionary describing centers' ordinates of horizontal routing layers. |
vRoutingTrackDict | A dictionary of routing tracks top and bottom extremities ordinates. |
topPlateStretching | Since not only the same metal 2 layer is used to draw top/bottom plates connections to vertical tracks but also the two plates are superimposed, the top plate's routing tracks is stretched. self.topPlateStretching is therefore the length added to top plate's routing layer in order to avoid short circuits between top and bottom plates routing to vertical tracks since the same metal is used for both. |
References RoutMatchedCapacitor.capacitor, CapacitorStack.dummyRing, RoutMatchedCapacitor.dummyRing, RoutMatchedCapacitor.dummyRingCapacitor, RoutMatchedCapacitor.hRoutingLayer_width, RoutMatchedCapacitor.hRoutingLayerYCenter, RoutMatchedCapacitor.hRoutingTrack_width, RoutMatchedCapacitor.hRoutingtrackYCenter, CapacitorStack.matrixDim, VerticalRoutingTracks.matrixDim, RoutMatchedCapacitor.maximumPosition, RoutMatchedCapacitor.minimumPosition, RoutMatchedCapacitor.minSpacing_hRoutingTrack, RoutMatchedCapacitor.topPlateStretching, and RoutMatchedCapacitor.vRTInstance.
- -def route | -( | -- | self, | -
- | - | - | bbMode = False |
-
- | ) | -- |
Draws the complete layout given the capacitor matrix.
-route
method is succession of calls to user-defined methods inside a newly created Updatesession
. The following tasks are excecuted :
UpdateSession
is created,UpdateSession
is closed.Meanwhile, an exception is raised when the entered capacitor
is not a capacitor matrix or if the capacitor type is unsupported.
References RoutMatchedCapacitor.__stretchTopPlates__(), RoutMatchedCapacitor.capacitor, RoutMatchedCapacitor.computeDimensions(), CapacitorUnit.computeDimensions(), Stack.computeDimensions(), RoutMatchedCapacitor.drawCuts(), RoutMatchedCapacitor.drawDummyRing_hRTracks_Cuts(), RoutMatchedCapacitor.drawHRLayers(), RoutMatchedCapacitor.drawHRoutingTracks(), CapacitorStack.dummyRing, RoutMatchedCapacitor.dummyRing, RoutMatchedCapacitor.dummyRingCapacitor, VerticalRoutingTracks.getVTrackYMax(), VerticalRoutingTracks.getVTrackYMin(), CapacitorUnit.hpitch, RoutMatchedCapacitor.hRoutingtrackYCenter, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, VerticalRoutingTracks.matrixDim, RoutMatchedCapacitor.maximumPosition, CapacitorUnit.metal3Width, RoutMatchedCapacitor.minimumPosition, VerticalRoutingTracks.nets, CapacitorStack.nets, RoutMatchedCapacitor.routeDummyRing(), RoutMatchedCapacitor.routeLeftAndRightSides(), RoutMatchedCapacitor.routeTopOrBottomSide(), RoutMatchedCapacitor.setLayers(), CapacitorStack.setRules(), CapacitorUnit.setRules(), RoutMatchedCapacitor.setRules(), CapacitorUnit.vpitch, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, and RoutMatchedCapacitor.vRoutingTrackXCenter.
- -def setRules | -( | -- | self | ) | -- |
Defines technology rules used to draw the layout.
-Some of the rules, namely those describing routing layers and tracks are applicable for both MIM and PIP capacitors. However, cuts rules are different.
-CapacitorStack
class rules are also reloaded in this class. An exception is raised if the entered capacitor type is unsupported.References CapacitorStack.capacitorType, CapacitorUnit.capacitorType, RoutMatchedCapacitor.capacitorType, CapacitorStack.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minSpacing_hRoutingLayer, RoutMatchedCapacitor.minSpacing_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minSpacing_hRoutingLayer_vRoutingTrack_cut, RoutMatchedCapacitor.minSpacing_hRoutingTrackCut, CapacitorStack.minSpacing_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_vRoutingTrackCut, CapacitorStack.minWidth_hRoutingLayer_topPlate_cut, and RoutMatchedCapacitor.minWidth_hRoutingLayer_topPlate_cut.
- -Referenced by RoutMatchedCapacitor.route(), and VerticalRoutingTracks.setRules().
- -def setLayers | -( | -- | self | ) | -- |
Defines all physical layers used to draw the layout.
-Layers are loaded using DataBase
API. The same routing layers are used for both capacitor types except cuts layers that connect top plates to vertical routing tracks. Basicaly, metal 2, meta 3, cut 1 and cut 2 are the ones defined.
References CapacitorStack.capacitorType, CapacitorUnit.capacitorType, RoutMatchedCapacitor.capacitorType, CapacitorStack.dummyRing, and RoutMatchedCapacitor.dummyRing.
- -Referenced by RoutMatchedCapacitor.route().
- -def computeDimensions | -( | -- | self, | -
- | - | - | bbMode | -
- | ) | -- |
Computes, through simple instructions and functions calls, layout variables detailed in Figure 2.
- -References CapacitorStack.abutmentBox_spacing, RoutMatchedCapacitor.abutmentBox_spacing, VerticalRoutingTracks.capacitorsNumber, CapacitorStack.capacitorsNumber, RoutMatchedCapacitor.computeBondingBoxDimInbbMode(), RoutMatchedCapacitor.computeHRLayerYCenter(), RoutMatchedCapacitor.computeHRoutingTrackYCenter(), RoutMatchedCapacitor.hRoutingLayer_width, CapacitorStack.matrixDim, VerticalRoutingTracks.matrixDim, RoutMatchedCapacitor.maximumPosition, CapacitorStack.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minEnclosure_hRoutingLayer_topPlate_cut, VerticalRoutingTracks.minEnclosure_hRoutingLayer_vRoutingTrack_cut, RoutMatchedCapacitor.minimumPosition, VerticalRoutingTracks.minWidth_hRoutingLayer, CapacitorStack.minWidth_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minWidth_hRoutingLayer_topPlate_cut, VerticalRoutingTracks.minWidth_hRoutingLayer_vRoutingTrack_cut, RoutMatchedCapacitor.vRoutingTrack_spacing, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, RoutMatchedCapacitor.vRoutingTrackDict, and RoutMatchedCapacitor.vRoutingTrackXCenter.
- -Referenced by RoutMatchedCapacitor.route().
- -def computeHRoutingTrackYCenter | -( | -- | self | ) | -- |
Computes centers' ordinates of the eight horizontal routing tracks.
-The tracks include four on top and four on bottom of the matrix. To do the computations, fist, center of the first bottom or top track, given in Figure 2, is computed. Then, all adjacent three centers are deduced by simples translation of the first one. Translation quantity is equal to the sum of distance between adjacent routing tracks, self.hRoutingTracks_spacing, and half width of the routing track itself, self.hRoutingTrack_width
.
References RoutMatchedCapacitor.__setPlatesIds__(), CapacitorUnit.hpitch, RoutMatchedCapacitor.hRoutingtrackYCenter, RoutMatchedCapacitor.maximumPosition, and RoutMatchedCapacitor.minimumPosition.
- -Referenced by RoutMatchedCapacitor.computeDimensions().
- -def computeHRLayerYCenter | -( | -- | self | ) | -- |
Sets the stretching value of top plates.
-Then iteratively computes the centers of horizontal routing layer regarding top and bottom plates.
- -References RoutMatchedCapacitor.__findPossibleShortCircuits__(), VerticalRoutingTracks.__setStretching__(), RoutMatchedCapacitor.__setStretchingDySourceDyTarget__(), RoutMatchedCapacitor.bondingBox, RoutMatchedCapacitor.capacitor, RoutMatchedCapacitor.hRoutingLayer_width, RoutMatchedCapacitor.hRoutingLayerYCenter, RoutMatchedCapacitor.hRoutingTrack_width, RoutMatchedCapacitor.hRoutingtrackYCenter, CapacitorStack.matrixDim, VerticalRoutingTracks.matrixDim, RoutMatchedCapacitor.minSpacing_hRoutingLayer, RoutMatchedCapacitor.topPlateStretching, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, and RoutMatchedCapacitor.vRoutingTrackXCenter.
- -Referenced by RoutMatchedCapacitor.computeDimensions().
- -def drawHRoutingTracks | -( | -- | self, | -
- | - | - | routingTracksLayer | -
- | ) | -- |
Iteratively draws horizontal routing tracks on top and bottom positions of the matrix using physical layer routingTracksLayer
.
References RoutMatchedCapacitor.hRoutingTrack_width, RoutMatchedCapacitor.hRoutingtrackYCenter, VerticalRoutingTracks.nets, CapacitorStack.nets, and RoutMatchedCapacitor.vRoutingTrackXCenter.
- -Referenced by RoutMatchedCapacitor.route().
- -def drawHRLayers | -( | -- | self, | -
- | - | - | xPlateRLayer | -
- | ) | -- |
Iteratively draws the horizontal routing layers starting with bottom left elementary capacitor .
References RoutMatchedCapacitor.__computeConnections__(), RoutMatchedCapacitor.hRoutingLayer_width, RoutMatchedCapacitor.hRoutingLayerYCenter, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, VerticalRoutingTracks.matrixDim, CapacitorStack.matrixDim, VerticalRoutingTracks.nets, and CapacitorStack.nets.
- -Referenced by RoutMatchedCapacitor.route().
- -def drawCuts | -( | -- | self, | -
- | - | - | layer_hRTrack_hRLayer, | -
- | - | - | layer_tracksCut, | -
- | - | - | layer_topPlateCut | -
- | ) | -- |
Draws all required cuts using physical layers :
-layer_hRTrack_hRLayer
to connect bottom plates to vertical routing tracks,layer_tracksCut
to connect vertical routing tracks to horizontal ones,layer_topPlateCut
to connect top plates to vertical routing tracks. ALso in drawCuts
, nUmber of maximum cuts number on every layer is computed and cuts enclosure is adjusted according to layer's width. References RoutMatchedCapacitor.__setPlatesLabels__(), VerticalRoutingTracks.capacitorIds, VerticalRoutingTracks.capacitorsNumber, CapacitorStack.capacitorsNumber, RoutMatchedCapacitor.drawCuts_stretchedTopPlate(), RoutMatchedCapacitor.drawCuts_vRoutingTrack_HRLayer(), RoutMatchedCapacitor.drawCuts_vRoutingTrack_hRoutingTrack(), RoutMatchedCapacitor.drawOneCut_vRoutingTrack_HRLayer(), RoutMatchedCapacitor.hRoutingLayerYCenter, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, VerticalRoutingTracks.matrixDim, CapacitorStack.matrixDim, CapacitorStack.minEnclosure_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_hRoutingTrackCut, CapacitorStack.minSpacing_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_vRoutingTrackCut, VerticalRoutingTracks.minWidth_hRoutingTrackCut, CapacitorStack.minWidth_vRoutingTrackCut, VerticalRoutingTracks.nets, CapacitorStack.nets, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, and RoutMatchedCapacitor.vRoutingTrackXCenter.
- -Referenced by RoutMatchedCapacitor.route().
- -def drawOneCut_vRoutingTrack_HRLayer | -( | -- | self, | -
- | - | - | net, | -
- | - | - | cutLayer, | -
- | - | - | cutXMin, | -
- | - | - | cutYMin, | -
- | - | - | cutNumber | -
- | ) | -- |
Draws one cut, in layer cutLayer
, in order to connect a vertical routing track, at position cutXMin
in metal 2, and a horizontal routing track, at position cutYMin
in metal 3.
References RoutMatchedCapacitor.minSpacing_hRoutingLayer_vRoutingTrack_cut, and VerticalRoutingTracks.minWidth_hRoutingLayer_vRoutingTrack_cut.
- -Referenced by RoutMatchedCapacitor.drawCuts().
- -def drawCuts_vRoutingTrack_hRoutingTrack | -( | -- | self, | -
- | - | - | cutLayer, | -
- | - | - | cutNumber, | -
- | - | - | enclosure_cut | -
- | ) | -- |
Draws cuts to connect vertical routing tracks in metal 2 and horizontal routing tracks in metal 3.
- -References RoutMatchedCapacitor.__setPlatesIds__(), RoutMatchedCapacitor.capacitor, RoutMatchedCapacitor.dummyRingCapacitor, RoutMatchedCapacitor.hRoutingLayerYCenter, RoutMatchedCapacitor.hRoutingtrackYCenter, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, VerticalRoutingTracks.matrixDim, CapacitorStack.matrixDim, CapacitorStack.minEnclosure_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minEnclosure_hRoutingLayer_topPlate_cut, CapacitorStack.minEnclosure_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minSpacing_hRoutingTrackCut, CapacitorStack.minSpacing_vRoutingTrackCut, RoutMatchedCapacitor.minSpacing_vRoutingTrackCut, CapacitorStack.minWidth_hRoutingLayer_topPlate_cut, RoutMatchedCapacitor.minWidth_hRoutingLayer_topPlate_cut, VerticalRoutingTracks.minWidth_hRoutingTrackCut, CapacitorStack.minWidth_vRoutingTrackCut, VerticalRoutingTracks.nets, CapacitorStack.nets, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, and RoutMatchedCapacitor.vRoutingTrackXCenter.
- -Referenced by RoutMatchedCapacitor.drawCuts().
- -def __stretchTopPlates__ | -( | -- | self, | -
- | - | - | capacitor, | -
- | - | - | rlayer | -
- | ) | -- |
Iteratively performs top plates stretching for the capacitor matrix.
-Vertical segments are connected to top plate routing layer.
-capacitor | Capacitor matrix. |
rlayer | Layer of the drawn vertical rectangle. |
References RoutMatchedCapacitor.__stretchTopPlateCompactCap__(), VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, VerticalRoutingTracks.matrixDim, CapacitorStack.matrixDim, VerticalRoutingTracks.nets, and CapacitorStack.nets.
- -Referenced by RoutMatchedCapacitor.route().
- -def __stretchTopPlateCompactCap__ | -( | -- | self, | -
- | - | - | net, | -
- | - | - | capacitor, | -
- | - | - | routingLayer, | -
- | - | - | j = 0 |
-
- | ) | -- |
Draws vertical stretched layers for a given elementary capacitor.
- -References RoutMatchedCapacitor.__setStretchingDySourceDyTarget__(), and RoutMatchedCapacitor.topPlateStretching.
- -Referenced by RoutMatchedCapacitor.__stretchTopPlates__().
- -def __setStretchingDySourceDyTarget__ | -( | -- | self, | -
- | - | - | capacitor, | -
- | - | - | deltay | -
- | ) | -- |
Sets the abcissas of the extremities of the vertical stretching to be applied to capacitor's top plates for a given elementary capacitor in the matrix.
-capacitor | .values() Elementary unit capacitor. |
deltay | Stretching value. |
dySource
and as top extremity and bottom extermity, respectively. Referenced by RoutMatchedCapacitor.__stretchTopPlateCompactCap__(), and RoutMatchedCapacitor.computeHRLayerYCenter().
- -def __computeConnections__ | -( | -- | self, | -
- | - | - | i, | -
- | - | - | j, | -
- | - | - | capacitorIdentifier | -
- | ) | -- |
Computes horizontal routing layers source and target abcissas for top and bottom plates connections to its associated routing track.
-(i,j) | row and column indexes, respectively, in the matrix which describe the elementary capacitor position in the matrix. |
capacitorIdentifier | equal to '1' if C1 and '2' if C2. |
topPlate
and bottomPlate and values equal to sub-dictionaries. The sub-dictionaries, are in their turn composed of two keys standing for the abcissa of the source and the abcissa of the target. References RoutMatchedCapacitor.__findHRLDyTrarget__(), RoutMatchedCapacitor.__isCapacitorAdummy__(), RoutMatchedCapacitor.__setPlatesLabels__(), RoutMatchedCapacitor.capacitor, VerticalRoutingTracks.capacitorIds, VerticalRoutingTracks.capacitorsNumber, CapacitorStack.capacitorsNumber, CapacitorStack.dummyElement, RoutMatchedCapacitor.dummyElement, CapacitorStack.dummyRing, RoutMatchedCapacitor.dummyRing, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, VerticalRoutingTracks.matrixDim, CapacitorStack.matrixDim, VerticalRoutingTracks.nets, CapacitorStack.nets, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, RoutMatchedCapacitor.vRoutingTrackXCenter, and RoutMatchedCapacitor.vRTsDistribution.
- -Referenced by RoutMatchedCapacitor.drawHRLayers().
- -Generated by doxygen 1.8.5 on Thu Mar 19 2020 | -Return to top of page | -
Oroshi - Analog Devices Layouts | -Copyright © 2018-2018 UPMC. All rights reserved | -
This is the complete list of members for CapacitorUnit, including all inherited members.
-Generated by doxygen 1.8.5 on Thu Mar 19 2020 | -Return to top of page | -
Oroshi - Analog Devices Layouts | -Copyright © 2018-2018 UPMC. All rights reserved | -
Draws a capacitor of type Poly-Poly or Metal-Metal in 350 nm AMS CMOS technology. - More...
--Public Member Functions | |
def | __init__ |
This is the class constructor. More... | |
def | __setCapacitorPerUnit__ |
Sets the area and perimeter capacitances as specified in 350 nm AMS technology and according to capacitorType (MIM or PIP). More... | |
def | __computeCapDim__ |
Computes width and length of the capacitor. More... | |
def | __isCapacitorUnitOK__ |
Checks if the computed capacitor dimensions exceed or are less than maximum and minimum limits, respectively, as specified in technology rules. More... | |
def | setRules |
Selects technological rules according to the capacitor type. More... | |
def | getCapacitorType |
def | getMaximumCapWidth |
maximum size of capacitor's top plate. More... | |
def | getMinimumCapWidth |
def | getLayers |
Loads the technology file then extracts the adequate layers according to the capacitor type (MIM or PIP). More... | |
def | create |
When bonding box mode is activated, the function draws all layout physical layers of the capacitor after checking its dimensions. More... | |
def | drawCapacitor |
Draws all layout physicial layers of the capacitor. More... | |
def | computeBottomPlateCuts |
Computes needed parameters to draw bottom plate cuts in its exact position, including : More... | |
def | computeTopPlateCuts |
Computes needed parameters to draw top plate cuts in its exact position, including : More... | |
def | drawAbutmentBox |
Draws the abutment box of the capacitor in position < (abutmentBoxXMin, abutmentBoxYMin)>. More... | |
def | drawOnePlate |
Draws the top or bottom plate through inflation of the Box under it. More... | |
def | drawBottomPlateCut |
Draws the required cuts to connect the bottom plate. More... | |
def | drawTopPlateCut |
Draws the top plate's cuts after computing the maximal number of cuts that can be placed and its exact enclosure in the top plate. More... | |
def | drawRoutingLayers |
Draws the routing layers of both bottom and top plates after computing widths and the exact position of these layers. More... | |
def | cutMaxNumber |
Computes the maximal number of cuts to be placed on a layer of width width_layer considering specifications such as the spacing between the cuts, its width and its enclosure in the layer. More... | |
def | cutLine |
Creates a horizontal or vertical line of contacts according to the specified direction. More... | |
def | cutMatrix |
Creates a matrix of cuts by vertically stacking horizontal lines of identical cuts. More... | |
def | getBottomPlateYMax |
def | getBottomPlateLeftCutXMin |
def | getBottomPlateLeftCutYMin |
def | getBottomPlateLeftCutYMax |
def | getBottomPlateRightCutXMin |
def | getBottomPlateRightCutYMin |
def | getBottomPlateRightCutYMax |
def | getBotPlateLeftRLayerXMax |
def | getBottomPlateRightCutYCenter |
def | getBotPlateLeftRLayerXMin |
def | getBotPlateRLayerYMin |
def | getBotPlateRLayerYMax |
def | getBotPlateRLayerWidth |
def | getBotPlateRightRLayerXCenter |
def | getBotPlateLeftRLayerXCenter |
def | getTopPlateRLayerYMin |
def | getTopPlateRLayerYMax |
def | getTopPlateRLayerWidth |
def | getTopPlateRLayerXCenter |
def | getTopPlateRLayerXMin |
def | getTopPlateRLayerXMax |
Draws a capacitor of type Poly-Poly or Metal-Metal in 350 nm AMS CMOS technology.
-PIP and MIM capacitors are the result of surface superposition between poly1 and poly2 or metal2 and metalcap layers, respectively. Given the capacitor value, layout dimensions are computed, then, capacitor layers are drawn. Capacitor value, , is given in the expression below, where
and
are, area capacitance, perimeter capacitance, area and permiter of the capacitor, respectively :
-
-
The drawn layout shape is square. Thus, metcap or poly2 length and width are equal and are computed using the capacitor expression. Furthermore, given ,
and enclosure technological rules, dimensions and positions of the abutment box as well as the bottom plate are computed. Layouts with dimensions that exceed technological limits cannot be drawn.
def __init__ | -( | -- | self, | -
- | - | - | device, | -
- | - | - | capacitorType, | -
- | - | - | abutmentBoxPosition, | -
- | - | - | capacitance = 0 , |
-
- | - | - | capDim = {} |
-
- | ) | -- |
This is the class constructor.
-Few of the class attributes final values are computed in this level. Most of attributes are only initialized to zero or empty values. Then, it is computed in dedicated class method. Input parameters are :
-device | Hurricane AMS device into which layout is drawn. |
capacitance | Capacitor value, expressed in ![]() |
abutmentBoxPosition | A list containing abscissa and ordinate of the bottom left corner of the abutment box. |
Class attributes are described in the list below. Most of class attributes refer to layout dimensions. Dictionaries are used to group attributes related to the same layout varibale. Layout dimensions and variables are described in Figure 1.
-device | Hurricane AMS device into which layout is drawn. |
capacitance | Capacitor value, expressed in ![]() |
capacitorType | Can be 'MIMCap' or 'PIPCap' as capacitor type. |
abutmentBoxDict | A dictionary containing abscissa and ordinate of the bottom left corner of the abutment box, (XMin) and (YMin), respectively. |
abutmentBox | Abutment box drawn square. It is an object of type Box . |
bottomPlateBox | Bottom plate drawn square. It is an object of type Box . |
topPlateBox | Top plate drawn square. It is an object of type Box . |
cut2MatrixDict | A dictionary containing center position of the left bottom, which is cut the first to be drawn in the matrix of cuts. Initially, the dictionary is empty. It is only updated when self.capacitorType is equal to 'MIMCap' . |
cutLeftLineDict | A dictionary containing abcissa and ordinate of the bottom cut in the left line of cuts to be drawn on bottom plate's layer. |
cutRightLineDict | A dictionary containing abcissa and ordinate of the bottom cut in the right line of cuts to be drawn on bottom plate's layer. |
topCutLineDict | A dictionary containing abcissa and ordinate of the bottom cut in the right line of cuts to be drawn on top plate's layer. Initially, the dictionary is empty. It is only updated when self.capacitorType is equal to 'PIPCap' . |
topPlateRLayerDict | A dictionary containing position information of the top plate's routing layer. The dictionary includes ordinates of the layer's top and bottom extremities, 'XMin' and 'YMin' , respectively, the abcissa of it's center, 'XCenter' and its width, 'width' . |
bottomPlateRLayerDict | A dictionary containing |
enclosure_botPlate_topPlate | Top plate's layer encolusre in bottom plate's layer. |
minheight_topPlatecut | Minimum height of cuts for top plate connection to other metal layer. |
topCutLineNumber | Maximum possible number cuts to be drawn for top plate's connection. |
bottomCutLineNumber | Maximum possible number cuts to be drawn for top plate's connection. |
NonUnitCapacitor
class must be precisely defined. References CapacitorUnit.__computeCapacitance__(), CapacitorUnit.__computeCapDim__(), CapacitorUnit.__initCapDim__(), CapacitorUnit.abutmentBox, CapacitorUnit.abutmentBoxDict, CapacitorUnit.bottomCutLineNumber, CapacitorUnit.bottomPlateBox, CapacitorUnit.bottomPlateBoxDict, CapacitorUnit.bottomPlateRLayerDict, CapacitorUnit.capacitorType, CapacitorUnit.capDim, CapacitorUnit.cut2MatrixDict, CapacitorUnit.cutLeftLineDict, CapacitorUnit.cutRightLineDict, CapacitorUnit.device, Stack.device, CapacitorUnit.enclosure_botPlate_abtBox, CapacitorUnit.enclosure_botPlate_topPlate, CapacitorUnit.minheight_topPlatecut, CapacitorUnit.topCutLineDict, CapacitorUnit.topCutLineNumber, CapacitorUnit.topPlateBox, CapacitorUnit.topPlateBoxDict, and CapacitorUnit.topPlateRLayerDict.
- -def __setCapacitorPerUnit__ | -( | -- | self, | -
- | - | - | capacitorType | -
- | ) | -- |
Sets the area and perimeter capacitances as specified in 350 nm AMS technology and according to capacitorType
(MIM or PIP).
Referenced by CapacitorUnit.__computeCapDim__().
- -def __computeCapDim__ | -( | -- | self, | -
- | - | - | capacitance, | -
- | - | - | capacitorType | -
- | ) | -- |
Computes width and length of the capacitor.
-Given capacitance
value as well as the permiter and area capacitances, a quadratic equation is solved where the unknown parameter is the width (also equivalent to the length).
References CapacitorUnit.__setCapacitorPerUnit__().
- -Referenced by CapacitorStack.__init__(), and CapacitorUnit.__init__().
- -def __isCapacitorUnitOK__ | -( | -- | self, | -
- | - | - | capDim | -
- | ) | -- |
Checks if the computed capacitor dimensions exceed or are less than maximum and minimum limits, respectively, as specified in technology rules.
-True
if all rules are respected. References CapacitorUnit.capacitorType, CapacitorUnit.getMaximumCapWidth(), and CapacitorUnit.getMinimumCapWidth().
- -Referenced by CapacitorStack.__init__(), and CapacitorUnit.create().
- -def setRules | -( | -- | self | ) | -- |
Selects technological rules according to the capacitor type.
-References CapacitorUnit.capacitorType, CapacitorUnit.hpitch, CapacitorUnit.isVH, Stack.isVH, CapacitorUnit.METAL2Pitch, CapacitorUnit.metal2Width, CapacitorUnit.METAL3Pitch, CapacitorUnit.metal3Width, CapacitorUnit.minEnclo_botPlate_botPlateCut, CapacitorUnit.minEnclo_botPlateRMetal_botPlateCut, CapacitorUnit.minEnclo_routingTrackMetal_cut, CapacitorUnit.minEnclo_topPlate_topPlateCut, CapacitorUnit.minEnclo_topPlateRMetal_topPlateCut, CapacitorUnit.minheight_topPlatecut, CapacitorUnit.minSpacing_botPlate, CapacitorUnit.minSpacing_botPlateCut_topPlate, CapacitorUnit.minSpacingOnBotPlate_cut, CapacitorUnit.minSpacingOnTopPlate_cut, CapacitorUnit.minWidth_botPlatecut, CapacitorUnit.minWidth_botRMetal, CapacitorUnit.minWidth_routingTrackcut, CapacitorUnit.minWidth_topPlate, CapacitorUnit.minWidth_topPlatecut, CapacitorUnit.minWidth_topRMetal, and CapacitorUnit.vpitch.
- -Referenced by CapacitorStack.create(), CapacitorUnit.create(), RoutMatchedCapacitor.route(), and VerticalRoutingTracks.setRules().
- -def getCapacitorType | -( | -- | self | ) | -- |
'MIMCap'
or 'PIPCap'
. getCapacitorType()
is especially useful when an instance of CapacitorUnit
class is called in another classes instances to identify the capacitor's type. def getMaximumCapWidth | -( | -- | self | ) | -- |
maximum size of capacitor's top plate.
-getMaximumCapWidth()
is called to check if capacitor dimensions are within acceptable technological limits. An exception is raised if the entered capacitor type is unknown.
getMaximumCapWidth()
References CapacitorUnit.capacitorType.
- -Referenced by CapacitorUnit.__isCapacitorUnitOK__().
- -def getMinimumCapWidth | -( | -- | self | ) | -- |
References CapacitorUnit.capacitorType.
- -Referenced by CapacitorUnit.__isCapacitorUnitOK__().
- -def getLayers | -( | -- | self | ) | -- |
Loads the technology file then extracts the adequate layers according to the capacitor type (MIM or PIP).
-References CapacitorUnit.capacitorType.
- -Referenced by CapacitorUnit.create().
- -def create | -( | -- | self, | -
- | - | - | t, | -
- | - | - | b, | -
- | - | - | bbMode = False , |
-
- | - | - | vEnclosure_botPlate_abtBox = None , |
-
- | - | - | hEnclosure_botPlate_abtBox = None |
-
- | ) | -- |
When bonding box mode is activated, the function draws all layout physical layers of the capacitor after checking its dimensions.
-All functions are excecuted in a new Update Session. In the contrary, only an exact estimation of layout dimensions is given. An error is raised when dimensions reach technological limits for MIM and PIP capacitors or when bbMode
parameters is other than True
or False
.
( | t , b ) nets of top and bottom plates, respectively |
bbMode | activates bonding box dimensions computing when set to True |
References CapacitorUnit.__isCapacitorUnitOK__(), CapacitorUnit.abutmentBoxDict, CapacitorUnit.capDim, CapacitorUnit.computeDimensions(), Stack.computeDimensions(), CapacitorUnit.drawAbutmentBox(), CapacitorUnit.drawCapacitor(), Technology.getLayers(), CapacitorUnit.getLayers(), and CapacitorUnit.setRules().
- -def drawCapacitor | -( | -- | self, | -
- | - | - | layerDict, | -
- | - | - | t, | -
- | - | - | b | -
- | ) | -- |
Draws all layout physicial layers of the capacitor.
-layerDict | a dictionary containing a description of the required physical layers according to capacitor type |
( | t , b ) nets of top and bottom plates, respectively |
References CapacitorUnit.bottomPlateBox, CapacitorUnit.bottomPlateBoxDict, CapacitorUnit.drawBottomPlateCut(), CapacitorUnit.drawOnePlate(), CapacitorUnit.drawRoutingLayers(), CapacitorUnit.drawTopPlateCut(), CapacitorUnit.topPlateBox, and CapacitorUnit.topPlateBoxDict.
- -Referenced by CapacitorUnit.create().
- -def computeBottomPlateCuts | -( | -- | self | ) | -- |
Computes needed parameters to draw bottom plate cuts in its exact position, including :
-Given parameters described above, it is possible to draw the entire lines of cuts on both sides of bottom plate using cutLine
function.
References CapacitorUnit.bottomCutLineNumber, CapacitorUnit.bottomPlateBoxDict, CapacitorUnit.cutLeftLineDict, CapacitorUnit.cutMaxNumber(), CapacitorUnit.cutRightLineDict, CapacitorUnit.minEnclo_botPlate_botPlateCut, CapacitorUnit.minheight_topPlatecut, CapacitorUnit.minSpacing_botPlateCut_topPlate, CapacitorUnit.minSpacingOnBotPlate_cut, CapacitorUnit.minWidth_topPlatecut, and CapacitorUnit.topPlateBoxDict.
- -Referenced by CapacitorUnit.drawAbutmentBox().
- -def computeTopPlateCuts | -( | -- | self | ) | -- |
Computes needed parameters to draw top plate cuts in its exact position, including :
-Given parameters described above, it is possible to draw the entire lines of cuts on both sides of bottom plate using cutLine
function.
References CapacitorUnit.abutmentBoxDict, CapacitorUnit.bottomPlateBoxDict, CapacitorUnit.bottomPlateRLayerDict, CapacitorUnit.capacitorType, CapacitorUnit.cut2MatrixDict, CapacitorUnit.cutLeftLineDict, CapacitorUnit.cutMaxNumber(), CapacitorUnit.cutRightLineDict, CapacitorUnit.enclosure_botPlate_topPlate, CapacitorUnit.hEnclosure_botPlate_abtBox, CapacitorUnit.minEnclo_botPlate_botPlateCut, CapacitorUnit.minEnclo_botPlateRMetal_botPlateCut, CapacitorUnit.minEnclo_routingTrackMetal_cut, CapacitorUnit.minEnclo_topPlate_topPlateCut, CapacitorUnit.minEnclo_topPlateRMetal_topPlateCut, CapacitorUnit.minheight_topPlatecut, CapacitorUnit.minSpacing_botPlate, CapacitorUnit.minSpacing_botPlateCut_topPlate, CapacitorUnit.minSpacingOnTopPlate_cut, CapacitorUnit.minWidth_botPlatecut, CapacitorUnit.minWidth_botRMetal, CapacitorUnit.minWidth_routingTrackcut, CapacitorUnit.minWidth_topPlatecut, CapacitorUnit.setBottomPlateAbtBoxEnclosure(), CapacitorUnit.topCutLineDict, CapacitorUnit.topCutLineNumber, CapacitorUnit.topPlateBoxDict, CapacitorUnit.topPlateRLayerDict, and CapacitorUnit.vEnclosure_botPlate_abtBox.
- -Referenced by CapacitorUnit.drawAbutmentBox().
- -def drawAbutmentBox | -( | -- | self | ) | -- |
Draws the abutment box of the capacitor in position <
(abutmentBoxXMin, abutmentBoxYMin)>.
First, the minimum enclosure of the top plate inside the bottom plate is computed. Second, using this parameters as well as the capacitor dimensions, the width and height of the abutment box are computed. The box is finally drawn.
- -References CapacitorUnit.abutmentBox, CapacitorUnit.abutmentBoxDict, CapacitorUnit.bottomPlateBoxDict, CapacitorUnit.computeAbutmentBoxDimensions(), CapacitorUnit.computeBottomPlateCuts(), CapacitorUnit.computeOnePlateBoxDimensions(), CapacitorUnit.computeRoutingLayersDimensions(), CapacitorUnit.computeTopPlateCuts(), CapacitorUnit.enclosure_botPlate_topPlate, CapacitorUnit.hEnclosure_botPlate_abtBox, CapacitorUnit.topPlateBoxDict, and CapacitorUnit.vEnclosure_botPlate_abtBox.
- -Referenced by CapacitorStack.create(), and CapacitorUnit.create().
- -def drawOnePlate | -( | -- | self, | -
- | - | - | layer, | -
- | - | - | net, | -
- | - | - | boxDimensions | -
- | ) | -- |
Draws the top or bottom plate through inflation of the Box under it.
-These boxes are the abutment box in the case of the bottom plate and the bottom plate's box in the case of the top plate. This function also creates a a net for the drawn plate and sets it as external.
-Referenced by CapacitorUnit.drawCapacitor().
- -def drawBottomPlateCut | -( | -- | self, | -
- | - | - | layer, | -
- | - | - | b | -
- | ) | -- |
Draws the required cuts to connect the bottom plate.
-First, the maximal possible number of cuts that can be drawn is computed. Second, using the computed number, the enclosure of this cuts in the bottom plate's layer is adjusted while the minimal enclosure is respected. Third, the relative positions of the cuts on both sides of the plate are computed. Finally, two vertical lines of cuts are drawns.
-References CapacitorUnit.bottomCutLineNumber, CapacitorUnit.cutLeftLineDict, CapacitorUnit.cutLine(), CapacitorUnit.cutRightLineDict, CapacitorUnit.minheight_topPlatecut, CapacitorUnit.minSpacingOnBotPlate_cut, and CapacitorUnit.minWidth_botPlatecut.
- -Referenced by CapacitorUnit.drawCapacitor().
- -def drawTopPlateCut | -( | -- | self, | -
- | - | - | layer, | -
- | - | - | t | -
- | ) | -- |
Draws the top plate's cuts after computing the maximal number of cuts that can be placed and its exact enclosure in the top plate.
- -References CapacitorUnit.capacitorType, CapacitorUnit.cut2MatrixDict, CapacitorUnit.cutLine(), CapacitorUnit.cutMatrix(), CapacitorUnit.minheight_topPlatecut, CapacitorUnit.minSpacingOnTopPlate_cut, CapacitorUnit.minWidth_topPlatecut, CapacitorUnit.topCutLineDict, and CapacitorUnit.topCutLineNumber.
- -Referenced by CapacitorUnit.drawCapacitor().
- -def drawRoutingLayers | -( | -- | self, | -
- | - | - | bottomPlateLayer, | -
- | - | - | topPlateLayer, | -
- | - | - | t, | -
- | - | - | b | -
- | ) | -- |
Draws the routing layers of both bottom and top plates after computing widths and the exact position of these layers.
-Also computes positions if rlayers that are crucial for routing.
- -References CapacitorUnit.bottomPlateRLayerDict, CapacitorUnit.cutLeftLineDict, CapacitorUnit.cutRightLineDict, and CapacitorUnit.topPlateRLayerDict.
- -Referenced by CapacitorUnit.drawCapacitor().
- -def cutMaxNumber | -( | -- | self, | -
- | - | - | width_layer, | -
- | - | - | width_cut, | -
- | - | - | spacing_cut, | -
- | - | - | enclosure_cut | -
- | ) | -- |
Computes the maximal number of cuts to be placed on a layer of width width_layer
considering specifications such as the spacing between the cuts, its width and its enclosure in the layer.
Referenced by CapacitorUnit.computeBottomPlateCuts(), and CapacitorUnit.computeTopPlateCuts().
- -def cutLine | -( | -- | self, | -
- | - | - | net, | -
- | - | - | layer, | -
- | - | - | firstCutXCenter, | -
- | - | - | firstCutYCenter, | -
- | - | - | width_cut, | -
- | - | - | height_cut, | -
- | - | - | spacing_cut, | -
- | - | - | cutNumber, | -
- | - | - | direction | -
- | ) | -- |
Creates a horizontal or vertical line of contacts according to the specified direction.
- -Referenced by CapacitorUnit.cutMatrix(), CapacitorUnit.drawBottomPlateCut(), and CapacitorUnit.drawTopPlateCut().
- -def cutMatrix | -( | -- | self, | -
- | - | - | net, | -
- | - | - | layer, | -
- | - | - | firstCutXCenter, | -
- | - | - | firstCutYCenter, | -
- | - | - | width_cut, | -
- | - | - | height_cut, | -
- | - | - | spacing_cut, | -
- | - | - | cutColumnNumber, | -
- | - | - | cutRowNumber | -
- | ) | -- |
Creates a matrix of cuts by vertically stacking horizontal lines of identical cuts.
-net | net to which the cuts belong |
layer | cuts physical layer |
firstCutXCenter | center's abcissa of the bottom left cut ( that is the first cut to be drawn in the matrix ) |
firstCutYCenter | center's abcissa of the bottom left cut |
(width_cut,height_cut,spacing_cut) | cuts dimenions |
(cutColumnNumber,cutRowNumber) | matrix dimensions |
References CapacitorUnit.cutLine().
- -Referenced by CapacitorUnit.drawTopPlateCut().
- -def getBottomPlateYMax | -( | -- | self | ) | -- |
dySource
of the bottom plate's box ) . References CapacitorUnit.bottomPlateBoxDict.
- -def getBottomPlateLeftCutXMin | -( | -- | self | ) | -- |
def getBottomPlateLeftCutYMin | -( | -- | self | ) | -- |
def getBottomPlateLeftCutYMax | -( | -- | self | ) | -- |
References CapacitorUnit.bottomCutLineNumber, CapacitorUnit.minSpacingOnBotPlate_cut, and CapacitorUnit.minWidth_botPlatecut.
- -def getBottomPlateRightCutXMin | -( | -- | self | ) | -- |
def getBottomPlateRightCutYMin | -( | -- | self | ) | -- |
Referenced by CapacitorUnit.getBottomPlateRightCutYCenter().
- -def getBottomPlateRightCutYMax | -( | -- | self | ) | -- |
References CapacitorUnit.bottomCutLineNumber, CapacitorUnit.minSpacingOnBotPlate_cut, and CapacitorUnit.minWidth_botPlatecut.
- -Referenced by CapacitorUnit.getBottomPlateRightCutYCenter().
- -def getBotPlateLeftRLayerXMax | -( | -- | self | ) | -- |
def getBottomPlateRightCutYCenter | -( | -- | self | ) | -- |
References CapacitorUnit.getBottomPlateRightCutYMax(), and CapacitorUnit.getBottomPlateRightCutYMin().
- -def getBotPlateLeftRLayerXMin | -( | -- | self | ) | -- |
def getBotPlateRLayerYMin | -( | -- | self | ) | -- |
def getBotPlateRLayerYMax | -( | -- | self | ) | -- |
def getBotPlateRLayerWidth | -( | -- | self | ) | -- |
def getBotPlateRightRLayerXCenter | -( | -- | self | ) | -- |
def getBotPlateLeftRLayerXCenter | -( | -- | self | ) | -- |
def getTopPlateRLayerYMin | -( | -- | self | ) | -- |
def getTopPlateRLayerYMax | -( | -- | self | ) | -- |
def getTopPlateRLayerWidth | -( | -- | self | ) | -- |
def getTopPlateRLayerXCenter | -( | -- | self | ) | -- |
def getTopPlateRLayerXMin | -( | -- | self | ) | -- |
References CapacitorUnit.topPlateRLayerDict.
- -def getTopPlateRLayerXMax | -( | -- | self | ) | -- |
References CapacitorUnit.topPlateRLayerDict.
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Oroshi - Analog Devices Layouts | -Copyright © 2018-2018 UPMC. All rights reserved | -
This is the complete list of members for VerticalRoutingTracks, including all inherited members.
-__setStretching__ | VerticalRoutingTracks | |
drawVRoutingTracks | VerticalRoutingTracks | |
setRules | VerticalRoutingTracks |
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Oroshi - Analog Devices Layouts | -Copyright © 2018-2018 UPMC. All rights reserved | -
Route two matched capacitors, C1 and C2, drawn in a capacitor matrix. - More...
- -Inherits CapacitorUnit, and CapacitorStack.
--Public Member Functions | |
def | __setStretching__ |
Sets vertical stretching value considering spacing between elementary capacitors in the matrix. More... | |
def | setRules |
Defines technology rules used to draw the layout. More... | |
def | drawVRoutingTracks |
Iteratively draws vertical routing tracks given the physical layer vRoutingTracksLayer . More... | |
Route two matched capacitors, C1 and C2, drawn in a capacitor matrix.
-Connections are put in place with reference to a given matching scheme. Elementary capacitor units are connected to horizontal and vertical routing tracks that represent top plates and bottom plates nets of C1 and C2. Supported types of capacitors are Poly-Poly and Metal-Metal. Technologycal rules are provided by 350 nm AMS CMOS technology with three-four metal layers. Metal layers that are used for routeing are placed similarly to horziontal-vertical (HV) symbolic Alliance CAD tool router, where horizontal metal channels are drawn in metal 2 and the vertical ones are in metal 3. Given a matrix of dimensions , the total number of vertical tracks is
equivalent to
couples, ensuring that every elementary capacitor is positioned between four vertical tracks, two from each side. In fact, every adjacent couple of these tracks represent top plates and bottom plates of C1 or C2 as shown in Figure 1.
An elementary capacitor unit can be a part of C1 or C2 according to the matching scheme. However, to respect common-centroid layout specifications, for C1 and C2 to be equal, the matrix number of colums and number of rows must be both even. Addionnally, the number of elementary capacitors dedicated to C1 must be equal to those dedicated to C2. These two conditions are tested in one of the class methods. An exception is raised if at least one of the two is not respected.
-def __setStretching__ | -( | -- | self | ) | -- |
Sets vertical stretching value considering spacing between elementary capacitors in the matrix.
-References VerticalRoutingTracks.abutmentBox_spacing, CapacitorStack.abutmentBox_spacing, and RoutMatchedCapacitor.abutmentBox_spacing.
- -Referenced by RoutMatchedCapacitor.computeHRLayerYCenter(), and VerticalRoutingTracks.drawVRoutingTracks().
- -def setRules | -( | -- | self | ) | -- |
Defines technology rules used to draw the layout.
-Some of the rules, namely those describing routeing layers and tracks are applicable for both MIM and PIP capacitors. However, cuts rules are different.
-CapacitorStack
class rules are also reloaded in this class. An exception is raised if the entered capacitor type is unsupported. References VerticalRoutingTracks.capacitorsNumber, CapacitorStack.capacitorsNumber, VerticalRoutingTracks.computeVRTDimensions(), VerticalRoutingTracks.drawVRoutingTracks(), VerticalRoutingTracks.minEnclosure_hRoutingLayer_vRoutingTrack_cut, VerticalRoutingTracks.minEnclosure_hRoutingTrackCut, VerticalRoutingTracks.minimizeVRTs(), VerticalRoutingTracks.minSpacing_hRoutingTrack, RoutMatchedCapacitor.minSpacing_hRoutingTrack, VerticalRoutingTracks.minWidth_hRoutingLayer, VerticalRoutingTracks.minWidth_hRoutingLayer_vRoutingTrack_cut, VerticalRoutingTracks.minWidth_hRoutingTrack, VerticalRoutingTracks.minWidth_hRoutingTrackCut, VerticalRoutingTracks.setRules(), CapacitorStack.setRules(), CapacitorUnit.setRules(), and RoutMatchedCapacitor.setRules().
- -Referenced by VerticalRoutingTracks.setRules().
- -def drawVRoutingTracks | -( | -- | self, | -
- | - | - | vRoutingTracksLayer | -
- | ) | -- |
Iteratively draws vertical routing tracks given the physical layer vRoutingTracksLayer
.
Every elementary capacitor is consequently positioned between four routing tracks, two from each side. Each couple of adjacent routeing tracks represent top plate and bottom plate nets of Ci, where i is in [1,2]. As given in Figure 2, capacitor with an even j value situated in even columns have and inversely for odd columns numbers.
References VerticalRoutingTracks.__computeVRTsNumber__(), VerticalRoutingTracks.__findCapIdsToEliminate__(), VerticalRoutingTracks.__findCapIdsToEliminatePerColumn__(), VerticalRoutingTracks.__findUsedCapIdsPerColumn__(), VerticalRoutingTracks.__findVRTsToEliminate__(), VerticalRoutingTracks.__setNetsDistribution__(), VerticalRoutingTracks.__setPlatesDistribution__(), VerticalRoutingTracks.__setStretching__(), VerticalRoutingTracks.__setVRTsDistribution__(), VerticalRoutingTracks.abutmentBox_spacing, CapacitorStack.abutmentBox_spacing, RoutMatchedCapacitor.abutmentBox_spacing, VerticalRoutingTracks.capacitorIds, VerticalRoutingTracks.capacitorsNumber, CapacitorStack.capacitorsNumber, VerticalRoutingTracks.computeXCenters(), VerticalRoutingTracks.dummyElement, CapacitorStack.dummyElement, RoutMatchedCapacitor.dummyElement, VerticalRoutingTracks.dummyRing, CapacitorStack.dummyRing, RoutMatchedCapacitor.dummyRing, VerticalRoutingTracks.getVTrackYMax(), VerticalRoutingTracks.getVTrackYMin(), CapacitorUnit.hpitch, RoutMatchedCapacitor.hRoutingTrack_width, VerticalRoutingTracks.hRoutingTrack_width, VerticalRoutingTracks.matchingScheme, CapacitorStack.matchingScheme, CapacitorStack.matrixDim, VerticalRoutingTracks.matrixDim, RoutMatchedCapacitor.maximumPosition, VerticalRoutingTracks.maximumPosition, CapacitorUnit.metal2Width, VerticalRoutingTracks.minEnclosure_hRoutingTrackCut, VerticalRoutingTracks.minimizeVRT, RoutMatchedCapacitor.minimumPosition, VerticalRoutingTracks.minimumPosition, VerticalRoutingTracks.minWidth_hRoutingTrack, VerticalRoutingTracks.minWidth_hRoutingTrackCut, VerticalRoutingTracks.nets, CapacitorStack.nets, VerticalRoutingTracks.platesDistribution, VerticalRoutingTracks.vRoutingTrack_width, CapacitorStack.vRoutingTrack_width, VerticalRoutingTracks.vRoutingTrackDict, RoutMatchedCapacitor.vRoutingTrackDict, VerticalRoutingTracks.vRoutingTrackXCenter, RoutMatchedCapacitor.vRoutingTrackXCenter, VerticalRoutingTracks.vRTsDistribution, RoutMatchedCapacitor.vRTsDistribution, and VerticalRoutingTracks.vRTsToEliminate.
- -Referenced by VerticalRoutingTracks.setRules().
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Oroshi - Analog Devices Layouts | -Copyright © 2018-2018 UPMC. All rights reserved | -
This is the complete list of members for Stack, including all inherited members.
-__init__ | Stack | |
computeDimensions | Stack | |
doLayout | Stack | |
setWirings | Stack |
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Oroshi - Analog Devices Layouts | -Copyright © 2018-2018 UPMC. All rights reserved | -
Draw a Stack of Transistors. - More...
- -Inherits object.
--Public Member Functions | |
def | __init__ |
[API] Constructor More... | |
def | setWirings |
[API] Set the Stack wiring specification. More... | |
def | computeDimensions |
[internal] Compute Stack dimensions from the technological rules. More... | |
def | doLayout |
[API] Draw the complete layout. More... | |
Draw a Stack of Transistors.
-A Stack of Transistors is a set of transistor put into a regular band and connected through their sources/drains. All share the exact same W & L. The way they are connecteds defines what functionnality the Stack implement.
-The abutment box of the stack is adjusted so that both height and width are even multiples of the track pitches, so the device can be easily placed and handled by the mixed router. The extra space needed for padding is added around the active area. Due to the presence of tracks at the top and bottom of the stack, the active area will be horizontally centered but not vertically.
-The drawing of the stack is controlled through a set of variables (attributes) that allows to create it regardless of the technology. The technology is taken into account in the way those variables are computed and, obviously, their values. The following schematics details the main stack drawing variables along with their computations.
-self.gatePitch
: the pitch of transistors gates, inside the stack. It also applies to dummy transistors.self.activeSideWidth
: the distance between the axis of the last transistor gate (on the left or right) and the edge of the active area (not the diffusion area).self.hTrackDistance
: the minimal distance between either the top or bottom edge of the active area and the axis of the first track.self.xpitches
: the number of vertical track pitches needed to fully enclose the active area.self.ypitches
: the number of horizontal track pitches needed to fully enclose the active area.self.activeOffsetX
& self.activeOffsetY
: the offsets of the active area from the bottom left corner of the abutment box.self.diffusionWidth
& self.diffusionHeight
are the minimun dimensions required to fit the active area.self.topTracksNb()
: the number of tracks at the top of the stack.self.botTracksNb()
: the number of tracks at the bottom of the stack.Stack routing is done through vertical metal1
wires coming from the gates and diffusions areas and metal2
horizontal wires that can be either above or below the active area. metal2
wires (or track) goes through the whole stack and are assigned to one net only. A net will have at least one track above or below and may have both.
The connections to the diffusions areas and gates of the various fingers are specified through a list. The stack is made of a regular alternation of diffusions and gates. The list tells, for each one starting from the left, to which net and track they are connected. For a stack of transistor fingers, the must wiring specification must contains
elements. The list is given through one string with each elements separated by one or more whitespace. The syntax for one element is detailed Atomic Wiring Specification.
Track numbering scheme
-Tracks above (top) the active area and below (bottom) each have their own numbering. In both case, the count start from the active area. This, the top tracks will be numbered by increasing Y and the bottom tracks by decreasing Y.
-Track/Net assignement
-The track/net assignement is deduced from the atomic wiring specifications. It also allows to compute the total number of tracks needed above and below the active area.
-An atomic wiring specification has the same syntax for either diffusions or gates. It must not comprise any whitespaces. it is made of the following parts:
-"t"
) or below ("b"
). The special case ("z"
) means that this element must be left unconnected (is such case possible?).The __setattr__()
and __getattr__
functions have been redefined so that the technological values (rules) can be accessed has normal attributes of the Stack class, in addition to the regular ones.
def __init__ | -( | -- | self, | -
- | - | - | device, | -
- | - | - | NERC, | -
- | - | - | NIRC | -
- | ) | -- |
[API] Constructor
-param rules The physical rule set.
-device | The Hurricane AMS device into which the layout will be drawn. |
NERC | Number of contact rows in external (first & last) diffusion connectors. |
NIRC | Number of contact rows in middle diffusion connectors. param w The width of every transistor of the stack (aka fingers). param L The length of every transistor. param NFs The total number of fingers (dummies includeds). param NDs The number of dummies to put on each side of the stack. |
References Stack.bImplantLayer, Stack.botTracks, Stack.botWTracks, Stack.bulkNet, Stack.bulks, Stack.device, Stack.dimensioned, Bulk.flags, Stack.flags, Stack.isNmos(), Stack.L, Stack.metaTnb(), Stack.metaTransistors, Stack.NDs, Stack.NERC, Stack.NFs, Stack.NIRC, Stack.tImplantLayer, Stack.topTracks, Stack.topWTracks, Stack.w, Stack.wellLayer, and Stack.wirings.
- -def setWirings | -( | -- | self, | -
- | - | - | wiringSpec | -
- | ) | -- |
[API] Set the Stack wiring specification.
-wiringSpec | A string defining the connections for the gates and diffusion areas. |
For a comprehensive explanation of the wiring specification, refers to Wiring Specifications .
- -References Stack.botTracks, Stack.botTracksNb(), Stack.botWTracks, Stack.bulkNet, Stack.computeDimensions(), Stack.device, Stack.dimensioned, Stack.eDiffMetal1Width, Bulk.flags, Stack.flags, Stack.gatePitch, Stack.getBotTrackY(), Stack.getHorizontalWidth(), Stack.horPitch, Stack.L, Stack.metal1ToGate, Stack.metaTransistors, Stack.sideActiveWidth, Stack.topTracks, Stack.topTracksNb(), Stack.topWTracks, Stack.wirings, and Stack.ypitches.
- -def computeDimensions | -( | -- | self | ) | -- |
[internal] Compute Stack dimensions from the technological rules.
-Internal function. Perform the computation of:
-self.metal1Pitch
self.minWidth_metal1
self.metal2Pitch
self.minWidth_metal2
self.gatePitch
self.sideActiveWidth
self.hTrackDistance
self.xpitches
self.ypitches
self.activeOffsetX
self.activeOffsetY
self.boundingBox
References Stack.activeBox, Stack.activeOffsetX, Stack.activeOffsetY, Stack.bbHeight, Stack.bbWidth, Stack.botWTracks, Stack.boundingBox, Stack.bulks, Stack.bulkWidth, Stack.computeLayoutParasitics(), Stack.computeStressEffect(), Stack.contactDiffPitch, Stack.contactDiffSide, Stack.DGG, Stack.DGI, Stack.dimensioned, Stack.DMCG, Stack.DMCGT, Stack.DMCI, Stack.eDiffMetal1Width, Bulk.flags, Stack.flags, Stack.gatePitch, Stack.gateVia1Pitch, Stack.getBotTrackY(), Stack.getHorizontalWidth(), Stack.getLastTopTrackY(), Stack.horPitch, Stack.hTrackDistance, Stack.iDiffMetal1Width, Stack.isVH, Stack.L, Stack.metal1ToGate, Stack.metal2Pitch, Stack.metal2TechnoPitch, Stack.metal3Pitch, Stack.NERC, Stack.NFs, Stack.NIRC, Stack.sideActiveWidth, Stack.tracksNbPitch(), Stack.vBulkDistance, Stack.verPitch, Stack.w, Stack.wire1Width, Stack.wire2Width, Stack.wire3Width, Stack.wirings, Stack.xpitches, and Stack.ypitches.
- -Referenced by CapacitorUnit.create(), Stack.doLayout(), RoutMatchedCapacitor.route(), and Stack.setWirings().
- -def doLayout | -( | -- | self, | -
- | - | - | bbMode | -
- | ) | -- |
[API] Draw the complete layout.
-Draw the commplete layout of the Stack.
- -References Stack.activeOffsetX, Stack.activeOffsetY, Stack.bbWidth, Stack.botTracks, Stack.botWTracks, Stack.boundingBox, Stack.bulkNet, Stack.bulks, Stack.bulkWidth, Stack.computeDimensions(), Stack.contactDiffPitch, Stack.device, Stack.DGG, Stack.DGI, Stack.DMCG, Stack.DMCGT, Stack.DMCI, Stack.drawActive(), Stack.drawGate(), Stack.drawSourceDrain(), Stack.drawWell(), Stack.eDiffMetal1Width, Bulk.flags, Stack.flags, Stack.gatePitch, Stack.gateVia1Pitch, Stack.getBotTrackY(), Stack.getHorizontalAxis(), Stack.getHorizontalWidth(), Stack.getTopTrackY(), Stack.getWiringWidth(), Stack.horPitch, Stack.iDiffMetal1Width, Stack.isBotTrack(), Stack.isVH, Stack.L, Stack.metal1ToGate, Stack.NERC, Stack.NFs, Stack.NIRC, Stack.sideActiveWidth, Stack.tImplantLayer, Stack.topTracks, Stack.topWTracks, Stack.w, Stack.wellLayer, Stack.wire1Width, Stack.wire2Width, Stack.wire3Width, and Stack.wirings.
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Oroshi - Analog Devices Layouts | -Copyright © 2018-2018 UPMC. All rights reserved | -