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coriolis
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Put the clock tree connecting wires farther apart from the corona border. 

* Bug: In cumulus/plugins.chip.powerplane, while building the connexion
    from the corona border to the root of the HTree, the horizontal
    wire at the top was too close from the border causing a minimal
    spacing error in the DRC. Now put two tracks of distance.
This commit is contained in:
Jean-Paul Chaput 2021-04-21 14:16:53 +02:00
parent f2f5f687d0
commit d10961b585
1 changed files with 1 additions and 1 deletions
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2
cumulus/src/plugins/alpha/chip/powerplane.py
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@ -539,7 +539,7 @@ class Builder ( object ):
raise ErrorMessage( 1, 'Cannot build clock terminal as no clock is not known.' ) raise ErrorMessage( 1, 'Cannot build clock terminal as no clock is not known.' )
return return
for i in range(len(self.conf.coronaCks)): for i in range(len(self.conf.coronaCks)):
self._connectClock( self.conf.coronaCks[i], i+1 ) self._connectClock( self.conf.coronaCks[i], i+2 )
def doLayout ( self ): def doLayout ( self ):
with UpdateSession(): with UpdateSession():