Correctly manage clock net isolateds from the main clock.
* New: In Bootstrap, in ccb.py, check if cmake is installed and issue a warning, if not. * New: In Hurricane, added Cell::getDeepNet() to search for a deepnet given a path and a leaf net. This method is slow and must not be used too often. Introduced for Kite::BuildPowerRails(). * Change: In CRL Core, in cmos/alliance.conf, modify the clock name pattern to match the sub-clock signals in the datapath operators. * Bug: In Etesian, do not blindly reset the top cell abutment-box. Do it only if it's empty, otherwise keep it. * Bug: In Kite, in buildPowerRails(), in getRootNet() the management of clock nets was incomplete. The case of unrouted clock nets that where not connected to the top core clock net, like the one in the datapath registers was faulty. They were partly recognized as unrouteds and partly as blockage generating a routing deadlock: routage impossible due to blockage generated from itself... * New: In Stratus1, add a buildModel() utility function to automate the model generation and allow a call by the model name (string). * Change: In Unicorn, in cgt.py, display the Alliance environement.
This commit is contained in:
parent
64ea693d6d
commit
bd3984a313
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@ -52,6 +52,15 @@ def safeImport ( moduleName, symbol=None ):
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return module
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return module
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def checkCMake ():
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child = subprocess.Popen ( ["which", "cmake"], stdout=subprocess.PIPE, stderr=subprocess.PIPE )
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(pid,status) = os.waitpid ( child.pid, 0 )
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status >>= 8
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if status != 0:
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print '[ERROR] The <cmake> program has not been found, please install it.'
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sys.exit(1)
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def guessOs ():
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def guessOs ():
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libDir = 'lib'
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libDir = 'lib'
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osSlsoc7x_64 = re.compile (".*Linux.*(el7|slsoc7).*x86_64.*")
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osSlsoc7x_64 = re.compile (".*Linux.*(el7|slsoc7).*x86_64.*")
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@ -171,6 +180,7 @@ def autoLocate ():
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# CCB Main Part.
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# CCB Main Part.
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autoLocate()
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autoLocate()
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checkCMake()
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parser = optparse.OptionParser ()
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parser = optparse.OptionParser ()
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parser.add_option ( "-g", "--gui" , action="store_true" , dest="gui" , help="Lauch the graphical interface." )
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parser.add_option ( "-g", "--gui" , action="store_true" , dest="gui" , help="Lauch the graphical interface." )
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@ -31,7 +31,7 @@ allianceConfig = \
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, ( 'OUT_PH' , 'ap')
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, ( 'OUT_PH' , 'ap')
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, ( 'POWER' , 'vdd')
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, ( 'POWER' , 'vdd')
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, ( 'GROUND' , 'vss')
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, ( 'GROUND' , 'vss')
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, ( 'CLOCK' , '^ck.*')
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, ( 'CLOCK' , '.*ck.*|.*nck.*')
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, ( 'BLOCKAGE' , '^blockage[Nn]et*')
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, ( 'BLOCKAGE' , '^blockage[Nn]et*')
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, ( 'PAD' , '.*_px$')
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, ( 'PAD' , '.*_px$')
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# The following are only read by the Alliance tool wrappers.
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# The following are only read by the Alliance tool wrappers.
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@ -495,11 +495,13 @@ namespace Etesian {
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Instance* instance = static_cast<Instance*>((*ioccurrence).getEntity());
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Instance* instance = static_cast<Instance*>((*ioccurrence).getEntity());
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Cell* masterCell = instance->getMasterCell();
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Cell* masterCell = instance->getMasterCell();
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if (masterCell->getAbutmentBox().isEmpty()) {
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// Have to check here if the model is fully placed or not.
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// Have to check here if the model is fully placed or not.
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masterCell->setAbutmentBox( topAb );
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masterCell->setAbutmentBox( topAb );
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instance->setTransformation( Transformation() ); // (0,0,ID).
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instance->setTransformation( Transformation() ); // (0,0,ID).
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instance->setPlacementStatus( Instance::PlacementStatus::PLACED );
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instance->setPlacementStatus( Instance::PlacementStatus::PLACED );
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}
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}
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}
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UpdateSession::close();
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UpdateSession::close();
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index_t instanceId = 0;
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index_t instanceId = 0;
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@ -189,6 +189,26 @@ void Cell::setAbutmentBox(const Box& abutmentBox)
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}
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}
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}
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}
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DeepNet* Cell::getDeepNet ( Path path, const Net* leafNet ) const
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// **************************************************************
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{
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if (not (_flags & FlattenedNets)) return NULL;
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Occurrence rootNetOccurrence ( getHyperNetRootNetOccurrence(Occurrence(leafNet,path)) );
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forEach ( Net*, inet, getNets() ) {
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DeepNet* deepNet = dynamic_cast<DeepNet*>( *inet );
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if (not deepNet) continue;
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Occurrence deepNetOccurrence = deepNet->getRootNetOccurrence();
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if ( (rootNetOccurrence.getEntity() == deepNetOccurrence.getEntity())
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and (rootNetOccurrence.getPath () == deepNetOccurrence.getPath ()) )
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return deepNet;
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}
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return NULL;
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}
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void Cell::flattenNets(unsigned int flags)
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void Cell::flattenNets(unsigned int flags)
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// ***************************************
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// ***************************************
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{
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{
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@ -258,6 +258,7 @@ class Cell : public Entity {
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public: Instances getNonLeafInstances() const;
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public: Instances getNonLeafInstances() const;
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public: Instances getNonLeafInstancesUnder(const Box& area) const;
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public: Instances getNonLeafInstancesUnder(const Box& area) const;
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public: Net* getNet(const Name& name) const {return _netMap.getElement(name);};
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public: Net* getNet(const Name& name) const {return _netMap.getElement(name);};
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public: DeepNet* getDeepNet( Path, const Net* ) const;
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public: Nets getNets() const {return _netMap.getElements();};
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public: Nets getNets() const {return _netMap.getElements();};
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public: Nets getGlobalNets() const;
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public: Nets getGlobalNets() const;
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public: Nets getExternalNets() const;
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public: Nets getExternalNets() const;
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@ -53,6 +53,8 @@ namespace {
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using Hurricane::DbU;
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using Hurricane::DbU;
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using Hurricane::Box;
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using Hurricane::Box;
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using Hurricane::Interval;
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using Hurricane::Interval;
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using Hurricane::Net;
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using Hurricane::DeepNet;
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using Hurricane::Horizontal;
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using Hurricane::Horizontal;
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using Hurricane::Vertical;
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using Hurricane::Vertical;
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using Hurricane::RoutingPad;
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using Hurricane::RoutingPad;
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@ -107,6 +109,7 @@ namespace {
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public:
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public:
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GlobalNetTable ( KiteEngine* );
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GlobalNetTable ( KiteEngine* );
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bool isCoreClockNetRouted ( const Net* ) const;
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bool isCoreClockNetRouted ( const Net* ) const;
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inline Cell* getTopCell () const;
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Net* getRootNet ( const Net*, Path ) const;
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Net* getRootNet ( const Net*, Path ) const;
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inline Net* getVdde () const;
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inline Net* getVdde () const;
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inline Net* getVddi () const;
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inline Net* getVddi () const;
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Net* _cki; // Clock net in the pad ring.
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Net* _cki; // Clock net in the pad ring.
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Net* _cko; // Clock net of the core (design).
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Net* _cko; // Clock net of the core (design).
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Net* _blockage;
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Net* _blockage;
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Cell* _topCell;
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};
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};
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inline Cell* GlobalNetTable::getTopCell () const { return _topCell; }
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inline Net* GlobalNetTable::getVdde () const { return _vdde; }
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inline Net* GlobalNetTable::getVdde () const { return _vdde; }
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inline Net* GlobalNetTable::getVddi () const { return _vddi; }
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inline Net* GlobalNetTable::getVddi () const { return _vddi; }
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inline Net* GlobalNetTable::getVsse () const { return _vsse; }
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inline Net* GlobalNetTable::getVsse () const { return _vsse; }
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, _cki (NULL)
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, _cki (NULL)
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, _cko (NULL)
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, _cko (NULL)
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, _blockage(NULL)
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, _blockage(NULL)
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, _topCell (kite->getCell())
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{
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{
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Cell* topCell = kite->getCell();
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if (_topCell == NULL) return;
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if (topCell == NULL) return;
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AllianceFramework* af = AllianceFramework::get();
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AllianceFramework* af = AllianceFramework::get();
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bool hasPad = false;
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bool hasPad = false;
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forEach ( Instance*, iinstance, topCell->getInstances() ) {
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forEach ( Instance*, iinstance, _topCell->getInstances() ) {
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if (af->isPad(iinstance->getMasterCell())) {
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if (af->isPad(iinstance->getMasterCell())) {
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if (not hasPad) {
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if (not hasPad) {
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cmess1 << " o Design has pads, assuming complete chip top structure." << endl;
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cmess1 << " o Design has pads, assuming complete chip top structure." << endl;
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@ -195,7 +200,7 @@ namespace {
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Net* net = iplug->getNet();
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Net* net = iplug->getNet();
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if (not net) {
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if (not net) {
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net = topCell->getNet( masterNet->getName() );
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net = _topCell->getNet( masterNet->getName() );
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if (not net) {
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if (not net) {
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cerr << Error("Missing global net <%s> at chip level.",getString(masterNet->getName()).c_str()) << endl;
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cerr << Error("Missing global net <%s> at chip level.",getString(masterNet->getName()).c_str()) << endl;
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continue;
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continue;
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@ -216,7 +221,7 @@ namespace {
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Net* masterNet = iplug->getMasterNet();
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Net* masterNet = iplug->getMasterNet();
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Net* net = iplug->getNet();
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Net* net = iplug->getNet();
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if (not net) {
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if (not net) {
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net = topCell->getNet( masterNet->getName() );
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net = _topCell->getNet( masterNet->getName() );
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if (not net) {
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if (not net) {
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cerr << Error("Missing global net <%s> at chip level.",getString(masterNet->getName()).c_str()) << endl;
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cerr << Error("Missing global net <%s> at chip level.",getString(masterNet->getName()).c_str()) << endl;
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continue;
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continue;
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@ -249,7 +254,7 @@ namespace {
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_vssiPadNetName = "";
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_vssiPadNetName = "";
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_ckoPadNetName = "";
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_ckoPadNetName = "";
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forEach ( Net*, inet, topCell->getNets() ) {
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forEach ( Net*, inet, _topCell->getNets() ) {
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if (NetRoutingExtension::isManualGlobalRoute(*inet)) continue;
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if (NetRoutingExtension::isManualGlobalRoute(*inet)) continue;
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Net::Type netType = inet->getType();
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Net::Type netType = inet->getType();
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@ -368,6 +373,7 @@ namespace {
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Net* GlobalNetTable::getRootNet ( const Net* net, Path path ) const
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Net* GlobalNetTable::getRootNet ( const Net* net, Path path ) const
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{
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{
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ltrace(300) << " getRootNet:" << path << ":" << net << endl;
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ltrace(300) << " getRootNet:" << path << ":" << net << endl;
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if (net == _blockage) return _blockage;
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if (net == _blockage) return _blockage;
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if (_vdde and (net->getName() == _vdde->getName())) return _vdde;
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if (_vdde and (net->getName() == _vdde->getName())) return _vdde;
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@ -379,6 +385,17 @@ namespace {
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return NULL;
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return NULL;
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}
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}
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DeepNet* deepClockNet = getTopCell()->getDeepNet( path, net );
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if (deepClockNet) {
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ltrace(300) << " Deep Clock Net:" << deepClockNet
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<< " state:" << NetRoutingExtension::getFlags(deepClockNet) << endl;
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return NetRoutingExtension::isFixed(deepClockNet) ? _blockage : NULL;
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} else {
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ltrace(300) << " Top Clock Net:" << net
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<< " state:" << NetRoutingExtension::getFlags(net) << endl;
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}
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// Track up, *only* for clocks.
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// Track up, *only* for clocks.
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const Net* upNet = net;
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const Net* upNet = net;
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@ -124,7 +124,6 @@ namespace Kite {
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Horizontal* horizontal = dynamic_cast<Horizontal*>(*icomponent);
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Horizontal* horizontal = dynamic_cast<Horizontal*>(*icomponent);
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if (horizontal) {
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if (horizontal) {
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cerr << horizontal << endl;
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segments.push_back( horizontal );
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segments.push_back( horizontal );
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isPreRouted = true;
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isPreRouted = true;
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if (horizontal->getWidth() != Session::getWireWidth(horizontal->getLayer()))
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if (horizontal->getWidth() != Session::getWireWidth(horizontal->getLayer()))
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@ -132,7 +131,6 @@ namespace Kite {
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} else {
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} else {
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Vertical* vertical = dynamic_cast<Vertical*>(*icomponent);
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Vertical* vertical = dynamic_cast<Vertical*>(*icomponent);
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if (vertical) {
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if (vertical) {
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cerr << vertical << endl;
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isPreRouted = true;
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isPreRouted = true;
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segments.push_back( vertical );
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segments.push_back( vertical );
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if (vertical->getWidth() != Session::getWireWidth(vertical->getLayer()))
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if (vertical->getWidth() != Session::getWireWidth(vertical->getLayer()))
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@ -140,7 +138,6 @@ namespace Kite {
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} else {
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} else {
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Contact* contact = dynamic_cast<Contact*>(*icomponent);
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Contact* contact = dynamic_cast<Contact*>(*icomponent);
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if (contact) {
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if (contact) {
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cerr << contact << endl;
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isPreRouted = true;
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isPreRouted = true;
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contacts.push_back( contact );
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contacts.push_back( contact );
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if ( (contact->getWidth () != Session::getViaWidth(contact->getLayer()))
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if ( (contact->getWidth () != Session::getViaWidth(contact->getLayer()))
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@ -1,7 +1,7 @@
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#!/usr/bin/python
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#!/usr/bin/python
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#
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#
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# This file is part of the Coriolis Software.
|
# This file is part of the Coriolis Software.
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# Copyright (c) UPMC/LIP6 2008-2012, All Rights Reserved
|
# Copyright (c) UPMC 2008-2014, All Rights Reserved
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#
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#
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# +-----------------------------------------------------------------+
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# +-----------------------------------------------------------------+
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# | C O R I O L I S |
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# | C O R I O L I S |
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@ -16,6 +16,7 @@
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try:
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try:
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import sys
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import sys
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import traceback
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import Cfg
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import Cfg
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import CRL
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import CRL
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@ -63,3 +64,44 @@ except Exception, e:
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print ' modules. Something may be wrong at Python/C API level.\n'
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print ' modules. Something may be wrong at Python/C API level.\n'
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print ' %s' % e
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print ' %s' % e
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sys.exit(2)
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sys.exit(2)
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DoNetlist = 0x0001
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DoLayout = 0x0002
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DoStop = 0x0004
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def buildModel ( name, flags ):
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try:
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module = __import__( name, globals(), locals(), name )
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if not module.__dict__.has_key(name):
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print '[ERROR] Stratus module <%s> do not contains a design of the same name.' % name
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sys.exit(1)
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print ' - Generating Stratus Model <%s>' % name
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model = module.__dict__[name](name)
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model.Interface()
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if flags & DoNetlist: model.Netlist()
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if flags & DoLayout: model.Layout ()
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stopLevel=0
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if flags & DoStop: stopLevel = 1
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model.View(stopLevel, 'Model %s' % name)
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model.Save(LOGICAL|PHYSICAL)
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|
except ImportError, e:
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module = str(e).split()[-1]
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|
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||||||
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print '[ERROR] The <%s> Stratus design cannot be loaded.' % module
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print ' Please check your design hierarchy.'
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sys.exit(1)
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|
except Exception, e:
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|
print '[ERROR] A strange exception occurred while loading the Stratus'
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print ' design <%s>. Please check that module for error:\n' % name
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traceback.print_tb(sys.exc_info()[2])
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|
print ' %s' % e
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sys.exit(2)
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|
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framework = CRL.AllianceFramework.get()
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|
return framework.getCell( name, CRL.Catalog.State.Views )
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|
|
|
@ -121,6 +121,7 @@ if __name__ == '__main__':
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args.insert(0, 'cgt')
|
args.insert(0, 'cgt')
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|
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af = CRL.AllianceFramework.get()
|
af = CRL.AllianceFramework.get()
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|
print af.getEnvironment().getPrint()
|
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|
|
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#Hurricane.trace(True)
|
#Hurricane.trace(True)
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Cfg.Configuration.pushDefaultPriority(Cfg.Parameter.Priority.CommandLine)
|
Cfg.Configuration.pushDefaultPriority(Cfg.Parameter.Priority.CommandLine)
|
||||||
|
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