The VST driver may suppress linkage type.
* Change: In Vhdl:::Signal::toVhdlPort(), in Alliance VST signal with undefined directions are typed "linkage". This may not be compatible with vasy, so allow to replace them by "in". * New: In CRL::Catalog::State, add a new flag VstNoLinkage to tell if the VST driver should not use the "linkage" type. * Change: In Vhdl::Entity, add a VstNoLinkage flag to disable the use of the "linkage" type.
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1ccb9c340f
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@ -281,7 +281,9 @@ namespace Vhdl {
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for ( auto isignal=internalSignals.begin(); isignal!=internalSignals.end() ; ++isignal ) {
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for ( auto isignal=internalSignals.begin(); isignal!=internalSignals.end() ; ++isignal ) {
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out << tab;
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out << tab;
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(*isignal)->toVhdlPort( out, width, Entity::AsInnerSignal|(_flags & Entity::IeeeMode) );
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(*isignal)->toVhdlPort( out, width, Entity::AsInnerSignal
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|(_flags & Entity::IeeeMode)
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|(_flags & Entity::VstNoLinkage) );
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out << ";\n";
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out << ";\n";
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}
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}
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out << "\n";
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out << "\n";
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@ -305,7 +307,9 @@ namespace Vhdl {
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size_t ioCount = 0;
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size_t ioCount = 0;
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for ( auto isignal=ioSignals.begin(); isignal!=ioSignals.end() ; ++isignal ) {
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for ( auto isignal=ioSignals.begin(); isignal!=ioSignals.end() ; ++isignal ) {
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if (ioCount) out << "\n" << tab << " ; ";
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if (ioCount) out << "\n" << tab << " ; ";
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(*isignal)->toVhdlPort( out, width, Entity::AsPortSignal|(_flags & Entity::IeeeMode ) );
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(*isignal)->toVhdlPort( out, width, Entity::AsPortSignal
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|(_flags & Entity::IeeeMode)
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|(_flags & Entity::VstNoLinkage ) );
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++ioCount;
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++ioCount;
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}
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}
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out << "\n" << tab << " );";
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out << "\n" << tab << " );";
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@ -33,6 +33,7 @@ namespace Vhdl {
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: _name(name)
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: _name(name)
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{ }
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{ }
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Signal::~Signal ()
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Signal::~Signal ()
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{ }
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{ }
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@ -54,7 +55,9 @@ namespace Vhdl {
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case Net::Direction::IN: out << "in"; break;
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case Net::Direction::IN: out << "in"; break;
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case Net::Direction::OUT: out << "out"; break;
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case Net::Direction::OUT: out << "out"; break;
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case Net::Direction::INOUT: out << "inout"; break;
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case Net::Direction::INOUT: out << "inout"; break;
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default: out << "linkage";
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default:
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if (flags & Entity::VstNoLinkage) out << "in";
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else out << "linkage";
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}
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}
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}
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}
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@ -42,6 +42,7 @@ namespace CRL {
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unsigned int entityFlags = Vhdl::Entity::EntityMode /* | Vhdl::Entity::IeeeMode */;
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unsigned int entityFlags = Vhdl::Entity::EntityMode /* | Vhdl::Entity::IeeeMode */;
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if (saveState & Catalog::State::VstUseConcat ) entityFlags |= Vhdl::Entity::VstUseConcat;
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if (saveState & Catalog::State::VstUseConcat ) entityFlags |= Vhdl::Entity::VstUseConcat;
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if (saveState & Catalog::State::VstNoLowerCase) entityFlags |= Vhdl::Entity::VstNoLowerCase;
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if (saveState & Catalog::State::VstNoLowerCase) entityFlags |= Vhdl::Entity::VstNoLowerCase;
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if (saveState & Catalog::State::VstNoLinkage ) entityFlags |= Vhdl::Entity::VstNoLinkage;
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//NamingScheme::toVhdl( cell, NamingScheme::FromVerilog );
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//NamingScheme::toVhdl( cell, NamingScheme::FromVerilog );
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Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell, entityFlags );
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Vhdl::Entity* vhdlEntity = Vhdl::EntityExtension::create( cell, entityFlags );
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@ -88,6 +88,7 @@ namespace CRL {
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, Foreign = 1 << 8
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, Foreign = 1 << 8
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, VstUseConcat = 1 << 9
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, VstUseConcat = 1 << 9
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, VstNoLowerCase = 1 << 10
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, VstNoLowerCase = 1 << 10
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, VstNoLinkage = 1 << 11
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, Views = Physical|Logical
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, Views = Physical|Logical
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};
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};
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// Constructors.
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// Constructors.
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@ -66,9 +66,10 @@ namespace Vhdl {
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, AsInnerSignal = 0x0010
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, AsInnerSignal = 0x0010
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, VstUseConcat = 0x0020
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, VstUseConcat = 0x0020
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, VstNoLowerCase = 0x0040
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, VstNoLowerCase = 0x0040
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, OptionMask = VstUseConcat|VstNoLowerCase
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, VstNoLinkage = 0x0080
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, OptionMask = VstUseConcat|VstNoLowerCase|VstNoLinkage
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};
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};
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const unsigned int ModeMask = VstUseConcat|VstNoLowerCase;
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const unsigned int ModeMask = VstUseConcat|VstNoLowerCase|VstNoLinkage;
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public:
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public:
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static std::vector<Entity*>&
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static std::vector<Entity*>&
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getAllEntities ();
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getAllEntities ();
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@ -147,6 +147,7 @@ extern "C" {
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LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Foreign ,"Foreign");
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LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Foreign ,"Foreign");
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LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstUseConcat ,"VstUseConcat");
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LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstUseConcat ,"VstUseConcat");
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LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstNoLowerCase ,"VstNoLowerCase");
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LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstNoLowerCase ,"VstNoLowerCase");
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LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::VstNoLinkage ,"VstNoLinkage");
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LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Views ,"Views");
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LoadObjectConstant(PyTypeCatalogState.tp_dict,Catalog::State::Views ,"Views");
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}
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}
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