Clocks in BLIF parser. In RSavePlugin, flags to select views to save.

* Bug: In CRL Core, in BlifParser, recognize clocks (Alliance patterns).
* Change: In Cumulus, in RSavePlugin, "kw" manage a new "views" to
    specify which views must be saved. Physical by default, but sometimes
    we need logical as well. If the design contains uniquified cells,
    save the logical view.
      In ClockTree, abort the clock tree building if the design has no
    top level clock.
* Change: In Katabatic, in GCellTopology, adds 2G_5M1 configuration.
* Bug: Kite, in BuildPowerRails, if we are not in a chip the nets
   composing the H-Tree must be protecteds be blockages.
This commit is contained in:
Jean-Paul Chaput 2016-03-26 11:59:32 +01:00
parent b5d3a2ec3c
commit a78882fd5b
6 changed files with 46 additions and 40 deletions

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@ -15,7 +15,6 @@
#include <time.h> #include <time.h>
#include "hurricane/Pin.h" #include "hurricane/Pin.h"
#include "hurricane/Instance.h" #include "hurricane/Instance.h"
#include "hurricane/Net.h" #include "hurricane/Net.h"
@ -28,7 +27,6 @@
#include "hurricane/Layer.h" #include "hurricane/Layer.h"
#include "hurricane/RegularLayer.h" #include "hurricane/RegularLayer.h"
#include "hurricane/Warning.h" #include "hurricane/Warning.h"
#include "Ap.h" #include "Ap.h"
#include "crlcore/Catalog.h" #include "crlcore/Catalog.h"

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@ -366,7 +366,6 @@ namespace {
, _subckts() , _subckts()
, _depth (0) , _depth (0)
{ {
_blifLut.insert( make_pair(getString(_cell->getName()), this) ); _blifLut.insert( make_pair(getString(_cell->getName()), this) );
if (_cell->isTerminal()) if (_cell->isTerminal())
_depth = 1; _depth = 1;
@ -398,17 +397,21 @@ namespace {
Net* Model::mergeNet ( string name, bool isExternal, unsigned int direction ) Net* Model::mergeNet ( string name, bool isExternal, unsigned int direction )
{ {
bool isClock = AllianceFramework::get()->isCLOCK( name );
Net* net = _cell->getNet( name ); Net* net = _cell->getNet( name );
if (not net) { if (not net) {
net = Net::create( _cell, name ); net = Net::create( _cell, name );
net->setExternal ( isExternal ); net->setExternal ( isExternal );
net->setDirection( (Net::Direction::Code)direction ); net->setDirection( (Net::Direction::Code)direction );
if (isClock) net->setType( Net::Type::CLOCK );
} else { } else {
net->addAlias( name ); net->addAlias( name );
if (isExternal) net->setExternal( true ); if (isExternal) net->setExternal( true );
direction &= ~Net::Direction::UNDEFINED; direction &= ~Net::Direction::UNDEFINED;
direction |= net->getDirection(); direction |= net->getDirection();
net->setDirection( (Net::Direction::Code)direction ); net->setDirection( (Net::Direction::Code)direction );
if (isClock) net->setType( Net::Type::CLOCK );
} }
return net; return net;
} }
@ -487,7 +490,6 @@ namespace {
// << "external: <" << netName << ">." // << "external: <" << netName << ">."
// << endl; // << endl;
Net* net = _cell->getNet( netName ); Net* net = _cell->getNet( netName );
Net* masterNet = instance->getMasterCell()->getNet(masterNetName); Net* masterNet = instance->getMasterCell()->getNet(masterNetName);
if(not masterNet) { if(not masterNet) {
ostringstream tmes; ostringstream tmes;
@ -511,7 +513,6 @@ namespace {
throw Error(tmes.str()); throw Error(tmes.str());
} }
Net* plugNet = plug->getNet(); Net* plugNet = plug->getNet();
if (not plugNet) { // Plug not connected yet if (not plugNet) { // Plug not connected yet
@ -526,7 +527,7 @@ namespace {
plugNet->merge( net ); plugNet->merge( net );
} }
if( plugNet->getType() == Net::Type::POWER or plugNet->getType() == Net::Type::GROUND ){ if ( plugNet->getType() == Net::Type::POWER or plugNet->getType() == Net::Type::GROUND ){
ostringstream tmes; ostringstream tmes;
string powType = plugNet->getType() == Net::Type::POWER ? "power" : "ground"; string powType = plugNet->getType() == Net::Type::POWER ? "power" : "ground";
string plugName = plugNet->getName()._getString(); // Name of the original net string plugName = plugNet->getName()._getString(); // Name of the original net

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@ -51,21 +51,23 @@ except Exception, e:
# of abutment box for placement, the netlist view must also # of abutment box for placement, the netlist view must also
# be saved. # be saved.
def rsave ( cell, depth=0 ): def rsave ( cell, views=CRL.Catalog.State.Physical, depth=0 ):
if cell.isTerminal(): return if cell.isTerminal(): return
framework = CRL.AllianceFramework.get() framework = CRL.AllianceFramework.get()
if depth == 0: print ' o Recursive Save-Cell.' if depth == 0: print ' o Recursive Save-Cell.'
print ' %s+ %s (layout).' % ( ' '*(depth*2), cell.getName() ) sviews = 'layout'
views = CRL.Catalog.State.Physical if views & CRL.Catalog.State.Logical: sviews += ',netlist'
print ' %s+ %s (%s).' % ( ' '*(depth*2), cell.getName(), sviews )
if cell.isUniquified(): views |= CRL.Catalog.State.Logical if cell.isUniquified(): views |= CRL.Catalog.State.Logical
framework.saveCell( cell, views ) framework.saveCell( cell, views )
for instance in cell.getInstances(): for instance in cell.getInstances():
masterCell = instance.getMasterCell() masterCell = instance.getMasterCell()
if not masterCell.isTerminal(): if not masterCell.isTerminal():
rsave( masterCell, depth+1 ) rsave( masterCell, views, depth+1 )
return return
@ -89,11 +91,14 @@ def ScriptMain ( **kw ):
cell, editor = plugins.kwParseMain( **kw ) cell, editor = plugins.kwParseMain( **kw )
views = CRL.Catalog.State.Physical
if kw.has_key('views'): views |= kw['views']
if not cell: if not cell:
print WarningMessage( 'No Cell loaded in the editor (yet), nothing done.' ) print WarningMessage( 'No Cell loaded in the editor (yet), nothing done.' )
return 0 return 0
rsave( cell ) rsave( cell, views )
CRL.destroyAllVHDL() CRL.destroyAllVHDL()
except ErrorMessage, e: except ErrorMessage, e:

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@ -124,7 +124,7 @@ class HTree ( GaugeConfWrapper ):
self.masterClock = net self.masterClock = net
break break
if not self.masterClock: if not self.masterClock:
print '[WARNING] Cell %s has no clock net.' % cell.getName() raise ErrorMessage( 3, 'ClockTree: Cell %s has no clock net.' % cell.getName() )
self._createChildNet( self.topBuffer, 'ck_htree' ) self._createChildNet( self.topBuffer, 'ck_htree' )
return return

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@ -699,6 +699,7 @@ namespace {
, Conn_2G_2M1 = CONNEXITY_VALUE( 2, 2, 0, 0, 0 , 0 ) , Conn_2G_2M1 = CONNEXITY_VALUE( 2, 2, 0, 0, 0 , 0 )
, Conn_2G_3M1 = CONNEXITY_VALUE( 2, 3, 0, 0, 0 , 0 ) , Conn_2G_3M1 = CONNEXITY_VALUE( 2, 3, 0, 0, 0 , 0 )
, Conn_2G_4M1 = CONNEXITY_VALUE( 2, 4, 0, 0, 0 , 0 ) , Conn_2G_4M1 = CONNEXITY_VALUE( 2, 4, 0, 0, 0 , 0 )
, Conn_2G_5M1 = CONNEXITY_VALUE( 2, 5, 0, 0, 0 , 0 )
, Conn_2G_1M2 = CONNEXITY_VALUE( 2, 0, 1, 0, 0 , 0 ) , Conn_2G_1M2 = CONNEXITY_VALUE( 2, 0, 1, 0, 0 , 0 )
, Conn_2G_2M2 = CONNEXITY_VALUE( 2, 0, 2, 0, 0 , 0 ) , Conn_2G_2M2 = CONNEXITY_VALUE( 2, 0, 2, 0, 0 , 0 )
, Conn_2G_3M2 = CONNEXITY_VALUE( 2, 0, 3, 0, 0 , 0 ) , Conn_2G_3M2 = CONNEXITY_VALUE( 2, 0, 3, 0, 0 , 0 )
@ -950,6 +951,7 @@ namespace {
case Conn_2G_2M1: case Conn_2G_2M1:
case Conn_2G_3M1: case Conn_2G_3M1:
case Conn_2G_4M1: case Conn_2G_4M1:
case Conn_2G_5M1:
case Conn_3G_1M1: case Conn_3G_1M1:
case Conn_3G_2M1: case Conn_3G_2M1:
case Conn_3G_3M1: case Conn_3G_3M1:

View File

@ -393,6 +393,10 @@ namespace {
return NULL; return NULL;
} }
// Track up, *only* for clocks.
const Net* upNet = net;
if (not path.isEmpty()) {
DeepNet* deepClockNet = getTopCell()->getDeepNet( path, net ); DeepNet* deepClockNet = getTopCell()->getDeepNet( path, net );
if (deepClockNet) { if (deepClockNet) {
ltrace(300) << " Deep Clock Net:" << deepClockNet ltrace(300) << " Deep Clock Net:" << deepClockNet
@ -404,10 +408,6 @@ namespace {
<< " state:" << NetRoutingExtension::getFlags(net) << endl; << " state:" << NetRoutingExtension::getFlags(net) << endl;
} }
// Track up, *only* for clocks.
const Net* upNet = net;
if (not path.isEmpty()) {
Path upPath = path; Path upPath = path;
Instance* instance = NULL; Instance* instance = NULL;
Plug* plug = NULL; Plug* plug = NULL;
@ -441,7 +441,7 @@ namespace {
} }
} }
return NULL; return NetRoutingExtension::isFixed(upNet) ? _blockage : NULL;
} }