We have a semantic issue with the blockages layers. Two meanings are possibles:

1. They represent an exact area where no metal should be put, and that area
   has been computed by the standard cell abstractor and *do not* need to be
   expanded. This is the forbidden area, period!

2. They match the shapes of the components inside the standard cell (say an
   horizontal segment). In that case, the blockage *must be expanded* by the minimal
   spacing rules as any fixed wiring already present.

It is not clear to me what is the accepted norm. This commit stays on semantic [1].

The semantic is implemented in PowerRailsPlanes::Rail::doLayout().
This commit is contained in:
Jean-Paul Chaput 2023-07-22 16:51:26 +02:00
parent 96f41776a8
commit a70382d9f9
1 changed files with 7 additions and 16 deletions

View File

@ -498,8 +498,10 @@ namespace {
delta = plane->getLayerGauge()->getPitch(); delta = plane->getLayerGauge()->getPitch();
} }
} }
if (AllianceFramework::get()->getCellGauge()->getName() == Name("StdCellLib")) { else {
//if (AllianceFramework::get()->getCellGauge()->getName() == Name("StdCellLib")) {
delta = plane->getLayerGauge()->getPitch(); delta = plane->getLayerGauge()->getPitch();
//}
} }
} }
@ -551,22 +553,11 @@ namespace {
axisMax += delta; axisMax += delta;
} }
// if (segment->getId() == 51904) {
// DebugSession::open( 0, 1000 );
// }
Track* track = plane->getTrackByPosition ( axisMin, Constant::Superior ); Track* track = plane->getTrackByPosition ( axisMin, Constant::Superior );
for ( ; track and (track->getAxis() <= axisMax) ; track = track->getNextTrack() ) { for ( ; track and (track->getAxis() <= axisMax) ; track = track->getNextTrack() ) {
TrackElement* element = TrackFixedSegment::create ( track, segment ); TrackElement* element = TrackFixedSegment::create ( track, segment );
cdebug_log(159,0) << " Insert in " << track << "+" << element << endl; cdebug_log(159,0) << " Insert in " << track << "+" << element << endl;
// if (segment->getId() == 51904) {
// cerr << " Insert in " << track << endl;
// cerr << " +" << element << endl;
// }
} }
// if (segment->getId() == 51904) {
// DebugSession::close();
// }
} }
} else { } else {
list<Interval>::iterator ichunk = _chunks.begin(); list<Interval>::iterator ichunk = _chunks.begin();