diff --git a/crlcore/src/ccore/openaccess/OpenAccessCommon.h b/crlcore/src/ccore/openaccess/OpenAccessCommon.h index 6d9fa8dd..dee43061 100644 --- a/crlcore/src/ccore/openaccess/OpenAccessCommon.h +++ b/crlcore/src/ccore/openaccess/OpenAccessCommon.h @@ -1,5 +1,5 @@ // -*-compile-command:"cd ../../../../.. && make"-*- -// Time-stamp: "2010-08-16 16:52:02" - OpenAccessCommon.h +// Time-stamp: "2010-08-24 13:07:42" - OpenAccessCommon.h // x-----------------------------------------------------------------x // | This file is part of the hurricaneAMS Software. | // | Copyright (c) UPMC/LIP6 2008-2010, All Rights Reserved | diff --git a/crlcore/src/ccore/openaccess/OpenAccessDriver.cpp b/crlcore/src/ccore/openaccess/OpenAccessDriver.cpp index f695cbba..798954dd 100644 --- a/crlcore/src/ccore/openaccess/OpenAccessDriver.cpp +++ b/crlcore/src/ccore/openaccess/OpenAccessDriver.cpp @@ -1,5 +1,5 @@ // -*-compile-command:"cd ../../../../.. && make"-*- -// Time-stamp: "2010-08-18 12:19:15" - OpenAccessDriver.cpp +// Time-stamp: "2010-08-24 13:35:19" - OpenAccessDriver.cpp // x-----------------------------------------------------------------x // | This file is part of the hurricaneAMS Software. | // | Copyright (c) UPMC/LIP6 2008-2010, All Rights Reserved | @@ -326,7 +326,8 @@ namespace { cerr << " o get value for constraint" << endl; long minSize = Hurricane::DbU::getDb(layer->getMinimalSize()); long minSpace = Hurricane::DbU::getDb(layer->getMinimalSpacing()); - long pitch = Hurricane::DbU::getDb(layer->getPitch()); +// long pitch = Hurricane::DbU::getDb(layer->getPitch()); + long pitch = 1; oaLayerConstraint* cMinSize = oaLayerConstraint::create(aOALayer->getNumber(), oaLayerConstraintDef::get(oacMinWidth), oaIntValue::create(theOATech,minSize)); @@ -339,6 +340,15 @@ namespace { oaLayerConstraint* cPitchV = oaLayerConstraint::create(aOALayer->getNumber(), oaLayerConstraintDef::get(oacVerticalRouteGridPitch), oaIntValue::create(theOATech,pitch)); + + { + oaConstraintDef *def = oaLayerConstraintDef::get(oacVerticalRouteGridPitch); + oaConstraint *c = oaLayerConstraint::find(getFoundryRules(), + aOALayer->getNumber(), + (oaLayerConstraintDef*) def); + } + + return aOALayer; } @@ -381,7 +391,8 @@ namespace { //create and add foundry constraint group for General manufacturing rules //and add oaSimpleConstraintType too assert(theOATech); - theOATech->getDefaultConstraintGroup();//add the constraint group for oa2lef + //add the constraint group for oa2lef + theOATech->getDefaultConstraintGroup(); oaConstraintGroup *cgFoundry = theOATech->getFoundryRules(); } @@ -569,6 +580,7 @@ namespace { cerr << "toOARect" << endl; assert(component); assert(block); + assert(_oaTech); Component2OARectMap::iterator it = _component2OARect.find(component); if (it != _component2OARect.end()) @@ -576,7 +588,7 @@ namespace { oaRect* rect = oaRect::create(block, toOALayerNum( component->getLayer() ), - oacDrawingPurposeType, + oaPurpose::get(_oaTech ,oacDrawingPurposeType)->getNumber(), toOABox(component->getBoundingBox()) ); return rect; } @@ -588,6 +600,7 @@ namespace { cerr << "toOAPathSeg" << endl; assert(segment); assert(blockNet); + assert(_oaTech); Segment2OAPathSegMap::iterator it = _segment2OAPathSeg.find(segment); if (it != _segment2OAPathSeg.end()) @@ -606,7 +619,7 @@ namespace { oaSegStyle style(segment->getWidth(), oacTruncateEndStyle, oacTruncateEndStyle); res = oaPathSeg::create(blockNet->getBlock(), toOALayerNum( segment->getLayer() ), - oacDrawingPurposeType, + oaPurpose::get(_oaTech ,oacDrawingPurposeType)->getNumber(), p1, p2, style); @@ -975,6 +988,17 @@ namespace { oaBox boundingBox = toOABox(bBox); topBlock->getBBox(boundingBox); } + + oaUInt4 count = 0; + oaIter headers(designCellView->getTopBlock()->getLPPHeaders()); + while (oaLPPHeader* lppHeader = headers.getNext()) { + cout << "Layer Purpose Pair " << ++count << endl; + + oaLayerNum layerNum = lppHeader->getLayerNum(); + oaPurposeNum purpNum = lppHeader->getPurposeNum(); + cout << "\t Layer = " << layerNum << endl; + cout << "\t Purpose = " << purpNum << endl; + } return designCellView; } @@ -1054,6 +1078,7 @@ namespace { namespace CRL { void OpenAccess::oaDriver(const string& path, Cell* cell) { + cerr << "oaDriver" << endl; #ifdef HAVE_OPENACCESS oaCell* convertedCell = NULL; assert(cell); diff --git a/crlcore/src/ccore/openaccess/testDriver/CMakeLists.txt b/crlcore/src/ccore/openaccess/testDriver/CMakeLists.txt deleted file mode 100755 index fa8d564f..00000000 --- a/crlcore/src/ccore/openaccess/testDriver/CMakeLists.txt +++ /dev/null @@ -1,28 +0,0 @@ -PROJECT(testOAWrapper) - -CMAKE_MINIMUM_REQUIRED(VERSION 2.4.0) - -LIST(INSERT CMAKE_MODULE_PATH 0 "$ENV{BOOTSTRAP_TOP}/share/cmake/Modules/") -find_package(Bootstrap REQUIRED) -setup_project_paths(VLSISAPD) -setup_project_paths(CORIOLIS) - -LIST(INSERT CMAKE_MODULE_PATH 0 "${CRLCORE_SOURCE_DIR}/cmake_modules/") - - -LIST(INSERT CMAKE_MODULE_PATH 0 "${CRLCORE_SOURCE_DIR}/cmake_modules/") -LIST(INSERT CMAKE_MODULE_PATH 0 - "$ENV{CHAMS_USER_TOP}/share/cmake/Modules/" - "$ENV{CHAMS_TOP}/share/cmake/Modules/") -print_cmake_module_path() - -FIND_PACKAGE(HURRICANE REQUIRED) -FIND_PACKAGE(CORIOLIS REQUIRED) -FIND_PACKAGE(VLSISAPD REQUIRED) -FIND_PACKAGE(HURRICANEAMS REQUIRED) -FIND_PACKAGE(AMSCORE REQUIRED) -FIND_PACKAGE(Qt4 REQUIRED) # find and setup Qt4 for this project -FIND_PACKAGE(LibXml2 REQUIRED) -FIND_PACKAGE(PythonLibs REQUIRED) - -ADD_SUBDIRECTORY(src) diff --git a/crlcore/src/ccore/openaccess/testDriver/Makefile b/crlcore/src/ccore/openaccess/testDriver/Makefile deleted file mode 100644 index 059e1231..00000000 --- a/crlcore/src/ccore/openaccess/testDriver/Makefile +++ /dev/null @@ -1,38 +0,0 @@ - -TESTDIR= ./testOA -#TECHNOFILE= /dsk/l1/misc/caba/coriolis-2.x/Linux.SLSoC5x/Release.Shared/install/etc/chams/config.freePDK45.xml -TECHNOFILE= /dsk/l1/misc/caba/coriolis-2.x/Linux.SLSoC5x_64/Release.Shared/install/etc/chams/config.freePDK45.xml -M=$$(uname -m) - -all: compile run - -lefTest: - cd sxlib2lef && make - -compile: - ./compile.sh - -run: compile - ./$(M)/usr/local/bin/testOAWrapper $(TECHNOFILE) $(TESTDIR) 2>&1 | tee $@.log - cd $(TESTDIR)/OAdrive && oa2lef -lib sxlib -views layout -lef sxlibFromOA.lef - -debug: compile - gdb -args ./$(M)/usr/local/bin/testOAWrapper $(TECHNOFILE) $(TESTDIR) - -ddd: compile - ddd -args ./$(M)/usr/local/bin/testOAWrapper $(TECHNOFILE) $(TESTDIR) - -valgrind_simple: compile - valgrind ./$(M)/usr/local/bin/testOAWrapper $(TECHNOFILE) $(TESTDIR) 2>&1 | tee $@.log - -valgrind_full: compile - valgrind -v --leak-check=full --show-reachable=yes ./$(M)/usr/local/bin/testOAWrapper $(TECHNOFILE) $(TESTDIR) 2>&1 | tee $@.log - -mrproper: clean - rm -rf $(TESTDIR) *.log .cadence - cd sxlib2lef && make mrproper - -clean: - rm -rf $(M) - -.PHONY: clean mrproper valgrind ddd debug run compile all lefTest diff --git a/crlcore/src/ccore/openaccess/testDriver/cds.lib b/crlcore/src/ccore/openaccess/testDriver/cds.lib deleted file mode 100644 index 1f09f42c..00000000 --- a/crlcore/src/ccore/openaccess/testDriver/cds.lib +++ /dev/null @@ -1,4 +0,0 @@ -DEFINE WorkLibrary /dsk/l1/misc/caba/coriolis-2.x/src/crlcore/src/ccore/openaccess/test/testOA/OAdrive/WorkLibrary -DEFINE myCM_Library /dsk/l1/misc/caba/coriolis-2.x/src/crlcore/src/ccore/openaccess/test/testOA/OAdrive/myCM_Library -DEFINE sxlibFromOA /dsk/l1/misc/caba/coriolis-2.x/src/crlcore/src/ccore/openaccess/test/testOA/OAdrive/sxlib -DEFINE sxlibFromLef /dsk/l1/misc/caba/coriolis-2.x/src/crlcore/src/ccore/openaccess/test/sxlib2lef/sxlib diff --git a/crlcore/src/ccore/openaccess/testDriver/compile.sh b/crlcore/src/ccore/openaccess/testDriver/compile.sh deleted file mode 100755 index bcac6239..00000000 --- a/crlcore/src/ccore/openaccess/testDriver/compile.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash -ARCH=`uname -m` - -if [ ! -e "./compile.sh" ]; then - echo "You must run compile.sh in its own direcotry : ./compile.sh" - exit 1 -fi - -if [ ! -d "$ARCH/build" ]; then - echo "Creating build directory" - mkdir -p $ARCH/build -fi - -cd $ARCH/build && cmake ../.. && make DESTDIR=.. -j2 install diff --git a/crlcore/src/ccore/openaccess/testDriver/display.drf.old b/crlcore/src/ccore/openaccess/testDriver/display.drf.old deleted file mode 100644 index 7923ae62..00000000 --- a/crlcore/src/ccore/openaccess/testDriver/display.drf.old +++ /dev/null @@ -1,3445 +0,0 @@ -;========================================================================== -; -; $Id: display.drf 61 2007-07-24 20:05:21Z mdbucher $ -; -;-------------------------------------------------------------------------- - -drDefineDisplay( -;( DisplayName ) - ( display ) ;-- Screen -- - ( psc ) ;-- Color PS -- - ( psb ) ;-- B&W PS -- -) - - -; ------------------------------------------------------------------- -; ------ Display information for the display device 'display'. ------ -; ------------------------------------------------------------------- - -drDefineColor( -;( DisplayName ColorName Red Green Blue Blink ) -;( ----------- --------- --- ----- ---- ----- ) - ( display white 255 255 255 ) - ( display blinkWhite 255 255 255 t ) - ( display silver 217 230 255 ) - ( display cream 255 255 204 ) - ( display pink 255 191 242 ) - ( display magenta 255 0 255 ) - ( display lime 0 255 0 ) - ( display tan 255 230 191 ) - ( display cyan 0 255 255 ) - ( display cadetBlue 57 191 255 ) - ( display yellow 255 255 0 ) - ( display blinkYellow 255 255 0 t ) ; jts - ( display orange 255 128 0 ) - ( display red 255 0 0 ) - ( display purple 153 0 230 ) - ( display green 0 204 102 ) - ( display brown 191 64 38 ) - ( display blue 0 0 255 ) - ( display slate 140 140 166 ) - ( display gold 217 204 0 ) - ( display maroon 230 31 13 ) - ( display violet 94 0 230 ) - ( display forest 38 140 107 ) - ( display chocolate 128 38 38 ) - ( display navy 51 51 153 ) - ( display black 0 0 0 ) - ( display winBack 224 224 224 ) - ( display winFore 128 0 0 ) - ( display winText 51 51 51 ) - ( display winColor1 166 166 166 ) - ( display winColor2 115 115 115 ) - ( display winColor3 189 204 204 ) - ( display winColor4 204 204 204 ) - ( display winColor5 199 199 199 ) - ( display lightpink 255 196 209 ) - -;---- cmosx below ------------------------------- - ( display gray 204 204 217 ) - ( display volorange 255 164 0 ) - -) - -drDefineStipple( -;( DisplayName StippleName Bitmap ) -;( ----------- ----------- ------ ) - - ( display blank ( - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - ) ) - ( display solid ( - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - ) ) - ( display dots ( - (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - ) ) - ( display hLine ( - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - ) ) - ( display hLine2 ( - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - ) ) - ( display vLine ( - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - ) ) - ( display vLine2 ( - (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1) - ) ) - ( display cross ( - (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) - (0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1) - (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) - (0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1) - (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) - (0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1) - (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) - (0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1) - ) ) - ( display miniHatch ( - (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) - (0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0) - (0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) - (0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0) - (0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - ) ) - ( display grid ( - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - ) ) - ( display slash ( - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) - (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) - (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) - (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) - (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) - (0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0) - (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) - (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) - ) ) - ( display halfslash ( - (0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0) - (0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0) - (0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0) - 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(0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - ) ) - ( display cwellBp ( - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - ) ) - - ( display capID ( - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0) - (0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0) - (0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - ) ) - ( display resID ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 1 1 0 1 0 0 1 1 1 0 0 0 0 0 0 ) - ( 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) - ( display diodeID ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 ) - ( 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 ) - ( 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) - -) - -drDefineLineStyle( -;( DisplayName LineStyle Size Pattern ) -;( ----------- --------- ---- ------- ) - ( display solid 1 (1 1 1) ) - ( display dashed 1 (1 1 1 1 0 0) ) - ( display dots 1 (1 0 0) ) - ( display dashDot 1 (1 1 1 0 0 1 0 0) ) - ( display shortDash 1 (1 1 0 0) ) - ( display doubleDash 1 (1 1 1 1 0 0 1 1 0 0) ) - ( display hidden 1 (1 0 0 0) ) - ( display thickLine 3 (1 1 1) ) - ( display mLine 2 (1 1 1) ) - ) - -drDefinePacket( -;( DisplayName PacketName Stipple LineStyle Fill Outline ) -;( ----------- ---------- ------- --------- ---- ------- ) - ( display default blank solid green green ) - ( display hdrcBnd blank solid white white ) - ( display nwell wellp solid green green ) - ( display nwellNet blank solid green green ) - ( display nwellPin X solid green green ) - ( display pwell wellp solid orange orange ) - ( display pwellNet blank solid orange orange ) - ( display pwellPin X solid orange orange ) - ( display pbase checker2 solid orange orange ) - ( display pbaseNet blank solid orange orange ) - ( display pbasePin X solid orange orange ) - ( display vtg wellvtg dashed blue blue ) - ( display vtgNet blank dashed blue blue ) - ( display vth wellvth dashed blue blue ) - ( display vthNet blank dashed blue blue ) - ( display active contp solid green green ) - ( display activeNet blank solid green green ) - ( display activePin X solid green green ) - ( display thkox thickox solid yellow yellow ) - ( display thkoxLbl blank solid yellow yellow ) - ( display nimplant triangle solid green green ) - ( display pimplant triangle solid orange orange ) - ( display poly checker1 solid red red ) - ( display polyNet blank solid red red ) - ( display polyPin X solid red red ) - ( display polyLbl blank solid red red ) - ( display polyBnd blank solid red red ) - ( display sblock brick solid blue blue ) - ( display highres resID solid blue blue ) - ( display elec checker2 solid yellow yellow ) - ( display elecNet blank solid yellow yellow ) - ( display elecPin X solid yellow yellow ) - ( display elecLbl blank solid yellow yellow ) - ( display elecBnd blank solid yellow yellow ) - ( display metal1 backSlash solid blue blue ) - ( display metal1Net blank solid blue blue ) - ( display metal1Pin X solid blue blue ) - ( display metal1Lbl blank solid blue blue ) - ( display metal1Bnd blank solid blue blue ) - ( display contact X solid black lime ) - ( display contactNe blank solid brown brown ) - ( display contactPin X solid black black ) - ( display contactLbl blank solid black black ) - ( display contactBnd blank solid black black ) - ( display metal2 dots solid magenta magenta ) - ( display metal2Net blank solid magenta magenta ) - ( display metal2Pin X solid magenta magenta ) - ( display metal2Lbl blank solid magenta magenta ) - ( display metal2Bnd blank solid magenta magenta ) - ( display via1 invCross solid magenta navy ) - ( display via1Net blank solid purple black ) - ( display via1Pin X solid purple black ) - ( display via1Lbl blank solid purple black ) - ( display via1Bnd blank solid purple black ) - ( display metal3 halfslash solid cyan cyan ) - ( display metal3Net blank solid cyan cyan ) - ( display metal3Pin X solid cyan cyan ) - ( display metal3Lbl blank solid cyan cyan ) - ( display metal3Bnd blank solid cyan cyan ) - ( display via2 invCross solid cadetBlue cadetBlue ) - ( display via2Net blank solid cadetBlue cadetBlue ) - ( display via2Pin X solid cadetBlue cadetBlue ) - ( display via2Lbl blank solid cadetBlue cadetBlue ) - ( display via2Bnd blank solid cadetBlue cadetBlue ) - ( display metal4 dot4 solid cream cream ) - ( display metal4Net blank solid cream cream ) - ( display metal4Pin X solid cream cream ) - ( display metal4Lbl blank solid cream cream ) - ( display metal4Bnd blank solid cream cream ) - ( display via3 invCross solid tan tan ) - ( display via3Net blank solid tan tan ) - ( display via3Pin X solid tan tan ) - ( display via3Lbl blank solid tan tan ) - ( display via3Bnd blank solid tan tan ) - ( display metal5 metal2S solid cadetBlue cadetBlue ) - ( display metal5Net blank solid cadetBlue cadetBlue ) - ( display metal5Pin X solid cadetBlue cadetBlue ) - ( display metal5Lbl blank solid cadetBlue cadetBlue ) - ( display metal5Bnd blank solid cadetBlue cadetBlue ) - ( display via4 invCross solid blue blue ) - ( display via4Net blank solid blue blue ) - ( display via4Pin X solid blue blue ) - ( display via4Lbl blank solid blue blue ) - ( display via4Bnd blank solid blue blue ) - ( display metal6 miniHatch solid gold gold ) - ( display metal6Net blank solid gold gold ) - ( display metal6Pin X solid gold gold ) - ( display metal6Lbl blank solid gold gold ) - ( display metal6Bnd blank solid gold gold ) - ( display via5 invCross solid yellow yellow ) - ( display via5Net blank solid yellow yellow ) - ( display via5Pin X solid yellow yellow ) - ( display via5Lbl blank solid yellow yellow ) - ( display via5Bnd blank solid yellow yellow ) - ( display metal7 halfslash solid lime lime ) - ( display metal7Net blank solid lime lime ) - ( display metal7Pin X solid lime lime ) - ( display metal7Lbl blank solid lime lime ) - ( display metal7Bnd blank solid lime lime ) - ( display via6 invCross solid magenta magenta ) - ( display via6Net blank solid magenta magenta ) - ( display via6Pin X solid magenta magenta ) - ( display via6Lbl blank solid magenta magenta ) - ( display via6Bnd blank solid magenta magenta ) - ( display metal8 hLine2 solid white white ) - ( display metal8Net blank solid white white ) - ( display metal8Pin X solid white white ) - ( display metal8Lbl blank solid white white ) - ( display metal8Bnd blank solid white white ) - ( display via7 invCross solid cadetBlue cadetBlue ) - ( display via7Net blank solid cadetBlue cadetBlue ) - ( display via7Pin X solid cadetBlue cadetBlue ) - ( display via7Lbl blank solid cadetBlue cadetBlue ) - ( display via7Bnd blank solid cadetBlue cadetBlue ) - ( display metal9 vLine2 solid tan tan ) - ( display metal9Net blank solid tan tan ) - ( display metal9Pin X solid tan tan ) - ( display metal9Lbl blank solid tan tan ) - ( display metal9Bnd blank solid tan tan ) - ( display via8 invCross solid cream cream ) - ( display via8Net blank solid cream cream ) - ( display via8Pin X solid cream cream ) - ( display via8Lbl blank solid cream cream ) - ( display via8Bnd blank solid cream cream ) - ( display metal10 metal2S solid orange orange ) - ( display metal10Net blank solid orange orange ) - ( display metal10Pin X solid orange orange ) - ( display metal10Lbl blank solid orange orange ) - ( display metal10Bnd blank solid orange orange ) - ( display via9 invCross solid blue blue ) - ( display via9Net blank solid blue blue ) - ( display via9Pin X solid blue blue ) - ( display via9Lbl blank solid blue blue ) - ( display via9Bnd blank solid blue blue ) - ( display glass vLine solid slate slate ) - ( display open vCurb solid violet violet ) - ( display openNet blank solid violet violet ) - ( display openPin X solid violet violet ) - ( display openLbl blank solid violet violet ) - ( display openBnd blank solid violet violet ) - ( display pstop dagger solid maroon maroon ) - ( display pstopNet blank solid maroon maroon ) - ( display pstopPin X solid maroon maroon ) - ( display pstopLbl blank solid maroon maroon ) - ( display pstopBnd blank solid maroon maroon ) - ( display pad X doubleDash yellow yellow ) - ( display nodrc X doubleDash cyan cyan ) - ( display nolpe dot3 doubleDash tan tan ) - ( display cap_id capID doubleDash slate slate ) - ( display res_id resID doubleDash slate slate ) - ( display dio_id diodeID doubleDash slate slate ) - ( display metalcap miniHatch solid violet violet ) - ( display metalcapBnd miniHatch solid violet violet ) - ( display metalcapPin X solid violet violet ) - ( display metalcapNet blank solid violet violet ) - ( display metalcapLbl blank solid violet violet ) - ( display background solid solid black black ) - ( display grid blank solid slate slate ) - ( display grid1 blank solid white white ) - ( display axis blank solid white white ) - ( display instance blank solid red red ) - ( display instanceLbl blank solid red red ) - ( display prBoundary blank solid purple purple ) - ( display prBoundaryBnd blank solid cyan cyan ) - ( display prBoundaryLbl blank solid purple purple ) - ( display align blank solid tan tan ) - ( display hardFence blank solid red red ) - ( display softFence blank solid yellow yellow ) - ( display text blank solid white white ) - ( display text1 blank dashed white white ) - ( display text2 solid solid white white ) - ( display border blank solid tan tan ) - ( display device blank solid green green ) - ( display device2 blank dashed green green ) - ( display device1 solid solid green green ) - ( display wire solid solid cadetBlue cadetBlue ) - ( display wireLbl solid solid cadetBlue cadetBlue ) - ( display wireFlt blank dashed red red ) - ( display deviceAnt blank solid yellow yellow ) - ( display deviceLbl blank solid green green ) - ( display pinLbl blank solid red red ) - ( display pin solid solid red red ) - ( display pinAnt blank solid red red ) - ( display annotate blank solid orange orange ) - ( display annotate1 blank solid pink pink ) - ( display annotate2 blank solid lime lime ) - ( display annotate3 blank solid cyan cyan ) - ( display annotate4 blank solid yellow yellow ) - ( display annotate5 blank solid white white ) - ( display annotate6 blank solid silver silver ) - ( display annotate7 blank solid red red ) - ( display annotate8 blank solid tan tan ) - ( display annotate9 blank solid green green ) - ( display edgeLayer blank solid winColor5 winColor5 ) - ( display edgeLayerPin blank solid yellow yellow ) - ( display snap blank solid yellow yellow ) - ( display stretch blank solid yellow yellow ) - ( display y0 blank dashed magenta magenta ) - ( display y1 blank dashed brown brown ) - ( display y2 blank dashed red red ) - ( display y3 blank dashed pink pink ) - ( display y4 blank dashed orange orange ) - ( display y5 blank dashed green green ) - ( display y6 blank dashed blue blue ) - ( display y7 blank dashed purple purple ) - ( display y8 blank dashed gold gold ) - ( display y9 blank dashed silver silver ) - ( display hilite blank thickLine white white ) - ( display hilite1 blank solid magenta magenta ) - ( display hilite2 blank solid orange orange ) - ( display hilite3 blank solid cyan cyan ) - ( display hilite4 blank solid tan tan ) - ( display hilite5 blank solid lime lime ) - ( display hilite6 blank solid orange orange ) - ( display hilite7 blank solid cream cream ) - ( display hilite8 blank solid magenta magenta ) - ( display hilite9 blank solid pink pink ) - ( display implant blank solid orange orange ) - ( display drive blank solid blue blue ) - ( display hiz blank solid orange orange ) - ( display resist blank solid cyan cyan ) - ( display spike blank solid purple purple ) - ( display supply blank solid lime lime ) - ( display unknown blank solid yellow yellow ) - ( display unset blank solid forest forest ) - ( display designFlow solid solid green green ) - ( display designFlow1 solid solid red red ) - ( display designFlow2 solid solid purple purple ) - ( display designFlow3 solid solid pink pink ) - ( display designFlow4 solid solid black black ) - ( display designFlow5 solid solid silver silver ) - ( display designFlow6 solid solid tan tan ) - ( display designFlow7 solid solid cyan cyan ) - ( display designFlow8 solid solid navy navy ) - ( display designFlow9 solid solid orange orange ) - ( display changedLayerTl0 blank solid red red ) - ( display changedLayerTl1 blank solid yellow yellow ) - ( display markerWarn X solid yellow yellow ) - ( display markerErr X solid white white ) - ( display Row blank solid cyan cyan ) - ( display RowLbl blank solid cyan cyan ) - ( display Group dots solid green green ) - ( display GroupLbl blank solid green green ) - ( display Cannotoccupy X solid red red ) - ( display CannotoccupyBnd blank solid red red ) - ( display Canplace blank solid cyan cyan ) - ( display Unrouted blank dashed winColor5 winColor5 ) - ( display Unrouted1 blank dashed brown brown ) - ( display Unrouted2 blank dashed red red ) - ( display Unrouted3 blank dashed pink pink ) - ( display Unrouted4 blank dashed orange orange ) - ( display Unrouted5 blank dashed green green ) - ( display Unrouted6 blank dashed blue blue ) - ( display Unrouted7 blank dashed purple purple ) - ( display Unrouted8 blank dashed gold gold ) - ( display Unrouted9 blank dashed silver silver ) - -;---- cmosx below ------------------------------------------------------------------ - ( display NdiffResMask metal1S solid green green ) - ( display NLDD_Block dagger solid cream cream ) - ( display PLDD_Block dagger solid orange orange ) - ( display glass2 blank solid silver silver ) - ( display PdiffResMask metal1S solid brown brown ) - ( display NwellResMask metal1S solid lime lime ) - ( display PwellResMask metal1S solid orange orange ) - ( display celltag blank solid silver silver ) - ( display cellpwrtext blank solid yellow yellow ) - ( display celliotext blank solid yellow yellow ) - ( display cellnametext blank solid yellow yellow ) - ( display cellioterm blank solid yellow yellow ) - ( display cellbox blank solid yellow yellow ) - ( display PolyResMask metal1S solid red red ) - ( display M1ResMask metal1S solid blue blue ) - ( display M2ResMask metal1S solid magenta magenta ) - ( display polytext blank solid yellow yellow ) - ( display paatext blank solid yellow yellow ) - ( display naatext blank solid yellow yellow ) - ( display pwelltext blank solid yellow yellow ) - ( display nwelltext blank solid yellow yellow ) - ( display psubtext blank solid yellow yellow ) - ( display metal2text blank solid cyan cyan ) - ( display metal1text blank solid violet violet ) - ( display aaPin X solid volorange volorange ) - ( display nplus blank solid green green ) - ( display aa blank solid volorange volorange ) - ( display pplus blank solid brown brown ) - ( display aaNet blank solid volorange volorange ) - ( display contact X solid white white ) - ( display contactNet blank solid winColor5 winColor5 ) - ( display contactPin blank solid red red ) - ( display glasscut blank solid yellow yellow ) - ( display NdiffNet blank solid green green ) - ( display Ndiff dagger solid green green ) - ( display PdiffPin X solid brown brown ) - ( display NdiffPin X solid green green ) - ( display PdiffNet blank solid brown brown ) - ( display Pdiff dagger solid brown brown ) - ( display Met1TopTxt blank solid violet violet ) - ( display Met2TopTxt blank solid cyan cyan ) - ( display Met3TopTxt blank solid tan tan ) - ( display diodeMask blank solid yellow yellow ) - ( display TFDmask blank solid yellow yellow ) - ( display TABmask blank solid yellow yellow ) - ( display metal3text blank solid tan tan ) - ( display PolyNwellCap capID solid lime yellow ) - ( display PolyPwellCap capID solid brown yellow ) - ( display M1PolyCap capID solid blue yellow ) - ( display M2M1Cap capID solid magenta yellow ) - -) - - -; ---------------------------------------------------------------------------- -; ------ Display information for the display device 'psc' (Color PS). -------- -; ---------------------------------------------------------------------------- -drDefineColor( -;( DisplayName ColorName Red Green Blue Blink ) -;( ----------- --------- --- ----- ---- ----- ) - ( psc white 255 255 255 ) - ( psc silver 217 230 255 ) - ( psc cream 255 255 204 ) - ( psc pink 255 191 242 ) - ( psc magenta 255 0 255 ) - ( psc lime 0 255 0 ) - ( psc tan 255 230 191 ) - ( psc cyan 0 255 255 ) - ( psc cadetBlue 57 191 255 ) - ( psc yellow 255 255 0 ) - ( psc orange 255 128 0 ) - ( psc red 255 0 0 ) - ( psc purple 153 0 230 ) - ( psc green 0 204 102 ) - ( psc brown 191 64 38 ) - ( psc blue 0 0 255 ) - ( psc slate 140 140 166 ) - ( psc gold 217 204 0 ) - ( psc maroon 230 31 13 ) - ( psc violet 94 0 230 ) - ( psc forest 38 140 107 ) - ( psc chocolate 128 38 38 ) - ( psc navy 51 51 153 ) - ( psc black 0 0 0 ) - ( psc winBack 224 224 224 ) - ( psc winFore 128 0 0 ) - ( psc winText 51 51 51 ) - ( psc winColor1 166 166 166 ) - ( psc winColor2 115 115 115 ) - ( psc winColor3 189 204 204 ) - ( psc winColor4 204 204 204 ) - ( psc winColor5 199 199 199 ) - ( psc lightpink 255 196 209 ) -) - -drDefineStipple( -;( DisplayName StippleName Bitmap ) -;( ----------- ----------- ------ ) - - ( psc blank ( - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - 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(0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - ) ) - ( psc cwellBp ( - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - ) ) - ( psc capID ( - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0) - (0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0) - (0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - ) ) - ( psc resID ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 1 1 0 1 0 0 1 1 1 0 0 0 0 0 0 ) - ( 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) - ( psc diodeID ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 ) - ( 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 ) - ( 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) -) - -drDefineLineStyle( -;( DisplayName LineStyle Size Pattern ) -;( ----------- --------- ---- ------- ) - ( psc solid 1 (1 1 1) ) - ( psc dashed 1 (1 1 1 1 0 0) ) - ( psc dots 1 (1 0 0) ) - ( psc dashDot 1 (1 1 1 0 0 1 0 0) ) - ( psc shortDash 1 (1 1 0 0) ) - ( psc doubleDash 1 (1 1 1 1 0 0 1 1 0 0) ) - ( psc hidden 1 (1 0 0 0) ) - ( psc thickLine 3 (1 1 1) ) - ( psc mLine 2 (1 1 1) ) - ) - -drDefinePacket( -;( DisplayName PacketName Stipple LineStyle Fill Outline ) -;( ----------- ---------- ------- --------- ---- ------- ) - ( psc default blank solid green green ) - ( psc hdrcBnd blank solid white white ) - ( psc nwell slash solid green green ) - ( psc nwellNet blank solid green green ) - ( psc nwellPin X solid green green ) - ( psc pwell slash solid orange orange ) - ( psc pwellNet blank solid orange orange ) - ( psc pwellPin X solid orange orange ) - ( psc pbase checker2 solid orange orange ) - ( psc pbaseNet blank solid orange orange ) - ( psc pbasePin X solid orange orange ) - ( psc active invCross solid green green ) - ( psc activeNet blank solid green green ) - ( psc activePin X solid green green ) - ( psc nimplant blank solid green green ) - ( psc pimplant blank solid orange orange ) - ( psc polycap checker2 solid lightpink lightpink ) - ( psc polycapNet blank solid lightpink lightpink ) - ( psc polycapPin X solid lightpink lightpink ) - ( psc polycapLbl blank solid lightpink lightpink ) - ( psc polycapBnd blank solid lightpink lightpink ) - ( psc poly checker1 solid red red ) - ( psc polyNet blank solid red red ) - ( psc polyPin X solid red red ) - ( psc polyLbl blank solid red red ) - ( psc polyBnd blank solid red red ) - ( psc sblock brick solid blue blue ) - ( psc highres resID solid blue blue ) - ( psc elec checker2 solid yellow yellow ) - ( psc elecNet blank solid yellow yellow ) - ( psc elecPin X solid yellow yellow ) - ( psc elecLbl blank solid yellow yellow ) - ( psc metal1 backSlash solid blue blue ) - ( psc metal1Net blank solid blue blue ) - ( psc metal1Pin X solid blue blue ) - ( psc metal1Lbl blank solid blue blue ) - ( psc metal1Bnd blank solid blue blue ) - ( psc contact solid solid black lime ) - ( psc contactNet blank solid brown brown ) - ( psc contactPin X solid black black ) - ( psc contactLbl blank solid black black ) - ( psc contactBnd blank solid black black ) - ( psc metal2 dots solid magenta magenta ) - ( psc metal2Net blank solid magenta magenta ) - ( psc metal2Pin X solid magenta magenta ) - ( psc metal2Lbl blank solid magenta magenta ) - ( psc metal2Bnd blank solid magenta magenta ) - ( psc via1 viap solid purple black ) - ( psc via1Net blank solid purple black ) - ( psc via1Pin X solid purple black ) - ( psc via1Lbl blank solid purple black ) - ( psc viaBnd blank solid purple black ) - ( psc metal3 halfslash solid cyan cyan ) - ( psc metal3Net blank solid cyan cyan ) - ( psc metal3Pin X solid cyan cyan ) - ( psc metal3Lbl blank solid cyan cyan ) - ( psc metal3Bnd blank solid cyan cyan ) - ( psc via2 brick solid black black ) - ( psc via2Net blank solid black black ) - ( psc via2Pin X solid black black ) - ( psc via2Lbl blank solid black black ) - ( psc via2Bnd blank solid black black ) - ( psc metal4 dot4 solid cream cream ) - ( psc metal4Net blank solid cream cream ) - ( psc metal4Pin X solid cream cream ) - ( psc metal4Lbl blank solid cream cream ) - ( psc metal4Bnd blank solid cream cream ) - ( psc via3 invCross solid tan tan ) - ( psc via3Net blank solid tan tan ) - ( psc via3Pin X solid tan tan ) - ( psc via3Lbl blank solid tan tan ) - ( psc via3Bnd blank solid tan tan ) - ( psc metal5 metal2S solid cadetBlue cadetBlue ) - ( psc metal5Net blank solid cadetBlue cadetBlue ) - ( psc metal5Pin X solid cadetBlue cadetBlue ) - ( psc metal5Lbl blank solid cadetBlue cadetBlue ) - ( psc metal5Bnd blank solid cadetBlue cadetBlue ) - ( psc via4 invCross solid blue blue ) - ( psc via4Net blank solid blue blue ) - ( psc via4Pin X solid blue blue ) - ( psc via4Lbl blank solid blue blue ) - ( psc via4Bnd blank solid blue blue ) - ( psc metal6 miniHatch solid gold gold ) - ( psc metal6Net blank solid gold gold ) - ( psc metal6Pin X solid gold gold ) - ( psc metal6Lbl blank solid gold gold ) - ( psc metal6Bnd blank solid gold gold ) - ( psc via5 invCross solid yellow yellow ) - ( psc via5Net blank solid yellow yellow ) - ( psc via5Pin X solid yellow yellow ) - ( psc via5Lbl blank solid yellow yellow ) - ( psc via5Bnd blank solid yellow yellow ) - ( psc metal7 dots solid maroon maroon ) - ( psc metal7Net blank solid maroon maroon ) - ( psc metal7Pin X solid maroon maroon ) - ( psc metal7Lbl blank solid maroon maroon ) - ( psc metal7Bnd blank solid maroon maroon ) - ( psc via6 invCross solid magenta magenta ) - ( psc viaNet6 blank solid magenta magenta ) - ( psc viaPin6 X solid magenta magenta ) - ( psc viaLbl6 blank solid magenta magenta ) - ( psc viaBnd6 blank solid magenta magenta ) - ( psc metal8 halfslash solid cyan cyan ) - ( psc metal8Net blank solid cyan cyan ) - ( psc metal8Pin X solid cyan cyan ) - ( psc metal8Lbl blank solid cyan cyan ) - ( psc metal8Bnd blank solid cyan cyan ) - ( psc via7 invCross solid cadetBlue cadetBlue ) - ( psc via7Net blank solid cadetBlue cadetBlue ) - ( psc via7Pin X solid cadetBlue cadetBlue ) - ( psc via7Lbl blank solid cadetBlue cadetBlue ) - ( psc via7Bnd blank solid cadetBlue cadetBlue ) - ( psc metal9 dot4 solid cream cream ) - ( psc metal9Net blank solid cream cream ) - ( psc metal9Pin X solid cream cream ) - ( psc metal9Lbl blank solid cream cream ) - ( psc metal9Bnd blank solid cream cream ) - ( psc via8 invCross solid tan tan ) - ( psc via8Net blank solid tan tan ) - ( psc via8Pin X solid tan tan ) - ( psc via8Lbl blank solid tan tan ) - ( psc via8Bnd blank solid tan tan ) - ( psc metal10 metal2S solid cadetBlue cadetBlue ) - ( psc metal10Net blank solid cadetBlue cadetBlue ) - ( psc metal10Pin X solid cadetBlue cadetBlue ) - ( psc metal10Lbl blank solid cadetBlue cadetBlue ) - ( psc metal10Bnd blank solid cadetBlue cadetBlue ) - ( psc via9 invCross solid blue blue ) - ( psc via9Net blank solid blue blue ) - ( psc via9Pin X solid blue blue ) - ( psc via9Lbl blank solid blue blue ) - ( psc via9Bnd blank solid blue blue ) - ( psc metal11 miniHatch solid gold gold ) - ( psc metal11Net blank solid gold gold ) - ( psc metal11Pin X solid gold gold ) - ( psc metal11Lbl blank solid gold gold ) - ( psc metal11Bnd blank solid gold gold ) - ( psc glass vLine solid slate slate ) - ( psc open vCurb solid violet violet ) - ( psc openNet blank solid violet violet ) - ( psc openPin X solid violet violet ) - ( psc openLbl blank solid violet violet ) - ( psc openBnd blank solid violet violet ) - ( psc pstop dagger solid maroon maroon ) - ( psc pstopNet blank solid maroon maroon ) - ( psc pstopPin X solid maroon maroon ) - ( psc pstopLbl blank solid maroon maroon ) - ( psc pstopBnd blank solid maroon maroon ) - ( psc pad X doubleDash yellow yellow ) - ( psc nodrc X doubleDash cyan cyan ) - ( psc nolpe dot3 doubleDash tan tan ) - ( psc cap_id capID doubleDash slate slate ) - ( psc res_id resID doubleDash slate slate ) - ( psc dio_id diodeID doubleDash slate slate ) - ( psc metalcap miniHatch solid violet violet ) - ( psc metalcapBnd miniHatch solid violet violet ) - ( psc metalcapPin X solid violet violet ) - ( psc metalcapNet blank solid violet violet ) - ( psc metalcapLbl blank solid violet violet ) - ( psc background solid solid black black ) - ( psc grid blank solid slate slate ) - ( psc grid1 blank solid white white ) - ( psc axis blank solid white white ) - ( psc instance blank solid red red ) - ( psc instanceLbl blank solid gold gold ) - ( psc prBoundary blank solid purple purple ) - ( psc prBoundaryBnd blank solid cyan cyan ) - ( psc prBoundaryLbl blank solid purple purple ) - ( psc align blank solid tan tan ) - ( psc hardFence blank solid red red ) - ( psc softFence blank solid yellow yellow ) - ( psc text blank solid white white ) - ( psc text1 blank dashed white white ) - ( psc text2 solid solid white white ) - ( psc border blank solid tan tan ) - ( psc device blank solid green green ) - ( psc device2 blank dashed green green ) - ( psc device1 solid solid green green ) - ( psc wire solid solid cadetBlue cadetBlue ) - ( psc wireLbl solid solid cadetBlue cadetBlue ) - ( psc wireFlt blank dashed red red ) - ( psc deviceAnt blank solid yellow yellow ) - ( psc deviceLbl blank solid green green ) - ( psc pinLbl blank solid red red ) - ( psc pin solid solid red red ) - ( psc pinAnt blank solid red red ) - ( psc annotate blank solid orange orange ) - ( psc annotate1 blank solid pink pink ) - ( psc annotate2 blank solid lime lime ) - ( psc annotate3 blank solid cyan cyan ) - ( psc annotate4 blank solid yellow yellow ) - ( psc annotate5 blank solid white white ) - ( psc annotate6 blank solid silver silver ) - ( psc annotate7 blank solid red red ) - ( psc annotate8 blank solid tan tan ) - ( psc annotate9 blank solid green green ) - ( psc edgeLayer blank solid winColor5 winColor5 ) - ( psc edgeLayerPin blank solid yellow yellow ) - ( psc snap blank solid yellow yellow ) - ( psc stretch blank solid yellow yellow ) - ( psc y0 blank dashed winColor5 winColor5 ) - ( psc y1 blank dashed brown brown ) - ( psc y2 blank dashed red red ) - ( psc y3 blank dashed pink pink ) - ( psc y4 blank dashed orange orange ) - ( psc y5 blank dashed green green ) - ( psc y6 blank dashed blue blue ) - ( psc y7 blank dashed purple purple ) - ( psc y8 blank dashed gold gold ) - ( psc y9 blank dashed silver silver ) - ( psc hilite blank solid white white ) - ( psc hilite1 blank solid yellow yellow ) - ( psc hilite2 blank solid tan tan ) - ( psc hilite3 blank solid cyan cyan ) - ( psc hilite4 blank solid orange orange ) - ( psc hilite5 blank solid lime lime ) - ( psc hilite6 blank solid orange orange ) - ( psc hilite7 blank solid cream cream ) - ( psc hilite8 blank solid magenta magenta ) - ( psc hilite9 blank solid pink pink ) - ( psc select blank solid orange orange ) - ( psc drive blank solid blue blue ) - ( psc hiz blank solid orange orange ) - ( psc resist blank solid cyan cyan ) - ( psc spike blank solid purple purple ) - ( psc supply blank solid lime lime ) - ( psc unknown blank solid yellow yellow ) - ( psc unset blank solid forest forest ) - ( psc designFlow solid solid green green ) - ( psc designFlow1 solid solid red red ) - ( psc designFlow2 solid solid purple purple ) - ( psc designFlow3 solid solid pink pink ) - ( psc designFlow4 solid solid black black ) - ( psc designFlow5 solid solid silver silver ) - ( psc designFlow6 solid solid tan tan ) - ( psc designFlow7 solid solid cyan cyan ) - ( psc designFlow8 solid solid navy navy ) - ( psc designFlow9 solid solid orange orange ) - ( psc changedLayerTl0 blank solid red red ) - ( psc changedLayerTl1 blank solid yellow yellow ) - ( psc markerWarn X solid yellow yellow ) - ( psc markerErr X solid white white ) - ( psc Row blank solid cyan cyan ) - ( psc RowLbl blank solid cyan cyan ) - ( psc Group dots solid green green ) - ( psc GroupLbl blank solid green green ) - ( psc Cannotoccupy X solid red red ) - ( psc CannotoccupyBnd blank solid red red ) - ( psc Canplace blank solid cyan cyan ) - ( psc Unrouted blank dashed winColor5 winColor5 ) - ( psc Unrouted1 blank dashed brown brown ) - ( psc Unrouted2 blank dashed red red ) - ( psc Unrouted3 blank dashed pink pink ) - ( psc Unrouted4 blank dashed orange orange ) - ( psc Unrouted5 blank dashed green green ) - ( psc Unrouted6 blank dashed blue blue ) - ( psc Unrouted7 blank dashed purple purple ) - ( psc Unrouted8 blank dashed gold gold ) - ( psc Unrouted9 blank dashed silver silver ) -) - - -; ------------------------------------------------------------------------ -; ------ Display information for the display device 'psb' (B+W PS). ------ -; ------------------------------------------------------------------------ - -drDefineColor( -;( DisplayName ColorName Red Green Blue Blink ) -;( ----------- --------- --- ----- ---- ----- ) - ( psb white 255 255 255 ) - ( psb 1 0 0 0 ) -) - -drDefineStipple( -;( DisplayName StippleName Bitmap ) -;( ----------- ----------- ------ ) - - ( psb blank ( - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - ) ) - ( psb solid ( - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - ) ) - ( psb dots ( - (1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - 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( psb dot1 ( - (1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - ) ) - ( psb dot2 ( - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0) - (0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0) - (0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - ) ) - ( psb dot3 ( - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - ) ) - ( psb checker ( - (1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0) - (1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0) - (1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0) - (1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0) - (0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1) - (0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1) - (0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1) - (0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1) - (1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0) - (1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0) - (1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0) - (1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0) - (0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1) - (0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1) - (0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1) - (0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1) - ) ) - ( psb checker2 ( - (1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0) - (1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0) - (0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1) - (0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1) - (1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0) - (1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0) - (0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1) - (0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1) - (1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0) - (1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0) - (0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1) - (0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1) - (1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0) - (1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0) - (0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1) - (0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1) - ) ) - ( psb sgrid ( - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - (1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1) - (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) - ) ) - ( psb metal1S ( - (1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1) - ) ) - ( psb metal2S ( - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0) - (0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0) - (0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - ) ) - ( psb gnd2S ( - (1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1) - (1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0) - (1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0) - (0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0) - (0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0) - (0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0) - (0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0) - (0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0) - (1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1) - (1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0) - (1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0) - (0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0) - (0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0) - (0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0) - (0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0) - (0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0) - ) ) - ( psb vcc2S ( - (0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0) - (0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0) - (0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0) - (0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0) - (1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0) - (0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0) - (0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0) - (0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0) - (0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0) - (0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0) - (0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0) - (1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1) - (1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0) - (0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0) - (0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0) - ) ) - ( psb vcc1S ( - (1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0) - (0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0) - (0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0) - (0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0) - (1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1) - (1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0) - (0 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0) - (0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1) - (1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0) - (0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0) - (0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0) - (0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0) - (1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1) - (1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0) - (0 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0) - (0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1) - ) ) - ( psb capID ( - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0) - (0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0) - (0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) - ) ) - ( psb resID ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ) - ( 1 1 1 0 1 0 0 1 1 1 0 0 0 0 0 0 ) - ( 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) - ( psb diodeID ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 ) - ( 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 ) - ( 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) - ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) ) -) - -drDefineLineStyle( -;( DisplayName LineStyle Size Pattern ) -;( ----------- --------- ---- ------- ) - ( psb solid 1 (1 1 1) ) - ( psb dashed 1 (1 1 1 1 0 0 0 0) ) - ( psb dots 1 (1 0 0 0 0) ) - ( psb dashDot 1 (1 1 1 1 0 0 0 0 1 0 0 0 0) ) - ( psb shortDash 1 (1 1 0 0) ) - ( psb doubleDash 1 (1 1 1 1 0 0 0 0 1 1 0 0) ) - ( psb hidden 1 (1 0 0 0 0 0 0 0 0) ) - ( psb thickLine 3 (1 1 1) ) - ) - -drDefinePacket( -;( DisplayName PacketName Stipple LineStyle Fill Outline ) -;( ----------- ---------- ------- --------- ---- ------- ) - ( psb default blank solid 1 1 ) - ( psb nwell blank solid 1 1 ) - ( psb nwellNet blank solid 1 1 ) - ( psb nwellPin X solid 1 1 ) - ( psb pwell dot1 solid 1 1 ) - ( psb pwellNet blank solid 1 1 ) - ( psb pwellPin X solid 1 1 ) - ( psb pbase blank solid 1 1 ) - ( psb pbaseNet blank solid 1 1 ) - ( psb pbasePin X solid 1 1 ) - ( psb active dot3 solid 1 1 ) - ( psb activeNet blank solid 1 1 ) - ( psb activePin X solid 1 1 ) - ( psb nimplant blank solid 1 1 ) - ( psb pimplant blank doubleDash 1 1 ) - ( psb polycap checker2 solid 1 1 ) - ( psb polycapNet blank solid 1 1 ) - ( psb polycapPin X solid 1 1 ) - ( psb polycapLbl blank solid 1 1 ) - ( psb polycapBnd blank solid 1 1 ) - ( psb poly checker solid 1 1 ) - ( psb polyNet blank solid 1 1 ) - ( psb polyPin X solid 1 1 ) - ( psb polyLbl blank solid 1 1 ) - ( psb polyBnd blank solid 1 1 ) - ( psb sblock vCurb solid 1 1 ) - ( psb highres vCurb solid 1 1 ) - ( psb elec dagger solid 1 1 ) - ( psb elecNet blank solid 1 1 ) - ( psb elecPin X solid 1 1 ) - ( psb elecLbl blank solid 1 1 ) - ( psb metal1 metal1S thickLine 1 1 ) - ( psb metal1Net blank solid 1 1 ) - ( psb metal1Pin X solid 1 1 ) - ( psb metal1Lbl blank solid 1 1 ) - ( psb metal1Bnd blank solid 1 1 ) - ( psb contact solid solid 1 1 ) - ( psb contactNet blank solid 1 1 ) - ( psb contactPin X solid 1 1 ) - ( psb contactLbl blank solid 1 1 ) - ( psb contactBnd blank solid 1 1 ) - ( psb metal2 metal2S thickLine 1 1 ) - ( psb metal2Net blank solid 1 1 ) - ( psb metal2Pin X solid 1 1 ) - ( psb metal2Lbl blank solid 1 1 ) - ( psb metal2Bnd blank solid 1 1 ) - ( psb metal3 halfslash thickLine 1 1 ) - ( psb metal3Net blank solid 1 1 ) - ( psb metal3Pin X solid 1 1 ) - ( psb metal3Lbl blank solid 1 1 ) - ( psb metal3Bnd blank solid 1 1 ) - ( psb via2 dot1 thickLine 1 1 ) - ( psb via2Net blank solid 1 1 ) - ( psb via2Pin X solid 1 1 ) - ( psb via2Lbl blank solid 1 1 ) - ( psb via2Bnd blank solid 1 1 ) - ( psb metal4 hCurb thickLine 1 1 ) - ( psb metal4Net blank solid 1 1 ) - ( psb metal4Pin X solid 1 1 ) - ( psb metal4Lbl blank solid 1 1 ) - ( psb metal4Bnd blank solid 1 1 ) - ( psb via3 triangle thickLine 1 1 ) - ( psb via3Net blank solid 1 1 ) - ( psb via3Pin X solid 1 1 ) - ( psb via3Lbl blank solid 1 1 ) - ( psb via3Bnd blank solid 1 1 ) - ( psb metal5 hLine2 thickLine 1 1 ) - ( psb metal5Net blank solid 1 1 ) - ( psb metal5Pin X solid 1 1 ) - ( psb metal5Lbl blank solid 1 1 ) - ( psb metal5Bnd blank solid 1 1 ) - ( psb via4 dagger thickLine 1 1 ) - ( psb via4Net blank solid 1 1 ) - ( psb via4Pin X solid 1 1 ) - ( psb via4Lbl blank solid 1 1 ) - ( psb via4Bnd blank solid 1 1 ) - ( psb metal6 miniHatch solid 1 1 ) - ( psb metal6Net blank solid 1 1 ) - ( psb metal6Pin X solid 1 1 ) - ( psb metal6Lbl blank solid 1 1 ) - ( psb metal6Bnd blank solid 1 1 ) - ( psb via5 dot2 solid 1 1 ) - ( psb via5Net blank solid 1 1 ) - ( psb via5Pin X solid 1 1 ) - ( psb via5Lbl blank solid 1 1 ) - ( psb via5Bnd blank solid 1 1 ) - ( psb metal7 dots solid 1 1 ) - ( psb metal7Net blank solid 1 1 ) - ( psb metal7Pin X solid 1 1 ) - ( psb metal7Lbl blank solid 1 1 ) - ( psb metal7Bnd blank solid 1 1 ) - ( psb via6 dot2 solid 1 1 ) - ( psb viaNet6 blank solid 1 1 ) - ( psb viaPin6 X solid 1 1 ) - ( psb viaLbl6 blank solid 1 1 ) - ( psb viaBnd6 blank solid 1 1 ) - ( psb metal8 halfslash solid 1 1 ) - ( psb metal8Net blank solid 1 1 ) - ( psb metal8Pin X solid 1 1 ) - ( psb metal8Lbl blank solid 1 1 ) - ( psb metal8Bnd blank solid 1 1 ) - ( psb via7 dot2 solid 1 1 ) - ( psb via7Net blank solid 1 1 ) - ( psb via7Pin X solid 1 1 ) - ( psb via7Lbl blank solid 1 1 ) - ( psb via7Bnd blank solid 1 1 ) - ( psb metal9 dot2 solid 1 1 ) - ( psb metal9Net blank solid 1 1 ) - ( psb metal9Pin X solid 1 1 ) - ( psb metal9Lbl blank solid 1 1 ) - ( psb metal9Bnd blank solid 1 1 ) - ( psb via8 dot2 solid 1 1 ) - ( psb via8Net blank solid 1 1 ) - ( psb via8Pin X solid 1 1 ) - ( psb via8Lbl blank solid 1 1 ) - ( psb via8Bnd blank solid 1 1 ) - ( psb metal10 metal2S solid 1 1 ) - ( psb metal10Net blank solid 1 1 ) - ( psb metal10Pin X solid 1 1 ) - ( psb metal10Lbl blank solid 1 1 ) - ( psb metal10Bnd blank solid 1 1 ) - ( psb via9 dot2 solid 1 1 ) - ( psb via9Net blank solid 1 1 ) - ( psb via9Pin X solid 1 1 ) - ( psb via9Lbl blank solid 1 1 ) - ( psb via9Bnd blank solid 1 1 ) - ( psb metal11 miniHatch solid 1 1 ) - ( psb metal11Net blank solid 1 1 ) - ( psb metal11Pin X solid 1 1 ) - ( psb metal11Lbl blank solid 1 1 ) - ( psb metal11Bnd blank solid 1 1 ) - - - - - ( psb glass blank solid 1 1 ) - ( psb open vCurb solid 1 1 ) - ( psb openNet blank solid 1 1 ) - ( psb openPin blank solid 1 1 ) - ( psb openLbl blank solid 1 1 ) - ( psb openBnd blank solid 1 1 ) - ( psb pstop dagger solid 1 1 ) - ( psb pstopNet blank solid 1 1 ) - ( psb pstopPin X solid 1 1 ) - ( psb pstopLbl blank solid 1 1 ) - ( psb pstopBnd blank solid 1 1 ) - ( psb pad X doubleDash 1 1 ) - ( psb nodrc X doubleDash 1 1 ) - ( psb cap_id capID doubleDash 1 1 ) - ( psb res_id resID doubleDash 1 1 ) - ( psb dio_id diodeID doubleDash 1 1 ) - ( psb metalcap miniHatch solid 1 1 ) - ( psb metalcapBnd miniHatch solid 1 1 ) - ( psb metalcapPin X solid 1 1 ) - ( psb metalcapNet blank solid 1 1 ) - ( psb metalcapLbl blank solid 1 1 ) - ( psb background solid solid 1 1 ) - ( psb grid blank solid 1 1 ) - ( psb grid1 blank solid 1 1 ) - ( psb axis blank solid 1 1 ) - ( psb instance blank solid 1 1 ) - ( psb instanceLbl blank solid 1 1 ) - ( psb prBoundary blank solid 1 1 ) - ( psb prBoundaryBnd blank solid 1 1 ) - ( psb align blank solid 1 1 ) - ( psb text blank solid 1 1 ) - ( psb text1 blank solid 1 1 ) - ( psb text2 solid solid 1 1 ) - ( psb border solid solid 1 1 ) - ( psb device blank solid 1 1 ) - ( psb device1 blank solid 1 1 ) - ( psb wire solid solid 1 1 ) - ( psb wireLbl solid solid 1 1 ) - ( psb wireFlt blank solid 1 1 ) - ( psb deviceAnt blank solid 1 1 ) - ( psb deviceLbl blank solid 1 1 ) - ( psb pinLbl blank solid 1 1 ) - ( psb pin solid solid 1 1 ) - ( psb pinAnt blank solid 1 1 ) - ( psb annotate blank solid 1 1 ) - ( psb annotate1 blank solid 1 1 ) - ( psb annotate2 blank solid 1 1 ) - ( psb annotate3 blank solid 1 1 ) - ( psb annotate4 blank solid 1 1 ) - ( psb annotate5 blank solid 1 1 ) - ( psb annotate6 blank solid 1 1 ) - ( psb annotate7 blank solid 1 1 ) - ( psb annotate8 blank solid 1 1 ) - ( psb annotate9 blank solid 1 1 ) - ( psb edgeLayer blank solid 1 1 ) - ( psb edgeLayerPin blank solid 1 1 ) - ( psb snap blank solid 1 1 ) - ( psb stretch blank solid 1 1 ) - ( psb y0 blank solid 1 1 ) - ( psb y1 blank dashed 1 1 ) - ( psb y2 blank dots 1 1 ) - ( psb y3 blank dashDot 1 1 ) - ( psb y4 blank shortDash 1 1 ) - ( psb y5 blank doubleDash 1 1 ) - ( psb y6 blank hidden 1 1 ) - ( psb y7 blank thickLine 1 1 ) - ( psb y8 blank solid 1 1 ) - ( psb y9 hLine dashed 1 1 ) - ( psb hilite blank solid 1 1 ) - ( psb hilite1 blank solid 1 1 ) - ( psb hilite2 blank solid 1 1 ) - ( psb hilite3 blank solid 1 1 ) - ( psb hilite4 blank solid 1 1 ) - ( psb hilite5 blank solid 1 1 ) - ( psb hilite6 blank solid 1 1 ) - ( psb hilite7 blank solid 1 1 ) - ( psb hilite8 blank solid 1 1 ) - ( psb hilite9 blank solid 1 1 ) - ( psb select blank solid 1 1 ) - ( psb drive blank solid 1 1 ) - ( psb hiz blank solid 1 1 ) - ( psb resist blank solid 1 1 ) - ( psb spike blank solid 1 1 ) - ( psb supply blank solid 1 1 ) - ( psb designFlow solid solid 1 1 ) - ( psb designFlow1 blank solid 1 1 ) - ( psb designFlow2 blank solid 1 1 ) - ( psb designFlow3 blank solid 1 1 ) - ( psb designFlow4 blank solid 1 1 ) - ( psb designFlow5 blank solid 1 1 ) - ( psb designFlow6 blank solid 1 1 ) - ( psb designFlow7 blank solid 1 1 ) - ( psb designFlow8 blank solid 1 1 ) - ( psb designFlow9 blank solid 1 1 ) - ( psb changedLayerTl0 blank solid 1 1 ) - ( psb changedLayerTl1 blank solid 1 1 ) - ( psb markerWarn X solid 1 1 ) - ( psb markerErr X solid 1 1 ) -) - -; vim:ts=4:columns=132: diff --git a/crlcore/src/ccore/openaccess/testDriver/src/CMakeLists.txt b/crlcore/src/ccore/openaccess/testDriver/src/CMakeLists.txt deleted file mode 100755 index 4c53d292..00000000 --- a/crlcore/src/ccore/openaccess/testDriver/src/CMakeLists.txt +++ /dev/null @@ -1,26 +0,0 @@ - -INCLUDE(${QT_USE_FILE}) - -INCLUDE_DIRECTORIES ( ${HURRICANE_INCLUDE_DIR} - ${CORIOLIS_INCLUDE_DIR} - ${HURRICANEAMS_INCLUDE_DIR} - ${HURRICANEAMS_GRAPHICAL_INCLUDE_DIR} - ${AMSCORE_INCLUDE_DIR} - ${SCHEMATIC_SOURCE_DIR}/src - ) - -SET ( CPPS main.cpp ) - -SET(EXECUTABLE_OUTPUT_PATH ${CMAKE_BINARY_DIR}/bin) -ADD_EXECUTABLE(testOAWrapper ${QRCS_SRCS} ${MOCS} ${CPPS} ${QRCS}) -TARGET_LINK_LIBRARIES(testOAWrapper ${HURRICANE_LIBRARIES} - ${HURRICANE_PYTHON_LIBRARIES} - ${OPENCHAMS_LIBRARY} - ${CIF_LIBRARY} - ${AGDS_LIBRARY} - ${CORIOLIS_LIBRARIES} - ${HURRICANEAMS_LIBRARIES} - ${AMSCORE_LIBRARIES} - ${OA_LIBRARIES} ) -INSTALL(TARGETS testOAWrapper DESTINATION bin) - diff --git a/crlcore/src/ccore/openaccess/testDriver/src/main.cpp b/crlcore/src/ccore/openaccess/testDriver/src/main.cpp deleted file mode 100755 index fa4cd970..00000000 --- a/crlcore/src/ccore/openaccess/testDriver/src/main.cpp +++ /dev/null @@ -1,206 +0,0 @@ -// -*-compile-command:"cd .. && make"-*- -// x-----------------------------------------------------------------x -// | This file is part of | -// | Copyright (c) UPMC/LIP6 2008-2009, All Rights Reserved | -// | =============================================================== | -// | Author : Jean-Manuel Caba | -// | E-mail : Jean-Manuel.Caba@asim.lip6.fr | -// x-----------------------------------------------------------------x - -#include -#include -#include - -using namespace std; - -#include "hurricane/Cell.h" -#include "hurricane/Library.h" -#include "hurricane/DataBase.h" - -using namespace Hurricane; - -#include "crlcore/Catalog.h" -#include "crlcore/RealTechnologyParser.h" -#include "crlcore/SymbolicTechnologyParser.h" -#include "crlcore/AllianceFramework.h" - -#include "hurricaneAMS/environment/AnalogEnv.h" -#include "hurricaneAMS/devices/SimpleCurrentMirror.h" - -#include "crlcore/GdsDriver.h" -#include "crlcore/CifDriver.h" -#include "crlcore/OADriver.h" -using namespace CRL; - -namespace { - static string designName = "design"; - static string libName = "WorkLibrary"; -}; - -void testCell(Cell* dev,char* pathToTest){ - if(dev){ - cerr << "Cell created" << endl; - }else{ - cerr << "Cell not created" << endl; - return; - } - - cerr << "driving GDS" << endl; - GdsDriver(dev).save(string(pathToTest) + "/" + getString(dev->getName()) + ".gds"); - - cerr << "driving CIF" << endl; - CifDriver(dev).save(string(pathToTest) + "/" + getString(dev->getName()) + ".cif"); - - cerr << "driving OA" << endl; - OADriver(dev).save(string(pathToTest) + "/OAdrive"); -} - -void testAnalog(char* pathToConf,char* pathToTest){ - auto_ptr aenv(AnalogEnv::create(pathToConf));//create Database ... - cerr << "analog environment loaded and database created" << endl; - DataBase* db = DataBase::getDB(); - assert(db != NULL); - Library* rootLib = db->getRootLibrary(); - if(!rootLib){ - Library::create(db, "RootLibrary"); - rootLib = db->getRootLibrary(); - } - assert(rootLib != NULL); - - Library* workLibrary = rootLib->getLibrary(libName); - if(!workLibrary) - workLibrary = Library::create(rootLib, libName); - assert(workLibrary != NULL); - - Cell* design = workLibrary->getCell(designName); - if(!design) - design = Cell::create(workLibrary, designName); - assert(design != NULL); - - cerr << "creating cell myCM" << endl; - - bool bulkConnected = true;//bulk connected to source - Cell* dev = SimpleCurrentMirror::create(workLibrary, Name("myCM"), - TransistorFamily::NMOS, - bulkConnected); - - cerr << "testing cell myCM" << endl; - testCell(dev,pathToTest); - db->destroy(); -} - -void testNum(char* pathToConf,char* pathToTest,char* cellName){ - cerr << "creating cell from sxlib " << cellName << endl; - DataBase* db = DataBase::getDB(); - AllianceFramework* af =AllianceFramework::get(); - Cell* cell = af->getCell(cellName, Catalog::State::Views ); - cerr << "testing cell from sxlib "<< cellName << endl; - testCell(cell,pathToTest); -} - -int main(int argc,char** argv) { - if(argc != 3) - exit(-5); - - testAnalog(argv[1],argv[2]); - - testNum(argv[1],argv[2],"a2_x2"); - testNum(argv[1],argv[2],"a2_x4"); - testNum(argv[1],argv[2],"a3_x2"); - testNum(argv[1],argv[2],"a3_x4"); - testNum(argv[1],argv[2],"a4_x2"); - testNum(argv[1],argv[2],"a4_x4"); - testNum(argv[1],argv[2],"an12_x1"); - testNum(argv[1],argv[2],"an12_x4"); - testNum(argv[1],argv[2],"ao22_x2"); - testNum(argv[1],argv[2],"ao22_x4"); - testNum(argv[1],argv[2],"ao2o22_x2"); - testNum(argv[1],argv[2],"ao2o22_x4"); - testNum(argv[1],argv[2],"buf_x2"); - testNum(argv[1],argv[2],"buf_x4"); - testNum(argv[1],argv[2],"buf_x8"); - testNum(argv[1],argv[2],"fulladder_x2"); - testNum(argv[1],argv[2],"fulladder_x4"); - testNum(argv[1],argv[2],"halfadder_x2"); - testNum(argv[1],argv[2],"halfadder_x4"); - testNum(argv[1],argv[2],"inv_x1"); - testNum(argv[1],argv[2],"inv_x2"); - testNum(argv[1],argv[2],"inv_x4"); - testNum(argv[1],argv[2],"inv_x8"); - testNum(argv[1],argv[2],"mx2_x2"); - testNum(argv[1],argv[2],"mx2_x4"); - testNum(argv[1],argv[2],"mx3_x2"); - testNum(argv[1],argv[2],"mx3_x4"); - testNum(argv[1],argv[2],"na2_x1"); - testNum(argv[1],argv[2],"na2_x4"); - testNum(argv[1],argv[2],"na3_x1"); - testNum(argv[1],argv[2],"na3_x4"); - testNum(argv[1],argv[2],"na4_x1"); - testNum(argv[1],argv[2],"na4_x4"); - testNum(argv[1],argv[2],"nao22_x1"); - testNum(argv[1],argv[2],"nao22_x4"); - testNum(argv[1],argv[2],"nao2o22_x1"); - testNum(argv[1],argv[2],"nao2o22_x4"); - testNum(argv[1],argv[2],"nmx2_x1"); - testNum(argv[1],argv[2],"nmx2_x4"); - testNum(argv[1],argv[2],"nmx3_x1"); - testNum(argv[1],argv[2],"nmx3_x4"); - testNum(argv[1],argv[2],"no2_x1"); - testNum(argv[1],argv[2],"no2_x4"); - testNum(argv[1],argv[2],"no3_x1"); - testNum(argv[1],argv[2],"no3_x4"); - testNum(argv[1],argv[2],"no4_x1"); - testNum(argv[1],argv[2],"no4_x4"); - testNum(argv[1],argv[2],"noa22_x1"); - testNum(argv[1],argv[2],"noa22_x4"); - testNum(argv[1],argv[2],"noa2a22_x1"); - testNum(argv[1],argv[2],"noa2a22_x4"); - testNum(argv[1],argv[2],"noa2a2a23_x1"); - testNum(argv[1],argv[2],"noa2a2a23_x4"); - testNum(argv[1],argv[2],"noa2a2a2a24_x1"); - testNum(argv[1],argv[2],"noa2a2a2a24_x4"); - testNum(argv[1],argv[2],"noa2ao222_x1"); - testNum(argv[1],argv[2],"noa2ao222_x4"); - testNum(argv[1],argv[2],"noa3ao322_x1"); - testNum(argv[1],argv[2],"noa3ao322_x4"); - testNum(argv[1],argv[2],"nts_x1"); - testNum(argv[1],argv[2],"nts_x2"); - testNum(argv[1],argv[2],"nxr2_x1"); - testNum(argv[1],argv[2],"nxr2_x4"); - testNum(argv[1],argv[2],"o2_x2"); - testNum(argv[1],argv[2],"o2_x4"); - testNum(argv[1],argv[2],"o3_x2"); - testNum(argv[1],argv[2],"o3_x4"); - testNum(argv[1],argv[2],"o4_x2"); - testNum(argv[1],argv[2],"o4_x4"); - testNum(argv[1],argv[2],"oa22_x2"); - testNum(argv[1],argv[2],"oa22_x4"); - testNum(argv[1],argv[2],"oa2a22_x2"); - testNum(argv[1],argv[2],"oa2a22_x4"); - testNum(argv[1],argv[2],"oa2a2a23_x2"); - testNum(argv[1],argv[2],"oa2a2a23_x4"); - testNum(argv[1],argv[2],"oa2a2a2a24_x2"); - testNum(argv[1],argv[2],"oa2a2a2a24_x4"); - testNum(argv[1],argv[2],"oa2ao222_x2"); - testNum(argv[1],argv[2],"oa2ao222_x4"); - testNum(argv[1],argv[2],"oa3ao322_x2"); - testNum(argv[1],argv[2],"oa3ao322_x4"); - testNum(argv[1],argv[2],"on12_x1"); - testNum(argv[1],argv[2],"on12_x4"); - testNum(argv[1],argv[2],"one_x0"); - testNum(argv[1],argv[2],"powmid_x0"); - testNum(argv[1],argv[2],"rowend_x0"); - testNum(argv[1],argv[2],"sff1_x4"); - testNum(argv[1],argv[2],"sff2_x4"); - testNum(argv[1],argv[2],"sff3_x4"); - testNum(argv[1],argv[2],"tie_x0"); - testNum(argv[1],argv[2],"ts_x4"); - testNum(argv[1],argv[2],"ts_x8"); - testNum(argv[1],argv[2],"xr2_x1"); - testNum(argv[1],argv[2],"xr2_x4"); - testNum(argv[1],argv[2],"zero_x0"); - - DataBase::getDB()->destroy(); - cerr << "ending normally" << endl; - return 0; -} diff --git a/crlcore/src/ccore/openaccess/testDriver/sxlib2lef/Makefile b/crlcore/src/ccore/openaccess/testDriver/sxlib2lef/Makefile deleted file mode 100644 index 07c97029..00000000 --- a/crlcore/src/ccore/openaccess/testDriver/sxlib2lef/Makefile +++ /dev/null @@ -1,17 +0,0 @@ - -all: sxlib.lef - lef2oa -lib sxlib -lef sxlib.lef - oa2lef -lib sxlib -lef sxlib_back.lef - -sxlib.lef: - grep -v "END LIBRARY" cmos.lef.bak > sxlib.lef ; for i in $$(cat cells) ; do sxlib2lef $$i ; cat $$i.lef >> sxlib.lef ; done - echo "END LIBRARY" >> sxlib.lef - cp sxlib.lef sxlib.lef.bak - -mrproper: clean - rm -rf sxlib cds.lib .cadence .oalib - -clean: - rm -rf *.log *.slog *~ encounter* *.lef - -.PHONY: all mrproper clean diff --git a/crlcore/src/ccore/openaccess/testDriver/sxlib2lef/cells b/crlcore/src/ccore/openaccess/testDriver/sxlib2lef/cells deleted file mode 100644 index c5616138..00000000 --- a/crlcore/src/ccore/openaccess/testDriver/sxlib2lef/cells +++ /dev/null @@ -1,95 +0,0 @@ -a2_x2 -a2_x4 -a3_x2 -a3_x4 -a4_x2 -a4_x4 -an12_x1 -an12_x4 -ao22_x2 -ao22_x4 -ao2o22_x2 -ao2o22_x4 -buf_x2 -buf_x4 -buf_x8 -fulladder_x2 -fulladder_x4 -halfadder_x2 -halfadder_x4 -inv_x1 -inv_x2 -inv_x4 -inv_x8 -mx2_x2 -mx2_x4 -mx3_x2 -mx3_x4 -na2_x1 -na2_x4 -na3_x1 -na3_x4 -na4_x1 -na4_x4 -nao22_x1 -nao22_x4 -nao2o22_x1 -nao2o22_x4 -nmx2_x1 -nmx2_x4 -nmx3_x1 -nmx3_x4 -no2_x1 -no2_x4 -no3_x1 -no3_x4 -no4_x1 -no4_x4 -noa22_x1 -noa22_x4 -noa2a22_x1 -noa2a22_x4 -noa2a2a23_x1 -noa2a2a23_x4 -noa2a2a2a24_x1 -noa2a2a2a24_x4 -noa2ao222_x1 -noa2ao222_x4 -noa3ao322_x1 -noa3ao322_x4 -nts_x1 -nts_x2 -nxr2_x1 -nxr2_x4 -o2_x2 -o2_x4 -o3_x2 -o3_x4 -o4_x2 -o4_x4 -oa22_x2 -oa22_x4 -oa2a22_x2 -oa2a22_x4 -oa2a2a23_x2 -oa2a2a23_x4 -oa2a2a2a24_x2 -oa2a2a2a24_x4 -oa2ao222_x2 -oa2ao222_x4 -oa3ao322_x2 -oa3ao322_x4 -on12_x1 -on12_x4 -one_x0 -powmid_x0 -rowend_x0 -sff1_x4 -sff2_x4 -sff3_x4 -tie_x0 -ts_x4 -ts_x8 -xr2_x1 -xr2_x4 -zero_x0 diff --git a/crlcore/src/ccore/openaccess/testDriver/sxlib2lef/cmos.lef.bak b/crlcore/src/ccore/openaccess/testDriver/sxlib2lef/cmos.lef.bak deleted file mode 100644 index f9b7fa1c..00000000 --- a/crlcore/src/ccore/openaccess/testDriver/sxlib2lef/cmos.lef.bak +++ /dev/null @@ -1,435 +0,0 @@ -# -# $Id: cmos.lef,v 1.6 2005/03/01 14:59:15 jpc Exp $ -# -# /------------------------------------------------------------------\ -# | | -# | A l l i a n c e C A D S y s t e m | -# | S i l i c o n E n s e m b l e / A l l i a n c e | -# | | -# | Author : Jean-Paul CHAPUT | -# | E-mail : alliance-users@asim.lip6.fr | -# | ================================================================ | -# | LEF : "./cmos_12.lef" | -# | **************************************************************** | -# | U p d a t e s | -# | | -# \------------------------------------------------------------------/ -# - - -VERSION 5.2 ; -NAMESCASESENSITIVE ON ; -BUSBITCHARS "()" ; -DIVIDERCHAR "." ; - -#NOWIREEXTENSIONATPIN ON ; - - -#UNITS -# DATABASE MICRONS 100 ; -#END UNITS - - -LAYER POLY - TYPE MASTERSLICE ; -END POLY - - -LAYER VIAP - TYPE CUT ; -END VIAP - - -LAYER ALU1 - TYPE ROUTING ; - WIDTH 2.00 ; - SPACING 3.00 ; - PITCH 5.00 ; - DIRECTION VERTICAL ; - CAPACITANCE CPERSQDIST 0.000032 ; - RESISTANCE RPERSQ 0.100000 ; -END ALU1 - - -LAYER VIA1 - TYPE CUT ; -END VIA1 - - -LAYER ALU2 - TYPE ROUTING ; - WIDTH 2.00 ; - SPACING 3.00 ; - PITCH 5.00 ; - DIRECTION HORIZONTAL ; - CAPACITANCE CPERSQDIST 0.000032 ; - RESISTANCE RPERSQ 0.100000 ; -END ALU2 - - -LAYER VIA2 - TYPE CUT ; -END VIA2 - - -LAYER ALU3 - TYPE ROUTING ; - WIDTH 2.00 ; - SPACING 3.00 ; - PITCH 5.00 ; - DIRECTION VERTICAL ; - CAPACITANCE CPERSQDIST 0.000032 ; - RESISTANCE RPERSQ 0.100000 ; -END ALU3 - - -LAYER VIA3 - TYPE CUT ; -END VIA3 - - -LAYER ALU4 - TYPE ROUTING ; - WIDTH 2.00 ; - SPACING 3.00 ; - PITCH 5.00 ; - DIRECTION HORIZONTAL ; - CAPACITANCE CPERSQDIST 0.000032 ; - RESISTANCE RPERSQ 0.100000 ; -END ALU4 - - -LAYER VIA4 - TYPE CUT ; -END VIA4 - - -LAYER ALU5 - TYPE ROUTING ; - WIDTH 2.00 ; - SPACING 3.00 ; - PITCH 5.00 ; - DIRECTION VERTICAL ; - CAPACITANCE CPERSQDIST 0.000032 ; - RESISTANCE RPERSQ 0.100000 ; -END ALU5 - - -LAYER VIA5 - TYPE CUT ; -END VIA5 - - -LAYER ALU6 - TYPE ROUTING ; - WIDTH 2.00 ; - SPACING 3.00 ; - PITCH 5.00 ; - DIRECTION HORIZONTAL ; - CAPACITANCE CPERSQDIST 0.000032 ; - RESISTANCE RPERSQ 0.100000 ; -END ALU6 - - -#VIA CONT_POLY DEFAULT -# LAYER POLY ; -# RECT -1.50 -1.50 1.50 1.50 ; -# LAYER VIAP ; -# RECT -0.50 -0.50 0.50 0.50 ; -# LAYER ALU1 ; -# RECT -1.00 -1.00 1.00 1.00 ; -#END CONT_POLY - - -VIA CONT_VIA DEFAULT - LAYER ALU1 ; - RECT -1.00 -1.00 1.00 1.00 ; - LAYER VIA1 ; - RECT -0.50 -0.50 0.50 0.50 ; - LAYER ALU2 ; - RECT -1.00 -1.00 1.00 1.00 ; -END CONT_VIA - - -VIA CONT_VIA2 DEFAULT - LAYER ALU3 ; - RECT -1.00 -1.00 1.00 1.00 ; - LAYER VIA2 ; - RECT -0.50 -0.50 0.50 0.50 ; - LAYER ALU2 ; - RECT -1.00 -1.00 1.00 1.00 ; -END CONT_VIA2 - - -VIA CONT_VIA3 DEFAULT - LAYER ALU4 ; - RECT -1.00 -1.00 1.00 1.00 ; - LAYER VIA3 ; - RECT -0.50 -0.50 0.50 0.50 ; - LAYER ALU3 ; - RECT -1.00 -1.00 1.00 1.00 ; -END CONT_VIA3 - - -VIA CONT_VIA4 DEFAULT - LAYER ALU5 ; - RECT -1.00 -1.00 1.00 1.00 ; - LAYER VIA4 ; - RECT -0.50 -0.50 0.50 0.50 ; - LAYER ALU4 ; - RECT -1.00 -1.00 1.00 1.00 ; -END CONT_VIA4 - - -VIA CONT_VIA5 DEFAULT - LAYER ALU6 ; - RECT -1.00 -1.00 1.00 1.00 ; - LAYER VIA5 ; - RECT -0.50 -0.50 0.50 0.50 ; - LAYER ALU5 ; - RECT -1.00 -1.00 1.00 1.00 ; -END CONT_VIA5 - - -VIARULE TURN_ALU1 GENERATE - LAYER ALU1 ; - DIRECTION vertical ; - - LAYER ALU1 ; - DIRECTION horizontal ; -END TURN_ALU1 - - -VIARULE TURN_ALU2 GENERATE - LAYER ALU2 ; - DIRECTION vertical ; - - LAYER ALU2 ; - DIRECTION horizontal ; -END TURN_ALU2 - - -VIARULE TURN_ALU3 GENERATE - LAYER ALU3 ; - DIRECTION vertical ; - - LAYER ALU3 ; - DIRECTION horizontal ; -END TURN_ALU3 - - -VIARULE TURN_ALU4 GENERATE - LAYER ALU4 ; - DIRECTION vertical ; - - LAYER ALU4 ; - DIRECTION horizontal ; -END TURN_ALU4 - - -VIARULE TURN_ALU5 GENERATE - LAYER ALU5 ; - DIRECTION vertical ; - - LAYER ALU5 ; - DIRECTION horizontal ; -END TURN_ALU5 - - -VIARULE TURN_ALU6 GENERATE - LAYER ALU6 ; - DIRECTION vertical ; - - LAYER ALU6 ; - DIRECTION horizontal ; -END TURN_ALU6 - - -#VIARULE VIA1_HV -# LAYER ALU1 ; -# DIRECTION VERTICAL ; -# OVERHANG 0.50 ; -# METALOVERHANG 0.50 ; -# -# LAYER ALU2 ; -# DIRECTION HORIZONTAL ; -# OVERHANG 0.50 ; -# METALOVERHANG 0.50 ; -# -# VIA CONT_VIA ; -#END VIA1_HV -# -# -#VIARULE VIA2_VH -# LAYER ALU2 ; -# DIRECTION HORIZONTAL ; -# OVERHANG 0.50 ; -# METALOVERHANG 0.50 ; -# -# LAYER ALU3 ; -# DIRECTION VERTICAL ; -# OVERHANG 0.50 ; -# METALOVERHANG 0.50 ; -# -# VIA CONT_VIA2 ; -#END VIA2_VH -# -# -#VIARULE VIA3_VH -# LAYER ALU3 ; -# DIRECTION HORIZONTAL ; -# OVERHANG 0.50 ; -# METALOVERHANG 0.50 ; -# -# LAYER ALU4 ; -# DIRECTION VERTICAL ; -# OVERHANG 0.50 ; -# METALOVERHANG 0.50 ; -# -# VIA CONT_VIA3 ; -#END VIA3_VH - - -VIARULE genVIA1_HV GENERATE - LAYER ALU1 ; - DIRECTION VERTICAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER ALU2 ; - DIRECTION HORIZONTAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER VIA1 ; - RECT -0.50 -0.50 0.50 0.50 ; - SPACING 3.00 BY 3.00 ; -END genVIA1_HV - - -VIARULE genVIA1_VH GENERATE - LAYER ALU1 ; - DIRECTION HORIZONTAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER ALU2 ; - DIRECTION VERTICAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER VIA1 ; - RECT -0.50 -0.50 0.50 0.50 ; - SPACING 3.00 BY 3.00 ; -END genVIA1_VH - - -VIARULE genVIA2_VH GENERATE - LAYER ALU2 ; - DIRECTION HORIZONTAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER ALU3 ; - DIRECTION VERTICAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER VIA2 ; - RECT -0.50 -0.50 0.50 0.50 ; - SPACING 3.00 BY 3.00 ; -END genVIA2_VH - - -VIARULE genVIA2_HV GENERATE - LAYER ALU2 ; - DIRECTION VERTICAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER ALU3 ; - DIRECTION HORIZONTAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER VIA2 ; - RECT -0.50 -0.50 0.50 0.50 ; - SPACING 3.00 BY 3.00 ; -END genVIA2_HV - - -VIARULE genVIA3_VH GENERATE - LAYER ALU3 ; - DIRECTION HORIZONTAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER ALU4 ; - DIRECTION VERTICAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER VIA3 ; - RECT -0.50 -0.50 0.50 0.50 ; - SPACING 3.00 BY 3.00 ; -END genVIA3_VH - - -VIARULE genVIA3_HV GENERATE - LAYER ALU3 ; - DIRECTION VERTICAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER ALU4 ; - DIRECTION HORIZONTAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER VIA3 ; - RECT -0.50 -0.50 0.50 0.50 ; - SPACING 3.00 BY 3.00 ; -END genVIA3_HV - - -SPACING - SAMENET VIAP VIAP 3.00 ; - SAMENET VIA1 VIA1 3.00 ; - SAMENET VIA2 VIA2 3.00 ; - SAMENET VIAP VIA1 3.00 STACK ; - SAMENET VIA1 VIA2 3.00 STACK ; - SAMENET VIA2 VIA3 3.00 STACK ; - SAMENET VIA3 VIA4 3.00 STACK ; - SAMENET VIA4 VIA5 3.00 STACK ; - SAMENET POLY POLY 3.00 ; - SAMENET ALU1 ALU1 3.00 STACK ; - SAMENET ALU2 ALU2 3.00 STACK ; - SAMENET ALU3 ALU3 3.00 STACK ; - SAMENET ALU4 ALU4 3.00 STACK ; - SAMENET ALU5 ALU5 3.00 STACK ; - SAMENET ALU6 ALU6 3.00 ; -END SPACING - - -SITE core - SYMMETRY y ; - CLASS CORE ; - SIZE 5.00 BY 50.00 ; -END core - - -SITE pad - SYMMETRY y ; - CLASS PAD ; - SIZE 1.00 BY 500.00 ; -END pad - - -SITE corner - SYMMETRY y r90 ; - CLASS PAD ; - SIZE 500.00 BY 500.00 ; -END corner - - -END LIBRARY diff --git a/crlcore/src/ccore/openaccess/testDriver/sxlib2lef/sxlib.lef.bak b/crlcore/src/ccore/openaccess/testDriver/sxlib2lef/sxlib.lef.bak deleted file mode 100644 index 26955877..00000000 --- a/crlcore/src/ccore/openaccess/testDriver/sxlib2lef/sxlib.lef.bak +++ /dev/null @@ -1,8417 +0,0 @@ -# -# $Id: cmos.lef,v 1.6 2005/03/01 14:59:15 jpc Exp $ -# -# /------------------------------------------------------------------\ -# | | -# | A l l i a n c e C A D S y s t e m | -# | S i l i c o n E n s e m b l e / A l l i a n c e | -# | | -# | Author : Jean-Paul CHAPUT | -# | E-mail : alliance-users@asim.lip6.fr | -# | ================================================================ | -# | LEF : "./cmos_12.lef" | -# | **************************************************************** | -# | U p d a t e s | -# | | -# \------------------------------------------------------------------/ -# - - -VERSION 5.2 ; -NAMESCASESENSITIVE ON ; -BUSBITCHARS "()" ; -DIVIDERCHAR "." ; - -#NOWIREEXTENSIONATPIN ON ; - - -#UNITS -# DATABASE MICRONS 100 ; -#END UNITS - - -LAYER POLY - TYPE MASTERSLICE ; -END POLY - - -LAYER VIAP - TYPE CUT ; -END VIAP - - -LAYER ALU1 - TYPE ROUTING ; - WIDTH 2.00 ; - SPACING 3.00 ; - PITCH 5.00 ; - DIRECTION VERTICAL ; - CAPACITANCE CPERSQDIST 0.000032 ; - RESISTANCE RPERSQ 0.100000 ; -END ALU1 - - -LAYER VIA1 - TYPE CUT ; -END VIA1 - - -LAYER ALU2 - TYPE ROUTING ; - WIDTH 2.00 ; - SPACING 3.00 ; - PITCH 5.00 ; - DIRECTION HORIZONTAL ; - CAPACITANCE CPERSQDIST 0.000032 ; - RESISTANCE RPERSQ 0.100000 ; -END ALU2 - - -LAYER VIA2 - TYPE CUT ; -END VIA2 - - -LAYER ALU3 - TYPE ROUTING ; - WIDTH 2.00 ; - SPACING 3.00 ; - PITCH 5.00 ; - DIRECTION VERTICAL ; - CAPACITANCE CPERSQDIST 0.000032 ; - RESISTANCE RPERSQ 0.100000 ; -END ALU3 - - -LAYER VIA3 - TYPE CUT ; -END VIA3 - - -LAYER ALU4 - TYPE ROUTING ; - WIDTH 2.00 ; - SPACING 3.00 ; - PITCH 5.00 ; - DIRECTION HORIZONTAL ; - CAPACITANCE CPERSQDIST 0.000032 ; - RESISTANCE RPERSQ 0.100000 ; -END ALU4 - - -LAYER VIA4 - TYPE CUT ; -END VIA4 - - -LAYER ALU5 - TYPE ROUTING ; - WIDTH 2.00 ; - SPACING 3.00 ; - PITCH 5.00 ; - DIRECTION VERTICAL ; - CAPACITANCE CPERSQDIST 0.000032 ; - RESISTANCE RPERSQ 0.100000 ; -END ALU5 - - -LAYER VIA5 - TYPE CUT ; -END VIA5 - - -LAYER ALU6 - TYPE ROUTING ; - WIDTH 2.00 ; - SPACING 3.00 ; - PITCH 5.00 ; - DIRECTION HORIZONTAL ; - CAPACITANCE CPERSQDIST 0.000032 ; - RESISTANCE RPERSQ 0.100000 ; -END ALU6 - - -#VIA CONT_POLY DEFAULT -# LAYER POLY ; -# RECT -1.50 -1.50 1.50 1.50 ; -# LAYER VIAP ; -# RECT -0.50 -0.50 0.50 0.50 ; -# LAYER ALU1 ; -# RECT -1.00 -1.00 1.00 1.00 ; -#END CONT_POLY - - -VIA CONT_VIA DEFAULT - LAYER ALU1 ; - RECT -1.00 -1.00 1.00 1.00 ; - LAYER VIA1 ; - RECT -0.50 -0.50 0.50 0.50 ; - LAYER ALU2 ; - RECT -1.00 -1.00 1.00 1.00 ; -END CONT_VIA - - -VIA CONT_VIA2 DEFAULT - LAYER ALU3 ; - RECT -1.00 -1.00 1.00 1.00 ; - LAYER VIA2 ; - RECT -0.50 -0.50 0.50 0.50 ; - LAYER ALU2 ; - RECT -1.00 -1.00 1.00 1.00 ; -END CONT_VIA2 - - -VIA CONT_VIA3 DEFAULT - LAYER ALU4 ; - RECT -1.00 -1.00 1.00 1.00 ; - LAYER VIA3 ; - RECT -0.50 -0.50 0.50 0.50 ; - LAYER ALU3 ; - RECT -1.00 -1.00 1.00 1.00 ; -END CONT_VIA3 - - -VIA CONT_VIA4 DEFAULT - LAYER ALU5 ; - RECT -1.00 -1.00 1.00 1.00 ; - LAYER VIA4 ; - RECT -0.50 -0.50 0.50 0.50 ; - LAYER ALU4 ; - RECT -1.00 -1.00 1.00 1.00 ; -END CONT_VIA4 - - -VIA CONT_VIA5 DEFAULT - LAYER ALU6 ; - RECT -1.00 -1.00 1.00 1.00 ; - LAYER VIA5 ; - RECT -0.50 -0.50 0.50 0.50 ; - LAYER ALU5 ; - RECT -1.00 -1.00 1.00 1.00 ; -END CONT_VIA5 - - -VIARULE TURN_ALU1 GENERATE - LAYER ALU1 ; - DIRECTION vertical ; - - LAYER ALU1 ; - DIRECTION horizontal ; -END TURN_ALU1 - - -VIARULE TURN_ALU2 GENERATE - LAYER ALU2 ; - DIRECTION vertical ; - - LAYER ALU2 ; - DIRECTION horizontal ; -END TURN_ALU2 - - -VIARULE TURN_ALU3 GENERATE - LAYER ALU3 ; - DIRECTION vertical ; - - LAYER ALU3 ; - DIRECTION horizontal ; -END TURN_ALU3 - - -VIARULE TURN_ALU4 GENERATE - LAYER ALU4 ; - DIRECTION vertical ; - - LAYER ALU4 ; - DIRECTION horizontal ; -END TURN_ALU4 - - -VIARULE TURN_ALU5 GENERATE - LAYER ALU5 ; - DIRECTION vertical ; - - LAYER ALU5 ; - DIRECTION horizontal ; -END TURN_ALU5 - - -VIARULE TURN_ALU6 GENERATE - LAYER ALU6 ; - DIRECTION vertical ; - - LAYER ALU6 ; - DIRECTION horizontal ; -END TURN_ALU6 - - -#VIARULE VIA1_HV -# LAYER ALU1 ; -# DIRECTION VERTICAL ; -# OVERHANG 0.50 ; -# METALOVERHANG 0.50 ; -# -# LAYER ALU2 ; -# DIRECTION HORIZONTAL ; -# OVERHANG 0.50 ; -# METALOVERHANG 0.50 ; -# -# VIA CONT_VIA ; -#END VIA1_HV -# -# -#VIARULE VIA2_VH -# LAYER ALU2 ; -# DIRECTION HORIZONTAL ; -# OVERHANG 0.50 ; -# METALOVERHANG 0.50 ; -# -# LAYER ALU3 ; -# DIRECTION VERTICAL ; -# OVERHANG 0.50 ; -# METALOVERHANG 0.50 ; -# -# VIA CONT_VIA2 ; -#END VIA2_VH -# -# -#VIARULE VIA3_VH -# LAYER ALU3 ; -# DIRECTION HORIZONTAL ; -# OVERHANG 0.50 ; -# METALOVERHANG 0.50 ; -# -# LAYER ALU4 ; -# DIRECTION VERTICAL ; -# OVERHANG 0.50 ; -# METALOVERHANG 0.50 ; -# -# VIA CONT_VIA3 ; -#END VIA3_VH - - -VIARULE genVIA1_HV GENERATE - LAYER ALU1 ; - DIRECTION VERTICAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER ALU2 ; - DIRECTION HORIZONTAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER VIA1 ; - RECT -0.50 -0.50 0.50 0.50 ; - SPACING 3.00 BY 3.00 ; -END genVIA1_HV - - -VIARULE genVIA1_VH GENERATE - LAYER ALU1 ; - DIRECTION HORIZONTAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER ALU2 ; - DIRECTION VERTICAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER VIA1 ; - RECT -0.50 -0.50 0.50 0.50 ; - SPACING 3.00 BY 3.00 ; -END genVIA1_VH - - -VIARULE genVIA2_VH GENERATE - LAYER ALU2 ; - DIRECTION HORIZONTAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER ALU3 ; - DIRECTION VERTICAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER VIA2 ; - RECT -0.50 -0.50 0.50 0.50 ; - SPACING 3.00 BY 3.00 ; -END genVIA2_VH - - -VIARULE genVIA2_HV GENERATE - LAYER ALU2 ; - DIRECTION VERTICAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER ALU3 ; - DIRECTION HORIZONTAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER VIA2 ; - RECT -0.50 -0.50 0.50 0.50 ; - SPACING 3.00 BY 3.00 ; -END genVIA2_HV - - -VIARULE genVIA3_VH GENERATE - LAYER ALU3 ; - DIRECTION HORIZONTAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER ALU4 ; - DIRECTION VERTICAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER VIA3 ; - RECT -0.50 -0.50 0.50 0.50 ; - SPACING 3.00 BY 3.00 ; -END genVIA3_VH - - -VIARULE genVIA3_HV GENERATE - LAYER ALU3 ; - DIRECTION VERTICAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER ALU4 ; - DIRECTION HORIZONTAL ; - OVERHANG 0.50 ; - METALOVERHANG 0.50 ; - - LAYER VIA3 ; - RECT -0.50 -0.50 0.50 0.50 ; - SPACING 3.00 BY 3.00 ; -END genVIA3_HV - - -SPACING - SAMENET VIAP VIAP 3.00 ; - SAMENET VIA1 VIA1 3.00 ; - SAMENET VIA2 VIA2 3.00 ; - SAMENET VIAP VIA1 3.00 STACK ; - SAMENET VIA1 VIA2 3.00 STACK ; - SAMENET VIA2 VIA3 3.00 STACK ; - SAMENET VIA3 VIA4 3.00 STACK ; - SAMENET VIA4 VIA5 3.00 STACK ; - SAMENET POLY POLY 3.00 ; - SAMENET ALU1 ALU1 3.00 STACK ; - SAMENET ALU2 ALU2 3.00 STACK ; - SAMENET ALU3 ALU3 3.00 STACK ; - SAMENET ALU4 ALU4 3.00 STACK ; - SAMENET ALU5 ALU5 3.00 STACK ; - SAMENET ALU6 ALU6 3.00 ; -END SPACING - - -SITE core - SYMMETRY y ; - CLASS CORE ; - SIZE 5.00 BY 50.00 ; -END core - - -SITE pad - SYMMETRY y ; - CLASS PAD ; - SIZE 1.00 BY 500.00 ; -END pad - - -SITE corner - SYMMETRY y r90 ; - CLASS PAD ; - SIZE 500.00 BY 500.00 ; -END corner - - -MACRO a2_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 25.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END q - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 22.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 22.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 23.50 41.00 ; - END -END a2_x2 - -MACRO a2_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 30.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END i1 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 27.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 27.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 28.50 41.00 ; - END -END a2_x4 - -MACRO a3_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 30.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 39.00 26.00 41.00 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END q - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i0 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 27.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 27.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 28.50 41.00 ; - END -END a3_x2 - -MACRO a3_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 35.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 39.00 26.00 41.00 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 32.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 32.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 33.50 41.00 ; - END -END a3_x4 - -MACRO a4_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 35.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 39.00 31.00 41.00 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - RECT 29.00 9.00 31.00 11.00 ; - END - END q - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i3 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END i2 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 32.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 32.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 33.50 41.00 ; - END -END a4_x2 - -MACRO a4_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 40.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 39.00 31.00 41.00 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - RECT 29.00 9.00 31.00 11.00 ; - END - END q - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i3 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END i2 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 37.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 37.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 38.50 41.00 ; - END -END a4_x4 - -MACRO an12_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 25.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - END - END q - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 22.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 22.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 23.50 41.00 ; - END -END an12_x1 - -MACRO an12_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 40.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 39.00 31.00 41.00 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - RECT 29.00 9.00 31.00 11.00 ; - END - END q - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 39.00 26.00 41.00 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 37.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 37.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 38.50 41.00 ; - END -END an12_x4 - -MACRO ao22_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 30.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 39.00 26.00 41.00 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END q - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 27.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 27.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 28.50 41.00 ; - END -END ao22_x2 - -MACRO ao22_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 40.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 39.00 31.00 41.00 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - RECT 29.00 9.00 31.00 11.00 ; - END - END q - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - END - END i0 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 37.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 37.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 38.50 41.00 ; - END -END ao22_x4 - -MACRO ao2o22_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 45.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 39.00 41.00 41.00 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - RECT 39.00 9.00 41.00 11.00 ; - END - END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i2 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i3 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 42.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 42.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 43.50 41.00 ; - END -END ao2o22_x2 - -MACRO ao2o22_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 50.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 39.00 41.00 41.00 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - RECT 39.00 9.00 41.00 11.00 ; - END - END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i2 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i3 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 47.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 47.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 48.50 41.00 ; - END -END ao2o22_x4 - -MACRO buf_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 20.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END q - PIN i - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 17.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 17.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 18.50 41.00 ; - END -END buf_x2 - -MACRO buf_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 25.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END q - PIN i - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 22.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 22.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 23.50 41.00 ; - END -END buf_x4 - -MACRO buf_x8 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 40.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END q - PIN i - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 37.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 37.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 38.50 41.00 ; - END -END buf_x8 - -MACRO fulladder_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 100.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN cout - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - LAYER ALU1 ; - RECT 39.00 14.00 41.00 16.00 ; - RECT 39.00 9.00 41.00 11.00 ; - END - END cout - PIN sout - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 49.00 34.00 51.00 36.00 ; - RECT 49.00 29.00 51.00 31.00 ; - RECT 49.00 24.00 51.00 26.00 ; - RECT 49.00 19.00 51.00 21.00 ; - RECT 49.00 14.00 51.00 16.00 ; - RECT 49.00 9.00 51.00 11.00 ; - END - END sout - PIN cin1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END cin1 - PIN a2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END a2 - PIN b2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END b2 - PIN a3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 59.00 29.00 61.00 31.00 ; - RECT 59.00 24.00 61.00 26.00 ; - RECT 59.00 19.00 61.00 21.00 ; - RECT 59.00 14.00 61.00 16.00 ; - END - END a3 - PIN b3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 64.00 29.00 66.00 31.00 ; - RECT 64.00 24.00 66.00 26.00 ; - RECT 64.00 19.00 66.00 21.00 ; - RECT 64.00 14.00 66.00 16.00 ; - END - END b3 - PIN cin2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 69.00 29.00 71.00 31.00 ; - RECT 69.00 24.00 71.00 26.00 ; - RECT 69.00 19.00 71.00 21.00 ; - RECT 69.00 14.00 71.00 16.00 ; - END - END cin2 - PIN cin3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 84.00 29.00 86.00 31.00 ; - RECT 84.00 24.00 86.00 26.00 ; - RECT 84.00 19.00 86.00 21.00 ; - RECT 84.00 14.00 86.00 16.00 ; - END - END cin3 - PIN a1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END a1 - PIN b1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END b1 - PIN a4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 89.00 34.00 91.00 36.00 ; - RECT 89.00 29.00 91.00 31.00 ; - RECT 89.00 24.00 91.00 26.00 ; - RECT 89.00 19.00 91.00 21.00 ; - RECT 89.00 14.00 91.00 16.00 ; - END - END a4 - PIN b4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 94.00 34.00 96.00 36.00 ; - RECT 94.00 29.00 96.00 31.00 ; - RECT 94.00 24.00 96.00 26.00 ; - RECT 94.00 19.00 96.00 21.00 ; - RECT 94.00 14.00 96.00 16.00 ; - END - END b4 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 97.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 97.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 98.50 41.00 ; - END -END fulladder_x2 - -MACRO fulladder_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 105.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN sout - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 54.00 34.00 56.00 36.00 ; - RECT 54.00 29.00 56.00 31.00 ; - RECT 54.00 24.00 56.00 26.00 ; - RECT 54.00 19.00 56.00 21.00 ; - RECT 54.00 14.00 56.00 16.00 ; - RECT 54.00 9.00 56.00 11.00 ; - END - END sout - PIN cout - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 44.00 34.00 46.00 36.00 ; - RECT 44.00 29.00 46.00 31.00 ; - RECT 44.00 24.00 46.00 26.00 ; - RECT 44.00 19.00 46.00 21.00 ; - RECT 44.00 14.00 46.00 16.00 ; - RECT 44.00 9.00 46.00 11.00 ; - END - END cout - PIN a1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END a1 - PIN b1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END b1 - PIN cin1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END cin1 - PIN a2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END a2 - PIN b2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END b2 - PIN b4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 99.00 34.00 101.00 36.00 ; - RECT 99.00 29.00 101.00 31.00 ; - RECT 99.00 24.00 101.00 26.00 ; - RECT 99.00 19.00 101.00 21.00 ; - RECT 99.00 14.00 101.00 16.00 ; - END - END b4 - PIN a4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 94.00 34.00 96.00 36.00 ; - RECT 94.00 29.00 96.00 31.00 ; - RECT 94.00 24.00 96.00 26.00 ; - RECT 94.00 19.00 96.00 21.00 ; - RECT 94.00 14.00 96.00 16.00 ; - END - END a4 - PIN cin3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 89.00 29.00 91.00 31.00 ; - RECT 89.00 24.00 91.00 26.00 ; - RECT 89.00 19.00 91.00 21.00 ; - RECT 89.00 14.00 91.00 16.00 ; - END - END cin3 - PIN b3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 69.00 29.00 71.00 31.00 ; - RECT 69.00 24.00 71.00 26.00 ; - RECT 69.00 19.00 71.00 21.00 ; - RECT 69.00 14.00 71.00 16.00 ; - END - END b3 - PIN cin2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 74.00 29.00 76.00 31.00 ; - RECT 74.00 24.00 76.00 26.00 ; - RECT 74.00 19.00 76.00 21.00 ; - RECT 74.00 14.00 76.00 16.00 ; - END - END cin2 - PIN a3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 64.00 29.00 66.00 31.00 ; - RECT 64.00 24.00 66.00 26.00 ; - RECT 64.00 19.00 66.00 21.00 ; - END - END a3 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 102.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 102.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 103.50 41.00 ; - END -END fulladder_x4 - -MACRO halfadder_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 80.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN sout - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 74.00 39.00 76.00 41.00 ; - RECT 74.00 34.00 76.00 36.00 ; - RECT 74.00 29.00 76.00 31.00 ; - RECT 74.00 24.00 76.00 26.00 ; - RECT 74.00 19.00 76.00 21.00 ; - RECT 74.00 14.00 76.00 16.00 ; - RECT 74.00 9.00 76.00 11.00 ; - END - END sout - PIN cout - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END cout - PIN b - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 34.00 36.00 36.00 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - RECT 34.00 9.00 36.00 11.00 ; - END - END b - PIN a - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END a - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 77.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 77.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 78.50 41.00 ; - END -END halfadder_x2 - -MACRO halfadder_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 90.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN sout - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 79.00 39.00 81.00 41.00 ; - RECT 79.00 34.00 81.00 36.00 ; - RECT 79.00 29.00 81.00 31.00 ; - RECT 79.00 24.00 81.00 26.00 ; - RECT 79.00 19.00 81.00 21.00 ; - RECT 79.00 14.00 81.00 16.00 ; - RECT 79.00 9.00 81.00 11.00 ; - END - END sout - PIN cout - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END cout - PIN b - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - RECT 39.00 9.00 41.00 11.00 ; - END - END b - PIN a - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END a - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 87.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 87.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 88.50 41.00 ; - END -END halfadder_x4 - -MACRO inv_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 15.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END nq - PIN i - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 12.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 12.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 13.50 41.00 ; - END -END inv_x1 - -MACRO inv_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 15.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END nq - PIN i - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 12.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 12.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 13.50 41.00 ; - END -END inv_x2 - -MACRO inv_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 20.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END nq - PIN i - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 17.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 17.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 18.50 41.00 ; - END -END inv_x4 - -MACRO inv_x8 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 35.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END nq - PIN i - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 32.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 32.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 33.50 41.00 ; - END -END inv_x8 - -MACRO mx2_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 45.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 39.00 41.00 41.00 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - RECT 39.00 9.00 41.00 11.00 ; - END - END q - PIN cmd - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END cmd - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 39.00 31.00 41.00 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - RECT 29.00 9.00 31.00 11.00 ; - END - END i1 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 42.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 42.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 43.50 41.00 ; - END -END mx2_x2 - -MACRO mx2_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 50.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 39.00 41.00 41.00 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - RECT 39.00 9.00 41.00 11.00 ; - END - END q - PIN cmd - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END cmd - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 39.00 31.00 41.00 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - RECT 29.00 9.00 31.00 11.00 ; - END - END i1 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 47.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 47.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 48.50 41.00 ; - END -END mx2_x4 - -MACRO mx3_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 65.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 59.00 14.00 61.00 16.00 ; - RECT 59.00 9.00 61.00 11.00 ; - LAYER ALU1 ; - RECT 59.00 39.00 61.00 41.00 ; - RECT 59.00 34.00 61.00 36.00 ; - RECT 59.00 29.00 61.00 31.00 ; - RECT 59.00 24.00 61.00 26.00 ; - END - END q - PIN cmd1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END cmd1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 24.00 16.00 26.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 24.00 26.00 26.00 ; - END - END i1 - PIN cmd0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - END - END cmd0 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 19.00 41.00 21.00 ; - LAYER ALU1 ; - RECT 44.00 24.00 46.00 26.00 ; - LAYER ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 62.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 62.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 63.50 41.00 ; - END -END mx3_x2 - -MACRO mx3_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 70.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 64.00 19.00 66.00 21.00 ; - LAYER ALU1 ; - RECT 59.00 14.00 61.00 16.00 ; - RECT 59.00 9.00 61.00 11.00 ; - LAYER ALU1 ; - RECT 59.00 39.00 61.00 41.00 ; - RECT 59.00 34.00 61.00 36.00 ; - RECT 59.00 29.00 61.00 31.00 ; - RECT 59.00 24.00 61.00 26.00 ; - END - END q - PIN cmd0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - END - END cmd0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 24.00 26.00 26.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 24.00 16.00 26.00 ; - END - END i2 - PIN cmd1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END cmd1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 19.00 41.00 21.00 ; - LAYER ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - LAYER ALU1 ; - RECT 44.00 24.00 46.00 26.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 67.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 67.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 68.50 41.00 ; - END -END mx3_x4 - -MACRO na2_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 20.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END nq - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 17.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 17.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 18.50 41.00 ; - END -END na2_x1 - -MACRO na2_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 35.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END nq - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 32.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 32.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 33.50 41.00 ; - END -END na2_x4 - -MACRO na3_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 25.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 22.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 22.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 23.50 41.00 ; - END -END na3_x1 - -MACRO na3_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 40.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END nq - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 37.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 37.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 38.50 41.00 ; - END -END na3_x4 - -MACRO na4_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 30.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 39.00 26.00 41.00 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END i2 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i3 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 27.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 27.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 28.50 41.00 ; - END -END na4_x1 - -MACRO na4_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 50.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END nq - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 34.00 36.00 36.00 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - RECT 34.00 9.00 36.00 11.00 ; - END - END i2 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - RECT 39.00 9.00 41.00 11.00 ; - END - END i3 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - RECT 29.00 9.00 31.00 11.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 47.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 47.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 48.50 41.00 ; - END -END na4_x4 - -MACRO nao22_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 30.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 27.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 27.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 28.50 41.00 ; - END -END nao22_x1 - -MACRO nao22_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 50.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 39.00 41.00 41.00 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - RECT 39.00 9.00 41.00 11.00 ; - END - END nq - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 14.00 26.00 16.00 ; - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 47.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 47.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 48.50 41.00 ; - END -END nao22_x4 - -MACRO nao2o22_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 35.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - END - END i1 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 39.00 26.00 41.00 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 32.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 32.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 33.50 41.00 ; - END -END nao2o22_x1 - -MACRO nao2o22_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 55.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 44.00 39.00 46.00 41.00 ; - RECT 44.00 34.00 46.00 36.00 ; - RECT 44.00 29.00 46.00 31.00 ; - RECT 44.00 24.00 46.00 26.00 ; - RECT 44.00 19.00 46.00 21.00 ; - RECT 44.00 14.00 46.00 16.00 ; - RECT 44.00 9.00 46.00 11.00 ; - END - END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - END - END i1 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 52.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 52.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 53.50 41.00 ; - END -END nao2o22_x4 - -MACRO nmx2_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 35.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - LAYER ALU1 ; - RECT 19.00 9.00 21.00 11.00 ; - LAYER ALU1 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END nq - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 39.00 31.00 41.00 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - RECT 29.00 9.00 31.00 11.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i0 - PIN cmd - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - END - END cmd - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 32.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 32.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 33.50 41.00 ; - END -END nmx2_x1 - -MACRO nmx2_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 60.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 49.00 39.00 51.00 41.00 ; - RECT 49.00 34.00 51.00 36.00 ; - RECT 49.00 29.00 51.00 31.00 ; - RECT 49.00 24.00 51.00 26.00 ; - RECT 49.00 19.00 51.00 21.00 ; - RECT 49.00 14.00 51.00 16.00 ; - RECT 49.00 9.00 51.00 11.00 ; - END - END nq - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 39.00 31.00 41.00 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - RECT 29.00 9.00 31.00 11.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i0 - PIN cmd - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END cmd - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 57.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 57.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 58.50 41.00 ; - END -END nmx2_x4 - -MACRO nmx3_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 60.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 54.00 34.00 56.00 36.00 ; - RECT 54.00 29.00 56.00 31.00 ; - RECT 54.00 24.00 56.00 26.00 ; - RECT 54.00 19.00 56.00 21.00 ; - RECT 54.00 14.00 56.00 16.00 ; - RECT 54.00 9.00 56.00 11.00 ; - END - END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - LAYER ALU1 ; - RECT 44.00 24.00 46.00 26.00 ; - LAYER ALU1 ; - RECT 39.00 19.00 41.00 21.00 ; - END - END i0 - PIN cmd1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END cmd1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 24.00 16.00 26.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 24.00 26.00 26.00 ; - END - END i1 - PIN cmd0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - END - END cmd0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 57.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 57.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 58.50 41.00 ; - END -END nmx3_x1 - -MACRO nmx3_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 75.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 59.00 39.00 61.00 41.00 ; - RECT 59.00 34.00 61.00 36.00 ; - RECT 59.00 29.00 61.00 31.00 ; - RECT 59.00 24.00 61.00 26.00 ; - RECT 59.00 19.00 61.00 21.00 ; - RECT 59.00 14.00 61.00 16.00 ; - END - END nq - PIN cmd0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - END - END cmd0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 24.00 26.00 26.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 24.00 16.00 26.00 ; - END - END i2 - PIN cmd1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END cmd1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 19.00 41.00 21.00 ; - LAYER ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - LAYER ALU1 ; - RECT 44.00 24.00 46.00 26.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 72.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 72.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 73.50 41.00 ; - END -END nmx3_x4 - -MACRO no2_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 20.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END nq - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 17.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 17.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 18.50 41.00 ; - END -END no2_x1 - -MACRO no2_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 35.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i1 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 32.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 32.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 33.50 41.00 ; - END -END no2_x4 - -MACRO no3_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 25.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END nq - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i2 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 22.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 22.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 23.50 41.00 ; - END -END no3_x1 - -MACRO no3_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 40.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END nq - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 37.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 37.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 38.50 41.00 ; - END -END no3_x4 - -MACRO no4_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 30.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END nq - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 39.00 26.00 41.00 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i3 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i0 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 27.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 27.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 28.50 41.00 ; - END -END no4_x1 - -MACRO no4_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 50.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 39.00 36.00 41.00 ; - RECT 34.00 34.00 36.00 36.00 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - END - END nq - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 39.00 26.00 41.00 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i3 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i0 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 47.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 47.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 48.50 41.00 ; - END -END no4_x4 - -MACRO noa22_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 30.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 27.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 27.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 28.50 41.00 ; - END -END noa22_x1 - -MACRO noa22_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 50.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 39.00 41.00 41.00 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - RECT 39.00 9.00 41.00 11.00 ; - END - END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 47.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 47.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 48.50 41.00 ; - END -END noa22_x4 - -MACRO noa2a22_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 35.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END nq - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END i2 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i3 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 32.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 32.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 33.50 41.00 ; - END -END noa2a22_x1 - -MACRO noa2a22_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 55.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 44.00 39.00 46.00 41.00 ; - RECT 44.00 34.00 46.00 36.00 ; - RECT 44.00 29.00 46.00 31.00 ; - RECT 44.00 24.00 46.00 26.00 ; - RECT 44.00 19.00 46.00 21.00 ; - RECT 44.00 14.00 46.00 16.00 ; - RECT 44.00 9.00 46.00 11.00 ; - END - END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 52.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 52.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 53.50 41.00 ; - END -END noa2a22_x4 - -MACRO noa2a2a23_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 50.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END nq - PIN i5 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i5 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i2 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i3 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 44.00 29.00 46.00 31.00 ; - RECT 44.00 24.00 46.00 26.00 ; - RECT 44.00 19.00 46.00 21.00 ; - RECT 44.00 14.00 46.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - END - END i1 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i4 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 47.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 47.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 48.50 41.00 ; - END -END noa2a2a23_x1 - -MACRO noa2a2a23_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 65.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 49.00 39.00 51.00 41.00 ; - RECT 49.00 34.00 51.00 36.00 ; - RECT 49.00 29.00 51.00 31.00 ; - RECT 49.00 24.00 51.00 26.00 ; - RECT 49.00 19.00 51.00 21.00 ; - RECT 49.00 14.00 51.00 16.00 ; - END - END nq - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - END - END i0 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i4 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i2 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i3 - PIN i5 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i5 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 62.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 62.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 63.50 41.00 ; - END -END noa2a2a23_x4 - -MACRO noa2a2a2a24_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 70.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 59.00 34.00 61.00 36.00 ; - RECT 59.00 29.00 61.00 31.00 ; - RECT 59.00 24.00 61.00 26.00 ; - RECT 59.00 19.00 61.00 21.00 ; - RECT 59.00 14.00 61.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 54.00 34.00 56.00 36.00 ; - RECT 54.00 29.00 56.00 31.00 ; - RECT 54.00 24.00 56.00 26.00 ; - RECT 54.00 19.00 56.00 21.00 ; - RECT 54.00 14.00 56.00 16.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - END - END i2 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - END - END i3 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END i4 - PIN i5 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i5 - PIN i6 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i6 - PIN i7 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i7 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 67.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 67.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 68.50 41.00 ; - END -END noa2a2a2a24_x1 - -MACRO noa2a2a2a24_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 85.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 69.00 39.00 71.00 41.00 ; - RECT 69.00 34.00 71.00 36.00 ; - RECT 69.00 29.00 71.00 31.00 ; - RECT 69.00 24.00 71.00 26.00 ; - RECT 69.00 19.00 71.00 21.00 ; - RECT 69.00 14.00 71.00 16.00 ; - END - END nq - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - END - END i2 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - END - END i3 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END i4 - PIN i5 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i5 - PIN i6 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i6 - PIN i7 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i7 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 54.00 29.00 56.00 31.00 ; - RECT 54.00 24.00 56.00 26.00 ; - RECT 54.00 19.00 56.00 21.00 ; - RECT 54.00 14.00 56.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 64.00 34.00 66.00 36.00 ; - RECT 64.00 29.00 66.00 31.00 ; - RECT 64.00 24.00 66.00 26.00 ; - RECT 64.00 19.00 66.00 21.00 ; - RECT 64.00 14.00 66.00 16.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 82.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 82.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 83.50 41.00 ; - END -END noa2a2a2a24_x4 - -MACRO noa2ao222_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 35.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - LAYER ALU1 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END nq - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i2 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - END - END i4 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 32.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 32.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 33.50 41.00 ; - END -END noa2ao222_x1 - -MACRO noa2ao222_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 60.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 49.00 39.00 51.00 41.00 ; - RECT 49.00 34.00 51.00 36.00 ; - RECT 49.00 29.00 51.00 31.00 ; - RECT 49.00 24.00 51.00 26.00 ; - RECT 49.00 19.00 51.00 21.00 ; - RECT 49.00 14.00 51.00 16.00 ; - RECT 49.00 9.00 51.00 11.00 ; - END - END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - END - END i4 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i2 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END i3 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 57.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 57.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 58.50 41.00 ; - END -END noa2ao222_x4 - -MACRO noa3ao322_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 45.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - LAYER ALU1 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END nq - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i2 - PIN i6 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - END - END i6 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END i3 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 34.00 36.00 36.00 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - END - END i4 - PIN i5 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - END - END i5 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 42.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 42.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 43.50 41.00 ; - END -END noa3ao322_x1 - -MACRO noa3ao322_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 65.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i0 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 49.00 34.00 51.00 36.00 ; - RECT 49.00 29.00 51.00 31.00 ; - RECT 49.00 24.00 51.00 26.00 ; - RECT 49.00 19.00 51.00 21.00 ; - RECT 49.00 14.00 51.00 16.00 ; - END - END i3 - PIN i5 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 59.00 34.00 61.00 36.00 ; - RECT 59.00 29.00 61.00 31.00 ; - RECT 59.00 24.00 61.00 26.00 ; - RECT 59.00 19.00 61.00 21.00 ; - RECT 59.00 14.00 61.00 16.00 ; - END - END i5 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 54.00 34.00 56.00 36.00 ; - RECT 54.00 29.00 56.00 31.00 ; - RECT 54.00 24.00 56.00 26.00 ; - RECT 54.00 19.00 56.00 21.00 ; - RECT 54.00 14.00 56.00 16.00 ; - END - END i4 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 34.00 36.00 36.00 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - END - END i2 - PIN i6 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - END - END i6 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END i1 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 62.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 62.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 63.50 41.00 ; - END -END noa3ao322_x4 - -MACRO nts_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 30.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT TRISTATE ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END nq - PIN cmd - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END cmd - PIN i - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 27.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 27.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 28.50 41.00 ; - END -END nts_x1 - -MACRO nts_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 40.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT TRISTATE ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END nq - PIN i - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i - PIN cmd - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - RECT 29.00 9.00 31.00 11.00 ; - END - END cmd - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 37.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 37.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 38.50 41.00 ; - END -END nts_x2 - -MACRO nxr2_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 45.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 39.00 36.00 41.00 ; - RECT 34.00 34.00 36.00 36.00 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - RECT 34.00 9.00 36.00 11.00 ; - END - END i1 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 42.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 42.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 43.50 41.00 ; - END -END nxr2_x1 - -MACRO nxr2_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 60.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 49.00 39.00 51.00 41.00 ; - RECT 49.00 34.00 51.00 36.00 ; - RECT 49.00 29.00 51.00 31.00 ; - RECT 49.00 24.00 51.00 26.00 ; - RECT 49.00 19.00 51.00 21.00 ; - RECT 49.00 14.00 51.00 16.00 ; - RECT 49.00 9.00 51.00 11.00 ; - END - END nq - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 39.00 36.00 41.00 ; - RECT 34.00 34.00 36.00 36.00 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - END - END i1 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 57.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 57.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 58.50 41.00 ; - END -END nxr2_x4 - -MACRO o2_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 25.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END q - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 22.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 22.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 23.50 41.00 ; - END -END o2_x2 - -MACRO o2_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 30.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END q - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 27.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 27.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 28.50 41.00 ; - END -END o2_x4 - -MACRO o3_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 30.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 39.00 26.00 41.00 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END q - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 27.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 27.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 28.50 41.00 ; - END -END o3_x2 - -MACRO o3_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 35.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 39.00 26.00 41.00 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 32.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 32.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 33.50 41.00 ; - END -END o3_x4 - -MACRO o4_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 35.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 39.00 31.00 41.00 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - RECT 29.00 9.00 31.00 11.00 ; - END - END q - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i0 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i2 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END i3 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 32.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 32.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 33.50 41.00 ; - END -END o4_x2 - -MACRO o4_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 40.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 39.00 31.00 41.00 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - LAYER ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - RECT 34.00 9.00 36.00 11.00 ; - END - END q - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 39.00 26.00 41.00 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - END - END i3 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i0 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 37.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 37.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 38.50 41.00 ; - END -END o4_x4 - -MACRO oa22_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 30.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 39.00 26.00 41.00 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 27.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 27.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 28.50 41.00 ; - END -END oa22_x2 - -MACRO oa22_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 40.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 39.00 31.00 41.00 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - RECT 29.00 9.00 31.00 11.00 ; - END - END q - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 37.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 37.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 38.50 41.00 ; - END -END oa22_x4 - -MACRO oa2a22_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 45.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 39.00 41.00 41.00 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - RECT 39.00 9.00 41.00 11.00 ; - END - END q - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 42.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 42.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 43.50 41.00 ; - END -END oa2a22_x2 - -MACRO oa2a22_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 50.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 39.00 41.00 41.00 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - RECT 39.00 9.00 41.00 11.00 ; - END - END q - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - RECT 19.00 9.00 21.00 11.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 47.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 47.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 48.50 41.00 ; - END -END oa2a22_x4 - -MACRO oa2a2a23_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 60.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 54.00 39.00 56.00 41.00 ; - RECT 54.00 34.00 56.00 36.00 ; - RECT 54.00 29.00 56.00 31.00 ; - RECT 54.00 24.00 56.00 26.00 ; - RECT 54.00 19.00 56.00 21.00 ; - RECT 54.00 14.00 56.00 16.00 ; - RECT 54.00 9.00 56.00 11.00 ; - END - END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 44.00 29.00 46.00 31.00 ; - RECT 44.00 24.00 46.00 26.00 ; - RECT 44.00 19.00 46.00 21.00 ; - RECT 44.00 14.00 46.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - END - END i1 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i4 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i2 - PIN i5 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i5 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 57.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 57.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 58.50 41.00 ; - END -END oa2a2a23_x2 - -MACRO oa2a2a23_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 65.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 54.00 39.00 56.00 41.00 ; - RECT 54.00 34.00 56.00 36.00 ; - RECT 54.00 29.00 56.00 31.00 ; - RECT 54.00 24.00 56.00 26.00 ; - RECT 54.00 19.00 56.00 21.00 ; - RECT 54.00 14.00 56.00 16.00 ; - RECT 54.00 9.00 56.00 11.00 ; - END - END q - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 44.00 29.00 46.00 31.00 ; - RECT 44.00 24.00 46.00 26.00 ; - RECT 44.00 19.00 46.00 21.00 ; - RECT 44.00 14.00 46.00 16.00 ; - END - END i0 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i4 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i2 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i3 - PIN i5 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i5 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 62.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 62.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 63.50 41.00 ; - END -END oa2a2a23_x4 - -MACRO oa2a2a2a24_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 75.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 69.00 39.00 71.00 41.00 ; - RECT 69.00 34.00 71.00 36.00 ; - RECT 69.00 29.00 71.00 31.00 ; - RECT 69.00 24.00 71.00 26.00 ; - RECT 69.00 19.00 71.00 21.00 ; - RECT 69.00 14.00 71.00 16.00 ; - RECT 69.00 9.00 71.00 11.00 ; - END - END q - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 54.00 29.00 56.00 31.00 ; - RECT 54.00 24.00 56.00 26.00 ; - RECT 54.00 19.00 56.00 21.00 ; - RECT 54.00 14.00 56.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 64.00 34.00 66.00 36.00 ; - RECT 64.00 29.00 66.00 31.00 ; - RECT 64.00 24.00 66.00 26.00 ; - RECT 64.00 19.00 66.00 21.00 ; - RECT 64.00 14.00 66.00 16.00 ; - END - END i0 - PIN i7 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i7 - PIN i6 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i6 - PIN i5 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i5 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END i4 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 72.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 72.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 73.50 41.00 ; - END -END oa2a2a2a24_x2 - -MACRO oa2a2a2a24_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 80.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 69.00 39.00 71.00 41.00 ; - RECT 69.00 34.00 71.00 36.00 ; - RECT 69.00 29.00 71.00 31.00 ; - RECT 69.00 24.00 71.00 26.00 ; - RECT 69.00 19.00 71.00 21.00 ; - RECT 69.00 14.00 71.00 16.00 ; - RECT 69.00 9.00 71.00 11.00 ; - END - END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 64.00 34.00 66.00 36.00 ; - RECT 64.00 29.00 66.00 31.00 ; - RECT 64.00 24.00 66.00 26.00 ; - RECT 64.00 19.00 66.00 21.00 ; - RECT 64.00 14.00 66.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 54.00 29.00 56.00 31.00 ; - RECT 54.00 24.00 56.00 26.00 ; - RECT 54.00 19.00 56.00 21.00 ; - RECT 54.00 14.00 56.00 16.00 ; - END - END i1 - PIN i7 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i7 - PIN i6 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i6 - PIN i5 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i5 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END i4 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 77.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 77.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 78.50 41.00 ; - END -END oa2a2a2a24_x4 - -MACRO oa2ao222_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 50.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 44.00 39.00 46.00 41.00 ; - RECT 44.00 34.00 46.00 36.00 ; - RECT 44.00 29.00 46.00 31.00 ; - RECT 44.00 24.00 46.00 26.00 ; - RECT 44.00 19.00 46.00 21.00 ; - RECT 44.00 14.00 46.00 16.00 ; - RECT 44.00 9.00 46.00 11.00 ; - END - END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - END - END i4 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i2 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END i3 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 47.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 47.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 48.50 41.00 ; - END -END oa2ao222_x2 - -MACRO oa2ao222_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 55.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 44.00 39.00 46.00 41.00 ; - RECT 44.00 34.00 46.00 36.00 ; - RECT 44.00 29.00 46.00 31.00 ; - RECT 44.00 24.00 46.00 26.00 ; - RECT 44.00 19.00 46.00 21.00 ; - RECT 44.00 14.00 46.00 16.00 ; - RECT 44.00 9.00 46.00 11.00 ; - END - END q - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - END - END i3 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i2 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - END - END i4 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 52.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 52.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 53.50 41.00 ; - END -END oa2ao222_x4 - -MACRO oa3ao322_x2 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 55.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 39.00 6.00 41.00 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - RECT 4.00 9.00 6.00 11.00 ; - END - END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - END - END i0 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 44.00 34.00 46.00 36.00 ; - RECT 44.00 29.00 46.00 31.00 ; - RECT 44.00 24.00 46.00 26.00 ; - RECT 44.00 19.00 46.00 21.00 ; - RECT 44.00 14.00 46.00 16.00 ; - END - END i4 - PIN i5 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 49.00 34.00 51.00 36.00 ; - RECT 49.00 29.00 51.00 31.00 ; - RECT 49.00 24.00 51.00 26.00 ; - RECT 49.00 19.00 51.00 21.00 ; - RECT 49.00 14.00 51.00 16.00 ; - END - END i5 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - END - END i3 - PIN i6 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - END - END i6 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - END - END i2 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 52.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 52.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 53.50 41.00 ; - END -END oa3ao322_x2 - -MACRO oa3ao322_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 60.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END q - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END i1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - END - END i2 - PIN i6 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 34.00 36.00 36.00 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - END - END i6 - PIN i4 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 49.00 34.00 51.00 36.00 ; - RECT 49.00 29.00 51.00 31.00 ; - RECT 49.00 24.00 51.00 26.00 ; - RECT 49.00 19.00 51.00 21.00 ; - RECT 49.00 14.00 51.00 16.00 ; - END - END i4 - PIN i5 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 54.00 34.00 56.00 36.00 ; - RECT 54.00 29.00 56.00 31.00 ; - RECT 54.00 24.00 56.00 26.00 ; - RECT 54.00 19.00 56.00 21.00 ; - RECT 54.00 14.00 56.00 16.00 ; - END - END i5 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i0 - PIN i3 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 44.00 34.00 46.00 36.00 ; - RECT 44.00 29.00 46.00 31.00 ; - RECT 44.00 24.00 46.00 26.00 ; - RECT 44.00 19.00 46.00 21.00 ; - RECT 44.00 14.00 46.00 16.00 ; - END - END i3 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 57.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 57.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 58.50 41.00 ; - END -END oa3ao322_x4 - -MACRO on12_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 25.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 39.00 21.00 41.00 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - RECT 19.00 24.00 21.00 26.00 ; - RECT 19.00 19.00 21.00 21.00 ; - RECT 19.00 14.00 21.00 16.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i1 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 22.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 22.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 23.50 41.00 ; - END -END on12_x1 - -MACRO on12_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 40.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 39.00 31.00 41.00 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - RECT 29.00 9.00 31.00 11.00 ; - END - END q - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i0 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 39.00 26.00 41.00 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END i1 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 37.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 37.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 38.50 41.00 ; - END -END on12_x4 - -MACRO one_x0 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 15.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END q - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 12.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 12.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 13.50 41.00 ; - END -END one_x0 - -MACRO powmid_x0 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 35.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 32.00 47.00 ; - LAYER ALU3 ; - WIDTH 12.00 ; - PATH 10.00 6.00 10.00 44.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 32.00 3.00 ; - LAYER ALU3 ; - WIDTH 12.00 ; - PATH 25.00 6.00 25.00 44.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 33.50 41.00 ; - LAYER ALU2 ; - RECT 4.00 49.00 16.00 51.00 ; - RECT 19.00 -1.00 31.00 1.00 ; - END -END powmid_x0 - -MACRO rowend_x0 - CLASS CORE FEEDTHRU ; - ORIGIN 0.00 0.00 ; - SIZE 5.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 2.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 2.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 3.50 41.00 ; - END -END rowend_x0 - -MACRO sff1_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 90.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 79.00 39.00 81.00 41.00 ; - RECT 79.00 34.00 81.00 36.00 ; - RECT 79.00 29.00 81.00 31.00 ; - RECT 79.00 24.00 81.00 26.00 ; - RECT 79.00 19.00 81.00 21.00 ; - RECT 79.00 14.00 81.00 16.00 ; - RECT 79.00 9.00 81.00 11.00 ; - END - END q - PIN i - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - LAYER ALU1 ; - RECT 29.00 39.00 31.00 41.00 ; - LAYER ALU1 ; - RECT 29.00 9.00 31.00 11.00 ; - END - END i - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 87.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 87.00 3.00 ; - END - END vss - PIN ck - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END ck - OBS - LAYER ALU1 ; - RECT 1.50 9.00 88.50 41.00 ; - END -END sff1_x4 - -MACRO sff2_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 120.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 109.00 39.00 111.00 41.00 ; - RECT 109.00 34.00 111.00 36.00 ; - RECT 109.00 29.00 111.00 31.00 ; - RECT 109.00 24.00 111.00 26.00 ; - RECT 109.00 19.00 111.00 21.00 ; - RECT 109.00 14.00 111.00 16.00 ; - RECT 109.00 9.00 111.00 11.00 ; - END - END q - PIN cmd - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - END - END cmd - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - RECT 29.00 9.00 31.00 11.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 117.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 117.00 3.00 ; - END - END vss - PIN ck - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER ALU1 ; - RECT 44.00 34.00 46.00 36.00 ; - RECT 44.00 29.00 46.00 31.00 ; - RECT 44.00 24.00 46.00 26.00 ; - RECT 44.00 19.00 46.00 21.00 ; - RECT 44.00 14.00 46.00 16.00 ; - RECT 44.00 9.00 46.00 11.00 ; - END - END ck - OBS - LAYER ALU1 ; - RECT 1.50 9.00 118.50 41.00 ; - END -END sff2_x4 - -MACRO sff3_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 140.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 129.00 39.00 131.00 41.00 ; - RECT 129.00 34.00 131.00 36.00 ; - RECT 129.00 29.00 131.00 31.00 ; - RECT 129.00 24.00 131.00 26.00 ; - RECT 129.00 19.00 131.00 21.00 ; - RECT 129.00 14.00 131.00 16.00 ; - RECT 129.00 9.00 131.00 11.00 ; - END - END q - PIN cmd1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 4.00 34.00 6.00 36.00 ; - RECT 4.00 29.00 6.00 31.00 ; - RECT 4.00 24.00 6.00 26.00 ; - RECT 4.00 19.00 6.00 21.00 ; - RECT 4.00 14.00 6.00 16.00 ; - END - END cmd1 - PIN i2 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 24.00 16.00 26.00 ; - END - END i2 - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 24.00 24.00 26.00 26.00 ; - END - END i1 - PIN cmd0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - END - END cmd0 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 19.00 41.00 21.00 ; - LAYER ALU1 ; - RECT 39.00 29.00 41.00 31.00 ; - LAYER ALU1 ; - RECT 44.00 24.00 46.00 26.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 137.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 137.00 3.00 ; - END - END vss - PIN ck - DIRECTION INPUT ; - USE CLOCK ; - PORT - LAYER ALU1 ; - RECT 59.00 34.00 61.00 36.00 ; - RECT 59.00 29.00 61.00 31.00 ; - RECT 59.00 24.00 61.00 26.00 ; - RECT 59.00 19.00 61.00 21.00 ; - RECT 59.00 14.00 61.00 16.00 ; - RECT 59.00 9.00 61.00 11.00 ; - END - END ck - OBS - LAYER ALU1 ; - RECT 1.50 9.00 138.50 41.00 ; - END -END sff3_x4 - -MACRO tie_x0 - CLASS CORE FEEDTHRU ; - ORIGIN 0.00 0.00 ; - SIZE 10.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 7.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 7.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 8.50 41.00 ; - END -END tie_x0 - -MACRO ts_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 50.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT TRISTATE ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END q - PIN cmd - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - END - END cmd - PIN i - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - END - END i - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 47.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 47.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 48.50 41.00 ; - END -END ts_x4 - -MACRO ts_x8 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 65.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT TRISTATE ; - PORT - LAYER ALU1 ; - RECT 24.00 39.00 26.00 41.00 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - RECT 24.00 9.00 26.00 11.00 ; - END - END q - PIN cmd - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 29.00 39.00 31.00 41.00 ; - RECT 29.00 34.00 31.00 36.00 ; - RECT 29.00 29.00 31.00 31.00 ; - RECT 29.00 24.00 31.00 26.00 ; - RECT 29.00 19.00 31.00 21.00 ; - RECT 29.00 14.00 31.00 16.00 ; - RECT 29.00 9.00 31.00 11.00 ; - END - END cmd - PIN i - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 54.00 34.00 56.00 36.00 ; - RECT 54.00 29.00 56.00 31.00 ; - RECT 54.00 24.00 56.00 26.00 ; - RECT 54.00 19.00 56.00 21.00 ; - RECT 54.00 14.00 56.00 16.00 ; - END - END i - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 62.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 62.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 63.50 41.00 ; - END -END ts_x8 - -MACRO xr2_x1 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 45.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 19.00 9.00 21.00 11.00 ; - LAYER ALU1 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; - RECT 14.00 9.00 16.00 11.00 ; - LAYER ALU1 ; - RECT 19.00 34.00 21.00 36.00 ; - RECT 19.00 29.00 21.00 31.00 ; - END - END q - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 39.00 36.00 41.00 ; - RECT 34.00 34.00 36.00 36.00 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - RECT 34.00 9.00 36.00 11.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 42.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 42.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 43.50 41.00 ; - END -END xr2_x1 - -MACRO xr2_x4 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 60.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 49.00 39.00 51.00 41.00 ; - RECT 49.00 34.00 51.00 36.00 ; - RECT 49.00 29.00 51.00 31.00 ; - RECT 49.00 24.00 51.00 26.00 ; - RECT 49.00 19.00 51.00 21.00 ; - RECT 49.00 14.00 51.00 16.00 ; - RECT 49.00 9.00 51.00 11.00 ; - END - END q - PIN i1 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 34.00 39.00 36.00 41.00 ; - RECT 34.00 34.00 36.00 36.00 ; - RECT 34.00 29.00 36.00 31.00 ; - RECT 34.00 24.00 36.00 26.00 ; - RECT 34.00 19.00 36.00 21.00 ; - RECT 34.00 14.00 36.00 16.00 ; - END - END i1 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END i0 - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 57.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 57.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 58.50 41.00 ; - END -END xr2_x4 - -MACRO zero_x0 - CLASS CORE ; - ORIGIN 0.00 0.00 ; - SIZE 15.00 BY 50.00 ; - SYMMETRY X Y ; - SITE core ; - PIN nq - DIRECTION OUTPUT ; - PORT - LAYER ALU1 ; - RECT 9.00 39.00 11.00 41.00 ; - RECT 9.00 34.00 11.00 36.00 ; - RECT 9.00 29.00 11.00 31.00 ; - RECT 9.00 24.00 11.00 26.00 ; - RECT 9.00 19.00 11.00 21.00 ; - RECT 9.00 14.00 11.00 16.00 ; - RECT 9.00 9.00 11.00 11.00 ; - END - END nq - PIN vdd - DIRECTION INPUT ; - USE POWER ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 47.00 12.00 47.00 ; - END - END vdd - PIN vss - DIRECTION INPUT ; - USE GROUND ; - SHAPE ABUTMENT ; - PORT - LAYER ALU1 ; - WIDTH 6.00 ; - PATH 3.00 3.00 12.00 3.00 ; - END - END vss - OBS - LAYER ALU1 ; - RECT 1.50 9.00 13.50 41.00 ; - END -END zero_x0 - -END LIBRARY diff --git a/crlcore/src/ccore/openaccess/testParser/CMakeLists.txt b/crlcore/src/ccore/openaccess/testParser/CMakeLists.txt deleted file mode 100755 index fa8d564f..00000000 --- a/crlcore/src/ccore/openaccess/testParser/CMakeLists.txt +++ /dev/null @@ -1,28 +0,0 @@ -PROJECT(testOAWrapper) - -CMAKE_MINIMUM_REQUIRED(VERSION 2.4.0) - -LIST(INSERT CMAKE_MODULE_PATH 0 "$ENV{BOOTSTRAP_TOP}/share/cmake/Modules/") -find_package(Bootstrap REQUIRED) -setup_project_paths(VLSISAPD) -setup_project_paths(CORIOLIS) - -LIST(INSERT CMAKE_MODULE_PATH 0 "${CRLCORE_SOURCE_DIR}/cmake_modules/") - - -LIST(INSERT CMAKE_MODULE_PATH 0 "${CRLCORE_SOURCE_DIR}/cmake_modules/") -LIST(INSERT CMAKE_MODULE_PATH 0 - "$ENV{CHAMS_USER_TOP}/share/cmake/Modules/" - "$ENV{CHAMS_TOP}/share/cmake/Modules/") -print_cmake_module_path() - -FIND_PACKAGE(HURRICANE REQUIRED) -FIND_PACKAGE(CORIOLIS REQUIRED) -FIND_PACKAGE(VLSISAPD REQUIRED) -FIND_PACKAGE(HURRICANEAMS REQUIRED) -FIND_PACKAGE(AMSCORE REQUIRED) -FIND_PACKAGE(Qt4 REQUIRED) # find and setup Qt4 for this project -FIND_PACKAGE(LibXml2 REQUIRED) -FIND_PACKAGE(PythonLibs REQUIRED) - -ADD_SUBDIRECTORY(src) diff --git a/crlcore/src/ccore/openaccess/testParser/Makefile b/crlcore/src/ccore/openaccess/testParser/Makefile deleted file mode 100644 index 50a9650c..00000000 --- a/crlcore/src/ccore/openaccess/testParser/Makefile +++ /dev/null @@ -1,23 +0,0 @@ - -TECHNOFILE= /asim/chams/etc/chams/config.freePDK45.xml -M=$$(uname -m) - -all: compile - -compile: - ./compile.sh - -run: - ./$(M)/usr/local/bin/testOAWrapper \ - "/dsk/l1/misc/caba/OA_BENCHMARKS/NangateOpenCellLibrary_PDKv1_3_v2009_07/openaccess" \ - "NangateOpenCellLibrary" \ - "/dsk/l1/misc/caba/OA_BENCHMARKS/NangateOpenCellLibrary_PDKv1_3_v2009_07/openaccess" \ - "NCSU_FreePDK_45nm" - -mrproper: clean - rm -rf *.log .cadence - -clean: - rm -rf $(M) - -.PHONY: clean mrproper compile all run diff --git a/crlcore/src/ccore/openaccess/testParser/compile.sh b/crlcore/src/ccore/openaccess/testParser/compile.sh deleted file mode 100755 index bcac6239..00000000 --- a/crlcore/src/ccore/openaccess/testParser/compile.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash -ARCH=`uname -m` - -if [ ! -e "./compile.sh" ]; then - echo "You must run compile.sh in its own direcotry : ./compile.sh" - exit 1 -fi - -if [ ! -d "$ARCH/build" ]; then - echo "Creating build directory" - mkdir -p $ARCH/build -fi - -cd $ARCH/build && cmake ../.. && make DESTDIR=.. -j2 install diff --git a/crlcore/src/ccore/openaccess/testParser/src/CMakeLists.txt b/crlcore/src/ccore/openaccess/testParser/src/CMakeLists.txt deleted file mode 100755 index 4c53d292..00000000 --- a/crlcore/src/ccore/openaccess/testParser/src/CMakeLists.txt +++ /dev/null @@ -1,26 +0,0 @@ - -INCLUDE(${QT_USE_FILE}) - -INCLUDE_DIRECTORIES ( ${HURRICANE_INCLUDE_DIR} - ${CORIOLIS_INCLUDE_DIR} - ${HURRICANEAMS_INCLUDE_DIR} - ${HURRICANEAMS_GRAPHICAL_INCLUDE_DIR} - ${AMSCORE_INCLUDE_DIR} - ${SCHEMATIC_SOURCE_DIR}/src - ) - -SET ( CPPS main.cpp ) - -SET(EXECUTABLE_OUTPUT_PATH ${CMAKE_BINARY_DIR}/bin) -ADD_EXECUTABLE(testOAWrapper ${QRCS_SRCS} ${MOCS} ${CPPS} ${QRCS}) -TARGET_LINK_LIBRARIES(testOAWrapper ${HURRICANE_LIBRARIES} - ${HURRICANE_PYTHON_LIBRARIES} - ${OPENCHAMS_LIBRARY} - ${CIF_LIBRARY} - ${AGDS_LIBRARY} - ${CORIOLIS_LIBRARIES} - ${HURRICANEAMS_LIBRARIES} - ${AMSCORE_LIBRARIES} - ${OA_LIBRARIES} ) -INSTALL(TARGETS testOAWrapper DESTINATION bin) - diff --git a/crlcore/src/ccore/openaccess/testParser/src/main.cpp b/crlcore/src/ccore/openaccess/testParser/src/main.cpp deleted file mode 100755 index 65a80355..00000000 --- a/crlcore/src/ccore/openaccess/testParser/src/main.cpp +++ /dev/null @@ -1,60 +0,0 @@ -// -*-compile-command:"cd .. && make"-*- -// x-----------------------------------------------------------------x -// | This file is part of | -// | Copyright (c) UPMC/LIP6 2008-2009, All Rights Reserved | -// | =============================================================== | -// | Author : Jean-Manuel Caba | -// | E-mail : Jean-Manuel.Caba@asim.lip6.fr | -// x-----------------------------------------------------------------x - -#include -#include -#include - -using namespace std; - -#include -#if (QT_VERSION >= QT_VERSION_CHECK(4,5,0)) and not defined (__APPLE__) -# include -#endif -#include "hurricane/DataBase.h" -#include "hurricane/Technology.h" -#include "hurricane/Cell.h" - -#include "hurricane/viewer/Graphics.h" -#include "hurricane/viewer/CellViewer.h" -#include "hurricane/viewer/HApplication.h" - -using namespace Hurricane; - -#include "crlcore/AllianceFramework.h" -#include "crlcore/OAParser.h" -using namespace CRL; - -int main(int argc,char** argv) { - int returnCode=0; - - if(argc!=5) - return -1; - - dbo_ptr af(AllianceFramework::create()); - auto_ptr sys(DataBase::getDB()); - -// Cell* cell = af->getCell("inv_x1", Catalog::State::Views ); - Cell* cell = OAParser(argv[1],argv[2],argv[3],argv[4]).open("INV_X1"); - - auto_ptr qa(new HApplication(argc,argv)); -#if (QT_VERSION >= QT_VERSION_CHECK(4,5,0)) and not defined (__APPLE__) - qa->setStyle(new QGtkStyle()); -#endif - - Graphics::enable(); - auto_ptr blockViewer(new CellViewer()); - blockViewer->setCell(cell); - blockViewer->show(); - - returnCode = qa->exec(); - - cerr << "ending normally ?" << endl; - return returnCode; -}