Disclaimer: This document is still far from complete.
Contents
A symbolic layout is, in practice, made of only of three objects:
+| Object | +mbk | +Explanation | +
|---|---|---|
| Segments | +phseg | +Oriented segments with a width and an orientation. | +
| VIAs & contacts | +phvia | +Boils down to just a point. | +
| Big VIAs & Big Contacts | +phvia | +Point with a width and a height +That is a rectangle of width by height centered +on the VIA coordinates. | +
Each of thoses objects is associated to a symbolic layer which will +control how the object is translated in many real rectangles.
+| mbk | +Layer Name | +Usable By | +Usage | +
|---|---|---|---|
| phseg | +NWELL | +Segment | +N Well | +
| PWELL | +Segment | +P Well | +|
| NDIF | +Segment | +N Diffusion | +|
| PDIF | +Segment | +P Diffusion | +|
| NTIE | +Segment | +N Tie | +|
| PTIE | +Segment | +P Tie | +|
| NTRANS | +Segment | +N transistor, in Alliance, a transistor +is represented as a segment (it's grid). | +|
| PTRANS | +Segment | +P transistor | +|
| POLY | +Segment | +Polysilicium | +|
| ALUx | +Segment | +Metal level x | +|
| CALUx | +Segment | +Metal level x, that can be used by the +upper hierarchical level as a connector. +From the layout point of view it is the +same as ALUx. | +|
| TALUx | +Segment | +Blockage for metal level x. Will +diseappear in the real layout as it is an +information for the P&R tools only. | +|
| phvia | +CONT_BODY_N | +VIA, BIGVIA | +Contact to N Well | +
| CONT_BODY_P | +VIA, BIGVIA | +Contact to P Well | +|
| CONT_DIF_N | +VIA, BIGVIA | +Contact to N Diffusion | +|
| CONT_DIF_P | +VIA, BIGVIA | +Contact to P Diffusion | +|
| CONT_POLY | +VIA, BIGVIA | +Contact to polysilicium | +|
| CONT_VIA | +VIA, BIGVIA | +Contact between metal1 and metal2 | +|
| CONT_VIAx | +VIA, BIGVIA | +Contact between metal x and metal x+1. +The index is the the one of the bottom +metal of the VIA. | +|
| C_X_N | +VIA | +N transistor corner, to build transistor +bend. Not used anymore in recent technos | +|
| C_X_P | +VIA | +P transistor corner, to build transistor +bend. Not used anymore in recent technos | +
Note
+Not all association of object and symbolic layers are meaningful. +For instance you cannot associate a contact to a NTRANS layer.
+Note
+The symbolic layer associated with blockages is prefixed by a T, +for transparency, which may seems silly. It is for historical reasons, +it started as a true transparency, but at some point we had to invert +the meaning (blockage) with the rise of over-the-cell routing, but the +name stuck...
+In Alliance, segments are oriented (up, down, left, right). This disambiguate +the left or right side when using the LCW and RCW rules in the rds file. +It allows to generate, if needed, asymetric object in the real layout file.
+
The RDS file control how a symbolic layout is transformed into it's real conterpart.
RDS file:
DEFINE PHYSICAL_GRID 0.005 @@ -117,7 +1047,7 @@ the LAMBDA value can be any multiple of the fo
The MBK_TO_RDS_SEGMENT table control the way segments are translated into real rectangles. Be aware that we are translating segments and not rectangles. Segments are defined by their axis (source & target points) and their width. @@ -212,7 +1142,7 @@ rectangles).
This table is to translate default VIAs into real via. In the symbolic layout the default VIA is simply a point and a set of layers. All layers are converted in squares shapes centered on the VIA coordinate. The one dimension given is the @@ -246,7 +1176,7 @@ END
In s2r, when generating BIGVIAs, the matrix of holes they contains is not draw relative to the position of the BIGVIA itself, but on a grid which is common througout all the design real layout. This is to allow overlap @@ -255,7 +1185,10 @@ As a consequence, when visualizing the gds fil inside one individual BIGVIA.
The MBK_TO_RDS_BIGVIA_HOLE table define the global hole matrix for the whole design. The first number is the individual hole side and the second the grid step -(center to center).
+(edge to edge). The figure below show the hole generation. +
Example of BIGVIA overlap:
+
Example:
TABLE MBK_TO_RDS_BIGVIA_HOLE @@ -268,10 +1201,17 @@ TABLE MBK_TO_RDS_BIGVIA_HOLE END+
Note
+BIGVIA demotion. If the size of the bigvia is too small, there is +a possibility that no hole from the global matrix will be under it. +To avoid that case, if the either side of the BIGVIA is less than +1.5 * step, the BIGVIA is demoted to a simple VIA.
+This table describe how the metal part of a BIGVIA is expanded (for the hole part, see the previous table MBK_TO_RDS_BIGVIA_HOLE). The rule give for each metal:
@@ -304,7 +1244,7 @@ ENDFrom a strict standpoint this table shouldn't be here but put in a separate configuration file, because it contains informations only used by the symbolic layout tools (ocp, nero, ring).
@@ -341,5 +1281,6 @@ END