In designflow.technos.setupCMOS(), more relaxed clock name pattern.
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@ -69,7 +69,7 @@ def setupCMOS ( checkToolkit=None ):
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Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
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Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
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af = CRL.AllianceFramework.get()
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af = CRL.AllianceFramework.get()
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env = af.getEnvironment()
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env = af.getEnvironment()
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env.setCLOCK( '^ck$|m_clock|^clk$' )
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env.setCLOCK( '^ck$|m_clock|^clk' )
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env.addSYSTEM_LIBRARY( library=(Where.checkToolkit / 'cells' / 'niolib').as_posix()
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env.addSYSTEM_LIBRARY( library=(Where.checkToolkit / 'cells' / 'niolib').as_posix()
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, mode =CRL.Environment.Append )
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, mode =CRL.Environment.Append )
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