From 9b8ea64545523b3415abbe19da2261a822fc1b92 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Fri, 4 Jun 2021 11:28:12 +0200 Subject: [PATCH] Add VHDL "ref" keyword to CRL::NamingScheme. Cleanup BlifParser debug. --- crlcore/src/ccore/blif/BlifParser.cpp | 2 -- crlcore/src/ccore/toolbox/NamingScheme.cpp | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/crlcore/src/ccore/blif/BlifParser.cpp b/crlcore/src/ccore/blif/BlifParser.cpp index 835454ec..441f200e 100644 --- a/crlcore/src/ccore/blif/BlifParser.cpp +++ b/crlcore/src/ccore/blif/BlifParser.cpp @@ -741,8 +741,6 @@ namespace { // cerr << "sm0 plug:" << plug->getMasterNet()->getName() << " => net:" << net->getName() << endl; // } - cerr << "plugNet=" << (void*)plugNet << endl; - cerr << "plug->getMasterNet()=" << (void*)(plug->getMasterNet()) << endl; if (plugNet->isSupply() and not plug->getMasterNet()->isSupply()) { ostringstream message; message << "In " << instance << "\n " diff --git a/crlcore/src/ccore/toolbox/NamingScheme.cpp b/crlcore/src/ccore/toolbox/NamingScheme.cpp index e547cdf9..1f8af188 100644 --- a/crlcore/src/ccore/toolbox/NamingScheme.cpp +++ b/crlcore/src/ccore/toolbox/NamingScheme.cpp @@ -61,6 +61,7 @@ namespace CRL { // VHDL reserved keywords (scalar). if (loweredName == "in" ) return "in_v"; if (loweredName == "out" ) return "out_v"; + if (loweredName == "ref" ) return "ref_v"; if (loweredName == "inout") return "inout_v"; if (loweredName == "true" ) return "bool_true"; if (loweredName == "false") return "bool_false";