From 973cc0f3c3d2cbdd81596041e72cf722f38e4bc0 Mon Sep 17 00:00:00 2001
From: Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
Date: Mon, 7 Dec 2020 16:41:09 +0100
Subject: [PATCH] In LibreSOCIO, allow to choose between complete/abstract
 layout.

* New: In cumulus/plugins.core2chip.libresocio.CoreToChip, use new
    configuration variable "chip.useAbstractpads" to select between the
    abstract version (GPIO, VDD, ...) and the full version (IOPadInOut,
    IOPadVdd, ...) layout.
---
 crlcore/etc/symbolic/cmos/plugins.py          |  1 +
 .../src/plugins/alpha/core2chip/libresocio.py | 34 ++++++++++++++-----
 2 files changed, 27 insertions(+), 8 deletions(-)

diff --git a/crlcore/etc/symbolic/cmos/plugins.py b/crlcore/etc/symbolic/cmos/plugins.py
index 991a4bcd..d443c9bf 100644
--- a/crlcore/etc/symbolic/cmos/plugins.py
+++ b/crlcore/etc/symbolic/cmos/plugins.py
@@ -24,6 +24,7 @@ Cfg.getParamInt   ( "chip.block.rails.hWidth"   ).setInt   ( l( 12) )
 Cfg.getParamInt   ( "chip.block.rails.vWidth"   ).setInt   ( l( 12) )
 Cfg.getParamInt   ( "chip.block.rails.hSpacing" ).setInt   ( l(  6) )
 Cfg.getParamInt   ( "chip.block.rails.vSpacing" ).setInt   ( l(  6) )
+Cfg.getParamBool  ( "chip.useAbstractPads"      ).setBool  ( True )
 Cfg.getParamInt   ( 'clockTree.minimumSide'     ).setInt   ( l(600) )
 Cfg.getParamString( 'clockTree.buffer'          ).setString( 'buf_x2')
 Cfg.getParamString( 'clockTree.placerEngine'    ).setString( 'Etesian')
diff --git a/cumulus/src/plugins/alpha/core2chip/libresocio.py b/cumulus/src/plugins/alpha/core2chip/libresocio.py
index 5d7a4853..5b5af98c 100644
--- a/cumulus/src/plugins/alpha/core2chip/libresocio.py
+++ b/cumulus/src/plugins/alpha/core2chip/libresocio.py
@@ -29,9 +29,10 @@ import re
 from   Hurricane  import DbU, DataBase, UpdateSession, Breakpoint, \
                          Transformation , Instance , Net
 import Viewer     
-from   CRL        import Catalog
-from   CRL        import AllianceFramework
-from   helpers.io import ErrorMessage, WarningMessage
+from   CRL             import Catalog
+from   CRL             import AllianceFramework
+from   helpers.io      import ErrorMessage, WarningMessage
+from   helpers.overlay import CfgCache
 from   plugins.alpha.core2chip.core2chip import CoreToChip as BaseCoreToChip, \
                                                 IoNet, IoPad
 
@@ -43,13 +44,30 @@ class CoreToChip ( BaseCoreToChip ):
     rePadType = re.compile(r'(?P<type>.+)_(?P<index>[\d]+)$')
 
     def __init__ ( self, core ):
+        self.ioPadNames = { 'bidir':'GPIO'
+                          , 'vdd'  :'VDD'
+                          , 'vss'  :'VSS'
+                          , 'iovdd':'IOVDD'
+                          , 'iovss':'IOVSS'
+                          }
+        with CfgCache() as cfg:
+            cfg.chip.useAbstractPads = None
+            if not cfg.chip.useAbstractPads:
+                self.ioPadNames = { 'bidir':'IOPadInOut'
+                                  , 'vdd'  :'IOPadVdd'
+                                  , 'vss'  :'IOPadVss'
+                                  , 'iovdd':'IOPadIOVdd'
+                                  , 'iovss':'IOPadIOVss'
+                                  }
         BaseCoreToChip.__init__ ( self, core )
         self.ringNetNames = { 'iovdd' : None
                             , 'iovss' : None
                             , 'vdd'   : None
                             , 'vss'   : None
                             }
-        self.ioPadInfos   = [ BaseCoreToChip.IoPadInfo( IoPad.BIDIR, 'GPIO', 'pad', ['s', 'd', 'de'] )
+        self.ioPadInfos   = [ BaseCoreToChip.IoPadInfo( IoPad.BIDIR
+                                                      , self.ioPadNames['bidir']
+                                                      , 'pad', ['s', 'd', 'de'] )
                             ]
         self._getPadLib()
         return
@@ -95,7 +113,7 @@ class CoreToChip ( BaseCoreToChip ):
             self.ringNetNames['vss'] = chipNet
         ioPadConf.pads.append( Instance.create( self.chip
                                               , 'p_vss_{}'.format(ioPadConf.index)
-                                              , self.getCell('VSS') ) )
+                                              , self.getCell(self.ioPadNames['vss']) ) )
         self._connect( ioPadConf.pads[0], chipNet, 'vss' )
         self.groundPadCount += 1
         self.chipPads       += ioPadConf.pads
@@ -109,7 +127,7 @@ class CoreToChip ( BaseCoreToChip ):
             self.ringNetNames['iovss'] = padNet
         ioPadConf.pads.append( Instance.create( self.chip
                                               , 'p_iovss_{}'.format(ioPadConf.index)
-                                              , self.getCell('IOVSS') ) )
+                                              , self.getCell(self.ioPadNames['iovss']) ) )
         self._connect( ioPadConf.pads[0], padNet , 'iovss' )
         self.groundPadCount += 1
         self.chipPads       += ioPadConf.pads
@@ -132,7 +150,7 @@ class CoreToChip ( BaseCoreToChip ):
             self.ringNetNames['vdd'] = chipNet
         ioPadConf.pads.append( Instance.create( self.chip
                                               , 'p_vdd_{}'.format(ioPadConf.index)
-                                              , self.getCell('VDD') ) )
+                                              , self.getCell(self.ioPadNames['vdd']) ) )
         self._connect( ioPadConf.pads[0], chipNet, 'vdd' )
         self.powerPadCount += 1
         self.chipPads      += ioPadConf.pads
@@ -146,7 +164,7 @@ class CoreToChip ( BaseCoreToChip ):
             self.ringNetNames['iovdd'] = padNet
         ioPadConf.pads.append( Instance.create( self.chip
                                               , 'p_iovdd_{}'.format(ioPadConf.index)
-                                              , self.getCell('IOVDD') ) )
+                                              , self.getCell(self.ioPadNames['iovdd']) ) )
         self._connect( ioPadConf.pads[0], padNet , 'iovdd' )
         self.powerPadCount += 1
         self.chipPads      += ioPadConf.pads