From 8f69fa668dbdb9034edde6c4b91fc633c689f033 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Tue, 19 Sep 2023 16:01:00 +0200 Subject: [PATCH] More trials on SystemVerilog to Verilog translators. * New: In designflow.surelog, support for the Synlig Surelog/UHDM plugin for Yosys. * Fix: In designflow.svase, remove the transient file "slang-args.txt". * Change: In designflow.yosys, remove the direct SystemVerilog support that is delegated to Surelog and just load the resulting UHDM. Merge with yosysnp and automatically detect if we can load the Python plugin or go through a script. --- cumulus/src/CMakeLists.txt | 1 + cumulus/src/designflow/clean.py | 4 ++ cumulus/src/designflow/surelog.py | 70 +++++++++++++++++++++++++++++++ cumulus/src/designflow/svase.py | 1 + cumulus/src/designflow/yosys.py | 10 +++-- 5 files changed, 83 insertions(+), 3 deletions(-) create mode 100644 cumulus/src/designflow/surelog.py diff --git a/cumulus/src/CMakeLists.txt b/cumulus/src/CMakeLists.txt index 797d56e6..ebfe627e 100644 --- a/cumulus/src/CMakeLists.txt +++ b/cumulus/src/CMakeLists.txt @@ -17,6 +17,7 @@ ${CMAKE_CURRENT_SOURCE_DIR}/designflow/dreal.py ${CMAKE_CURRENT_SOURCE_DIR}/designflow/sv2v.py ${CMAKE_CURRENT_SOURCE_DIR}/designflow/svase.py + ${CMAKE_CURRENT_SOURCE_DIR}/designflow/surelog.py ${CMAKE_CURRENT_SOURCE_DIR}/designflow/yosys.py ${CMAKE_CURRENT_SOURCE_DIR}/designflow/blif2vst.py ${CMAKE_CURRENT_SOURCE_DIR}/designflow/pnr.py diff --git a/cumulus/src/designflow/clean.py b/cumulus/src/designflow/clean.py index e8bdca4d..88134d3b 100644 --- a/cumulus/src/designflow/clean.py +++ b/cumulus/src/designflow/clean.py @@ -1,4 +1,5 @@ +import shutil from pathlib import Path from doit.exceptions import TaskFailed from .task import FlowTask @@ -37,6 +38,9 @@ class Clean ( FlowTask ): if filePath.is_file(): print( ' - {:<40} [removed]'.format( filePath.as_posix() )) filePath.unlink() + elif filePath.is_dir(): + print( ' - {:<40} [removed (directory)]'.format( filePath.as_posix() )) + shutil.rmtree( filePath ) else: print( ' - {}'.format( filePath.as_posix() )) if doExtrasClean and len(self.extrasGlobs): diff --git a/cumulus/src/designflow/surelog.py b/cumulus/src/designflow/surelog.py new file mode 100644 index 00000000..1622fc33 --- /dev/null +++ b/cumulus/src/designflow/surelog.py @@ -0,0 +1,70 @@ + +import os.path +import shutil +import subprocess +from pathlib import Path +from doit.exceptions import TaskFailed +from .task import FlowTask + + +def printCommand ( command ): + commandBin = command[0] + print( commandBin, command[1] ) + for arg in command[2:]: + print( ' '*len(commandBin), arg ) + + +class Surelog ( FlowTask ): + + @staticmethod + def mkRule ( rule, depends, top, incdirs=[], libdirs=[], defines=[], options=[], flags=0 ): + return Surelog( rule, depends, top, incdirs, libdirs, defines, options, flags ) + + def __init__ ( self, rule, depends, top, incdirs, libdirs, defines, options, flags ): + self.flags = flags + self.top = top + self.incdirs = incdirs + self.libdirs = libdirs + self.defines = defines + self.options = options + self.success = True + targets = FlowTask._normFileList( [ self.top + '.uhdm' ] ) + depends = FlowTask._normFileList( depends ) + super().__init__( rule, targets, depends ) + self.addClean( targets ) + + def __repr__ ( self ): + return ''.format( self.main, self.top ) + + @property + def main ( self ): + return self.file_depend( 0 ) + + def doTask ( self ): + from ..helpers.io import ErrorMessage + for incdir in self.incdirs: + if not Path(incdir).is_dir(): + e = ErrorMessage( 1, [ 'Surelog.doTask(): Include directory not found "{}"' + , '"{}"'.format( incdir ) ] ) + return TaskFailed( e ) + command = [ 'surelog', '-parse' ] + command += [ ' '.join( self.options ) ] + command += [ '-D{}'.format(d) for d in self.defines ] + command += [ '-I{}'.format(i) for i in self.incdirs ] + for libdir in self.libdirs: + command += [ '-L', libdir ] + command += [ '-top', self.top ] + command += [ depend.as_posix() for depend in self.depends ] + printCommand( command ) + status = subprocess.call( command ) + if status != 0: return False + shutil.move( 'slpp_all/surelog.uhdm', self.file_target(0) ) + return True + + def create_doit_tasks ( self ): + return { 'basename' : self.basename + , 'actions' : [ self.doTask ] + , 'doc' : 'Run {}.'.format( self ) + , 'file_dep' : self.file_dep + , 'targets' : self.targets + } diff --git a/cumulus/src/designflow/svase.py b/cumulus/src/designflow/svase.py index 432855e3..cf5f27a3 100644 --- a/cumulus/src/designflow/svase.py +++ b/cumulus/src/designflow/svase.py @@ -37,6 +37,7 @@ class Svase ( FlowTask ): #if self.flags & Svase.FlagLog: # self.log = Path( self.top + '.log' ) # targets.append( self.log ) + targets.append( './slang-args.txt' ) super().__init__( rule, targets, depends ) self.addClean( targets ) diff --git a/cumulus/src/designflow/yosys.py b/cumulus/src/designflow/yosys.py index 4890fb9b..312316b0 100644 --- a/cumulus/src/designflow/yosys.py +++ b/cumulus/src/designflow/yosys.py @@ -110,8 +110,12 @@ class Yosys ( FlowTask ): self.success = TaskFailed( e ) return design = Path( design ) - if design.suffix == '.v' : self.script.append( 'read_verilog -sv {}'.format( design.as_posix() )) - elif design.suffix == '.il': self.script.append( 'read_ilang {}'.format( design.as_posix() )) + if design.suffix == '.v' : + self.script.append( 'read_verilog -sv {}'.format( design.as_posix() )) + elif design.suffix == '.il' : self.script.append( 'read_ilang {}'.format( design.as_posix() )) + elif design.suffix == '.uhdm': + self.script.append( 'plugin -i systemverilog' ) + self.script.append( 'read_uhdm {}'.format( design.as_posix() )) else: e = ErrorMessage( 1, 'Yosys._loadDesign(): Unsupported input format for "{}".'.format( design )) self.success = TaskFailed( e ) @@ -193,7 +197,7 @@ class Yosys ( FlowTask ): e = ErrorMessage( 1, [ 'Yosys.doTask(): File not found "{}"' , '"{}"'.format( self.liberty.as_posix() ) ] ) return TaskFailed( e ) - #print( 'Yosys.doTask() on "{}"'.format( self.design )) + #print( 'Yosys.doTask() on "{}"'.format( self.main )) self._loadBlackboxes() if self.flags & Yosys.FlagSystemVerilog: self._loadSVDesign()