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In CRLcore, new gauge "msxlib4" for compliance with AMS 350nm (symbolic). 

* New: In CRL/etc/symbolic/cmos45/kite.conf, new gauge "msxlib4" for both
    routing and cells. Have only 4 metal layers but with all the same pitches
    and width. Differs from the 45nm compliant where pitches double starting
    from METAL4.
* New: In CRL/etc/symbolic/cmos45/plugins.conf, adjust default parameters for
    the clock tree plugin so they are identical to the one of "cmos" (scaling).
* Change: In CRL/python/helpers/io.py, in catch(), do not set up the script
    path here as it is non-informative.
This commit is contained in:
Jean-Paul Chaput 2019-05-29 13:16:01 +02:00
parent 0df4821806
commit 8ad910301d
3 changed files with 11 additions and 8 deletions
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10
crlcore/etc/symbolic/cmos45/kite.conf
View File

@ -52,6 +52,13 @@ routingGaugesTable['msxlib'] = \
, ( 'METAL5' , ( Gauge.Vertical , Gauge.Default, 4, 0.0, l(0), l(20), l(6), l(4), l(8) ) )
, ( 'METAL6' , ( Gauge.Horizontal, Gauge.Default, 5, 0.0, l(0), l(20), l(6), l(4), l(8) ) )
)
routingGaugesTable['msxlib4'] = \
( ( 'METAL1' , ( Gauge.Vertical , Gauge.PinOnly, 0, 0.0, l(0), l(10), l(3), l(2), l(7) ) )
, ( 'METAL2' , ( Gauge.Horizontal, Gauge.Default, 1, 0.0, l(0), l(10), l(3), l(2), l(8) ) )
, ( 'METAL3' , ( Gauge.Vertical , Gauge.Default, 2, 0.0, l(0), l(10), l(3), l(2), l(8) ) )
, ( 'METAL4' , ( Gauge.Horizontal, Gauge.Default, 3, 0.0, l(0), l(10), l(3), l(2), l(8) ) )
)
routingGaugesTable['msxlib-2M'] = \
( ( 'METAL1', ( Gauge.Horizontal, Gauge.Default, 0, 0.0, l(0), l(10), l(3), l(3), l(7) ) )
@ -64,5 +71,6 @@ routingGaugesTable['msxlib-2M'] = \
# ( METAL_PIN, xy_common_pitch, slice_height, slice_step )
cellGaugesTable = {}
cellGaugesTable['msxlib'] = ('metal2', l(10), l(100), l(10))
cellGaugesTable['msxlib' ] = ('metal2', l(10), l(100), l(10))
cellGaugesTable['msxlib4'] = ('metal2', l(10), l(100), l(10))

7
crlcore/etc/symbolic/cmos45/plugins.conf
View File

@ -17,12 +17,7 @@ parametersTable = \
, ("chip.block.rails.vWidth" , TypeInt , l(24) )
, ("chip.block.rails.hSpacing" , TypeInt , l(12) )
, ("chip.block.rails.vSpacing" , TypeInt , l(12) )
, ('chip.pad.pck' , TypeString, 'pck_mpx')
, ('chip.pad.pvddick' , TypeString, 'pvddick_mpx')
, ('chip.pad.pvssick' , TypeString, 'pvssick_mpx')
, ('chip.pad.pvddeck' , TypeString, 'pvddeck_mpx')
, ('chip.pad.pvsseck' , TypeString, 'pvsseck_mpx')
, ('clockTree.minimumSide' , TypeInt , l(1000))
, ('clockTree.minimumSide' , TypeInt , l(1200))
, ('clockTree.buffer' , TypeString, 'buf_x2')
, ('clockTree.placerEngine' , TypeString, 'Etesian')
)

2
crlcore/python/helpers/io.py
View File

@ -221,7 +221,7 @@ def catch ( errorObject ):
else:
em = ErrorMessage( 2, errorObject )
em.trace = traceback.extract_tb( sys.exc_info()[2] )
em.scriptPath = __file__
#em.scriptPath = __file__
if Viewer.Graphics.get().isEnabled():
tryCont = ErrorWidget( em ).exec_()