From 85e969bca92af3b0770579d178717e895672d595 Mon Sep 17 00:00:00 2001
From: Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
Date: Wed, 31 Jul 2019 17:38:35 +0200
Subject: [PATCH] Disable the use of concat '&' in VST port map.

---
 crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp b/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
index 8b410d03..99e1db48 100644
--- a/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
+++ b/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
@@ -153,8 +153,8 @@ namespace Vhdl {
 
   void  VectorPortMap::toVhdlPortMap ( ostream& out, size_t width ) const
   {
+    vector<string>  mappedNames;
     if (getSignal()->isContiguous()) {
-      vector<string>  mappedNames;
       int             begin  = -1;
       int             end    = -1;
       int             delta  =  0;
@@ -220,7 +220,9 @@ namespace Vhdl {
           mappedNames.push_back( bitp->getName() );
         }
       }
+    }
   
+    if (mappedNames.size() == 1) {
       out << setw(width) << left << _signal->getName() << " => ";
   
       size_t lhsWidth  = 90 - tab.getWidth() - width - 4;