In Etesian, set correct direction for buffereds HFNS nets.
* Bug: In Etesian::HFNS::Cluster, all the created nets were systematically created in the IN direction, which is obviously wrong for the driver. Now Slice::raddTransPlug() accept a third argument stating if we are creating a driver or a sink. Direction of the net is now combining and can be IN, OUT or sometimes INOUT. The VHDL files where reflecting that problem and made GHDL choke. * Change: In Etesian::HFNS::Cluster, prefix the instance name by "cmpt_" so it doesn't clash with the signal name in VHDL.
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@ -59,6 +59,9 @@ namespace Etesian {
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// Class : "::Cluster".
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class Cluster {
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public:
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const uint32_t AS_DRIVER = (1<<0);
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const uint32_t AS_SINK = (1<<1);
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public:
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Cluster ( EtesianEngine* );
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virtual ~Cluster ();
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@ -72,8 +75,8 @@ namespace Etesian {
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inline void swapRps ( Cluster* );
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inline Net* getInputNet ();
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inline Net* getOutputNet ();
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Plug* raddTransPlug ( Net* topNet, Path );
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Net* raddTransNet ( Net* topNet, Path );
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Plug* raddTransPlug ( Net* topNet, Path, uint32_t flags );
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Net* raddTransNet ( Net* topNet, Path, uint32_t flags );
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Plug* getPlugByNet ( Instance* instance, Net* cellNet );
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void createInput ( Net* );
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void createOutput ();
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@ -143,7 +146,7 @@ namespace Etesian {
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}
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Plug* Cluster::raddTransPlug ( Net* topNet, Path path )
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Plug* Cluster::raddTransPlug ( Net* topNet, Path path, uint32_t flags )
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{
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if (path.isEmpty()) return NULL;
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if (topNet->getCell() != path.getOwnerCell() ) {
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@ -166,8 +169,11 @@ namespace Etesian {
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if (not masterNet) {
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masterNet = Net::create( masterCell, topNet->getName() );
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masterNet->setType ( topNet->getType() );
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masterNet->setDirection( Net::Direction::IN );
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}
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uint32_t direction = masterNet->getDirection();
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if (flags & AS_DRIVER) direction |= Net::Direction::OUT;
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if (flags & AS_SINK ) direction |= Net::Direction::IN;
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masterNet->setDirection( (Net::Direction::Code)direction );
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masterNet->setExternal( true );
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headPlug = headInstance->getPlug( masterNet );
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@ -182,16 +188,16 @@ namespace Etesian {
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}
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if (not tailPath.isEmpty())
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headPlug = raddTransPlug( masterNet, tailPath );
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headPlug = raddTransPlug( masterNet, tailPath, flags );
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return headPlug;
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}
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Net* Cluster::raddTransNet ( Net* topNet, Path path )
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Net* Cluster::raddTransNet ( Net* topNet, Path path, uint32_t flags )
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{
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if (path.isEmpty()) return topNet;
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return raddTransPlug( topNet, path )->getMasterNet();
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return raddTransPlug( topNet, path, flags )->getMasterNet();
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}
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@ -206,7 +212,7 @@ namespace Etesian {
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if (topCell != cellPnR) {
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inputPath = Path( instancePnR );
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blockNet = raddTransNet( upDriver, inputPath );
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blockNet = raddTransNet( upDriver, inputPath, AS_SINK );
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}
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Plug* inputPlug = bufferDatas->getInput( _buffer );
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inputPlug->setNet( blockNet );
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@ -224,14 +230,16 @@ namespace Etesian {
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Net* blockNet = NULL;
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Path outputPath = Path();
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driverName.insert( 0, "cmpt_" );
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_buffer = Instance::create( cellPnR, driverName, bufferDatas->getCell() );
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getSubNetNames()->nextSubNet();
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_driverNet = Net::create( topCell, driverName );
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_driverNet->setDirection( Net::Direction::OUT );
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if (topCell == cellPnR) blockNet = _driverNet;
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else {
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outputPath = Path( instancePnR );
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blockNet = raddTransNet( _driverNet, outputPath );
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blockNet = raddTransNet( _driverNet, outputPath, AS_DRIVER );
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}
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Plug* outputPlug = bufferDatas->getOutput( _buffer );
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outputPlug->setNet( blockNet );
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@ -247,7 +255,7 @@ namespace Etesian {
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}
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for ( RoutingPad* rp : _rps ) {
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Occurrence plugOcc = rp->getPlugOccurrence();
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Net* deepNet = raddTransNet( _driverNet, plugOcc.getPath() );
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Net* deepNet = raddTransNet( _driverNet, plugOcc.getPath(), AS_SINK );
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if (dynamic_cast<Pin*>(plugOcc.getEntity())) {
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continue;
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}
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@ -333,7 +341,7 @@ namespace Etesian {
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Occurrence driverRpOcc = _rpDriver->getPlugOccurrence();
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_rootNet->destroy();
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_rootNet = Net::create( topCell, topNetName );
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Net* deepDriverNet = raddTransNet( _rootNet, driverRpOcc.getPath() );
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Net* deepDriverNet = raddTransNet( _rootNet, driverRpOcc.getPath(), AS_DRIVER );
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dynamic_cast<Plug*>( driverRpOcc.getEntity() )->setNet( deepDriverNet );
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RoutingPad::create( _rootNet, driverRpOcc, RoutingPad::BiggestArea );
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}
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