* ./stratus:

- Change: Add support for chip-level nets. POWER/GROUND/CLOCK as signals.
    - Bug: Reorder import so that CRL is always imported first so that the
        problem of duplicated type_info RTTI doesn't show.

stratus1/src/stratus/st_instance.py

@@ -48,8 +48,8 @@
 
 
 
-from Hurricane        import *
 import CRL
+from Hurricane        import *
 
 from st_model         import Model, MODELMAP
 from st_getrealmodel  import GetRealModel, InitBV
@@ -79,10 +79,11 @@ DPSXLIB = "dp_.*_x[1-8]"
 ## Class of nets ##
 NET = ( "st_net.SignalIn", "st_net.SignalOut", "st_net.SignalInOut" \
       , "st_net.SignalUnknown", "st_net.TriState" \
-      , "st_net.CkIn" \
+      , "st_net.CkIn", "st_net.SignalCk" \
       , "st_net.Signal", "st_net.Sig" \
       , "st_net.VddIn", "st_net.VssIn" \
-      , "st_net.VddInFromHur", "st_net.VssInFromHur"
+      , "st_net.VddInFromHur", "st_net.VssInFromHur" \
+      , "st_net.SignalVdd" , "st_net.SignalVss" \
       )
 ALIM_NET = ( "st_net.VddIn", "st_net.VssIn" \
            , "st_net.VddInFromHur", "st_net.VssInFromHur"

stratus1/src/stratus/st_model.py

@@ -48,9 +48,9 @@
 
 
 
-from Hurricane  import *
-import Viewer
 import CRL
+import Viewer
+from Hurricane  import *
 
 import re, types, string
 
@@ -379,6 +379,15 @@ class Model :
             net = inst._map[pin]._to_merge[0][0]
             print "       net merged with :", net._name, "with arity :", net._arity
 
+  #############################
+  ##### Find An Instance  #####
+  #############################
+  def getInstance ( self, name ):
+    for instance in self._st_insts:
+      if instance._name == name:
+        return instance
+    return None
+
   #########################
   def PrintGraph ( self ) :
     if  "_graph" not in self.__dict__ :

stratus1/src/stratus/st_net.py

@@ -47,8 +47,8 @@
 # x-----------------------------------------------------------------x
 
 
-from Hurricane   import *
 import CRL
+from Hurricane   import *
 
 from st_model    import Model
 from st_instance import Inst
@@ -1112,6 +1112,16 @@ class CkIn ( net ) :
     
 class CkInFromHur ( net ) :
   def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
+    
+#########################
+# Internal Clock Signal #
+#########################
+class SignalCk ( net ) :
+  def __init__ ( self, nom ) :
+    self.create_net ( nom, 1, direction = "IN", hType = "CLOCK" )
+    
+class SignalCkFromHur ( net ) :
+  def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
         
 ###################
 # Internal Signal #
@@ -1138,6 +1148,16 @@ class VddInFromHur ( net ) :
   def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
 class VssInFromHur ( net ) :
   def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
+
+class SignalVdd ( net ) :
+  def __init__ ( self, nom ) : self.create_net ( nom, 1, direction = "IN", hType = "POWER" )
+class SignalVss ( net ) :
+  def __init__ ( self, nom ) : self.create_net ( nom, 1, direction = "IN", hType = "GROUND" )
+
+class SignalVddFromHur ( net ) :
+  def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
+class SignalVssFromHur ( net ) :
+  def __init__ ( self, hur_net ) : self.create_from_hur ( hur_net )
       
 ##################
 # Virtual signal #