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Keep Sphinx variant documentation sources, just in case...

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Jean-Paul Chaput 2023-01-14 12:45:08 +01:00
parent 0a69e7d62d
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# Minimal makefile for Sphinx documentation
#
# You can set these variables from the command line, and also
# from the environment for the first two.
SPHINXOPTS ?=
SPHINXBUILD ?= sphinx-build
SOURCEDIR = .
BUILDDIR = _build
# Put it first so that "make" without argument is like "make help".
help:
@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
.PHONY: help Makefile
# Catch-all target: route all unknown targets to Sphinx using the new
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
%: Makefile
@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)

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# Configuration file for the Sphinx documentation builder.
#
# This file only contains a selection of the most common options. For a full
# list see the documentation:
# https://www.sphinx-doc.org/en/master/usage/configuration.html
# -- Path setup --------------------------------------------------------------
# If extensions (or modules to document with autodoc) are in another directory,
# add these directories to sys.path here. If the directory is relative to the
# documentation root, use os.path.abspath to make it absolute, like shown here.
#
# import os
# import sys
# sys.path.insert(0, os.path.abspath('.'))
#import site
#sys.path.append( site.getsitepackages()+'breathe' )
# -- Project information -----------------------------------------------------
project = 'Coriolis'
copyright = '2022, Jean-Paul Chaput & Al.'
author = 'Jean-Paul Chaput & Al.'
# The full version, including alpha/beta/rc tags
release = '2.x'
# -- General configuration ---------------------------------------------------
# Add any Sphinx extension module names here, as strings. They can be
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
# ones.
extensions = [ 'breathe'
]
# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
# List of patterns, relative to source directory, that match files and
# directories to ignore when looking for source files.
# This pattern also affects html_static_path and html_extra_path.
exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store', '**/*_HTML.rst']
# -- Options for HTML output -------------------------------------------------
# The theme to use for HTML and HTML Help pages. See the documentation for
# a list of builtin themes.
#
html_theme = 'alabaster'
# Add any paths that contain custom static files (such as style sheets) here,
# relative to this directory. They are copied after the builtin static files,
# so a file named "default.css" will overwrite the builtin "default.css".
html_static_path = ['_static']
breathe_projects = { "Hurricane": "/dsk/l1/jpc/coriolis-2.x/src/coriolis/hurricane/doc/hurricane/xml/" }

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.. -*- Mode: rst; explicit-buffer-name: "definition.rst<documentation/etc>" -*-
.. role:: raw-html(raw)
:format: html
.. role:: raw-latex(raw)
:format: latex
.. role:: ul
.. role:: cb
.. role:: sc
.. role:: fboxtt
.. HTML/LaTeX backends mixed macros.
.. |br| replace:: :raw-latex:`\linebreak` :raw-html:`<br/>`
.. |medskip| replace:: :raw-latex:`\medskip` :raw-html:`<br class="medskip"/>`
.. |newpage| replace:: :raw-latex:`\newpage`
.. |linebreak| replace:: :raw-latex:`\smallskip`
.. |noindent| replace:: :raw-latex:`\noindent` :raw-html:`<p class="noindent"></p>`
.. |dotfill| replace:: :raw-html:`&nbsp;&nbsp;`
.. |bcenter| replace:: :raw-latex:`\begin{center}`
.. |ecenter| replace:: :raw-latex:`\end{center}`
.. |pagestylefancy| replace:: :raw-latex:`\thispagestyle{fancy}`
.. |lambda| replace:: :raw-latex:`$\lambda$` :raw-html:`&#955`
.. Acronyms & names.
.. |NDA| replace:: :sc:`nda`
.. |OS| replace:: :sc:`os`
.. |FOSS| replace:: :sc:`foss`
.. |GNU| replace:: :sc:`gnu`
.. |LGPL| replace:: :sc:`lgpl`
.. |GPL| replace:: :sc:`gpl`
.. |UPMC| replace:: :sc:`upmc`
.. |SorbonneUniversite| replace:: :sc:`Sorbonne Université`
.. |SU| replace:: :sc:`su`
.. |CIAN| replace:: :sc:`cian`
.. |LIP6| replace:: :sc:`lip6`
.. |Bull| replace:: :sc:`Bull`
.. |Cadence| replace:: :sc:`Cadence`
.. |Si2| replace:: :sc:`Si2`
.. |LEFDEF| replace:: :sc:`lefdef`
.. |LEF| replace:: :sc:`lef`
.. |DEF| replace:: :sc:`def`
.. |Flute| replace:: :sc:`Flute`
.. |MacOS| replace:: :sc:`MacOS`
.. |Darwin| replace:: :sc:`Darwin`
.. |RHEL| replace:: :sc:`rhel`
.. |RHEL6| replace:: :sc:`rhel6`
.. |RHEL7| replace:: :sc:`rhel7`
.. |SL6| replace:: :sc:`Scientific Linux 6`
.. |SL7| replace:: :sc:`Scientific Linux 7`
.. |Scientific Linux| replace:: :sc:`Scientific Linux`
.. |CentOS| replace:: :sc:`CentOS`
.. |RedHat| replace:: :sc:`RedHat`
.. |Fedora| replace:: :sc:`Fedora`
.. |FC13| replace:: :sc:`fc13`
.. |EPEL| replace:: :sc:`epel`
.. |Debian| replace:: :sc:`Debian`
.. |Ubuntu| replace:: :sc:`Ubuntu`
.. |MOSIS| replace:: :sc:`mosis`
.. |Blif| replace:: :sc:`blif`
.. |TSMC| replace:: :sc:`tsmc`
.. |AMS| replace:: :sc:`ams`
.. |XFAB| replace:: :sc:`xfab`
.. |XH035| replace:: :cb:`XH035`
.. |ROHM| replace:: :sc:`rohm`
.. |Alexandre| replace:: :sc:`Alexandre`
.. |Belloeil| replace:: :sc:`Belloeil`
.. |Chaput| replace:: :sc:`Chaput`
.. |Chotin| replace:: :sc:`Chotin`
.. |Chu| replace:: :sc:`Chu`
.. |Clement| replace:: :sc:`Clement`
.. |Dupuis| replace:: :sc:`Dupuis`
.. |Escassut| replace:: :sc:`Escassut`
.. |Gouvine| replace:: :sc:`Gouvine`
.. |Masson| replace:: :sc:`Masson`
.. |Sroka| replace:: :sc:`Sroka`
.. |Yifei| replace:: :sc:`Yifei`
.. |Mead| replace:: :sc:`Mead`
.. |Conway| replace:: :sc:`Conway`
.. |Petley| replace:: :sc:`Petley`
.. |FloresGomez| replace:: :sc:`Flores Gomez`
.. |SNX| replace:: :sc:`snx`
.. |ASIC| replace:: :sc:`asic`
.. |EDA| replace:: :sc:`eda`
.. |RTL| replace:: :sc:`rtl`
.. |HSL| replace:: :sc:`hsl`
.. |FHS| replace:: :sc:`fhs`
.. |IEEE| replace:: :sc:`ieee`
.. |ANSI| replace:: :sc:`ansi`
.. |MIPS| replace:: :sc:`mips`
.. |EDI| replace:: :sc:`edi`
.. |Yosys| replace:: :sc:`Yosys`
.. |nMigen| replace:: :sc:`nMigen`
.. |NanoRoute| replace:: :sc:`NanoRoute`
.. |Pharosc| replace:: :sc:`Pharosc`
.. |Am2901| replace:: :sc:`Am2901`
.. |CAIRO| replace:: :sc:`cairo`
.. |CAIRO+| replace:: :sc:`cairo+`
.. |Hurricane| replace:: :sc:`Hurricane`
.. |CRL| replace:: :sc:`crl`
.. |Alliance| replace:: :sc:`Alliance`
.. |StaCS| replace:: :sc:`StaCS`
.. |GenLib| replace:: :sc:`GenLib`
.. |Nero| replace:: :sc:`Nero`
.. |Druc| replace:: :cb:`Druc`
.. |Coloquinte| replace:: :sc:`Coloquinte`
.. |Coriolis| replace:: :sc:`Coriolis`
.. |Coriolis1| replace:: :sc:`Coriolis 1`
.. |Coriolis2| replace:: :sc:`Coriolis 2`
.. |alliance-check-toolkit| replace:: ``alliance-check-toolkit``
.. |VLSISAPD| replace:: :sc:`vlsisapd`
.. |CRLcore| replace:: :sc:`CRLcore`
.. |Cyclop| replace:: :sc:`Cyclop`
.. |Nimbus| replace:: :sc:`Nimbus`
.. |hMetis| replace:: :sc:`hMetis`
.. |Mauka| replace:: :sc:`Mauka`
.. |Etesian| replace:: :sc:`Etesian`
.. |Knik| replace:: :sc:`Knik`
.. |Anabatic| replace:: :sc:`Anabatic`
.. |Katabatic| replace:: :sc:`Katabatic`
.. |Kite| replace:: :sc:`Kite`
.. |Katana| replace:: :sc:`Katana`
.. |Stratus| replace:: :sc:`Stratus`
.. |Stratus1| replace:: :sc:`Stratus1`
.. |Stratus2| replace:: :sc:`Stratus2`
.. |Unicorn| replace:: :sc:`Unicorn`
.. |ccb| replace:: :cb:`ccb`
.. |cgt| replace:: :cb:`cgt`
.. |Chams| replace:: :sc:`Chams`
.. |OpenChams| replace:: :sc:`OpenChams`
.. |API| replace:: :sc:`api`
.. |STL| replace:: :sc:`stl`
.. |XML| replace:: :sc:`xml`
.. |pdf| replace:: :sc:`pdf`
.. |UTF-8| replace:: :sc:`utf-8`
.. |Python| replace:: :sc:`Python`
.. |TCL| replace:: :sc:`tcl`
.. |Linux| replace:: :sc:`Linux`
.. |MacPorts| replace:: :sc:`MacPorts`
.. |devtoolset| replace:: :cb:`devtoolset`
.. |boost| replace:: :cb:`boost`
.. |Qt| replace:: :sc:`qt`
.. |Qwt| replace:: :sc:`qwt`
.. |PyQt| replace:: :sc:`PyQt`
.. |PyQt4| replace:: :sc:`PyQt4`
.. |PyQt5| replace:: :sc:`PyQt5`
.. |UID| replace:: :sc:`uid`
.. |GID| replace:: :sc:`gid`
.. |root| replace:: :cb:`root`
.. |tty| replace:: :cb:`tty`
.. |svn| replace:: :cb:`svn`
.. |git| replace:: :cb:`git`
.. |rpm| replace:: :cb:`rpm`
.. |gdb| replace:: :cb:`gdb`
.. |valgrind| replace:: :cb:`valgrind`
.. |cmake| replace:: :cb:`cmake`
.. |bison| replace:: :cb:`bison`
.. |flex| replace:: :cb:`flex`
.. |struct| replace:: :cb:`struct`
.. |Makefile| replace:: :cb:`Makefile`
.. |KeyUp| replace:: :fboxtt:`Up`
.. |KeyDown| replace:: :fboxtt:`Down`
.. |KeyLeft| replace:: :fboxtt:`Left`
.. |KeyRight| replace:: :fboxtt:`Right`
.. |KeyF| replace:: :fboxtt:`f`
.. |KeyL| replace:: :fboxtt:`l`
.. |KeyG| replace:: :fboxtt:`g`
.. |KeyZ| replace:: :fboxtt:`z`
.. |KeyM| replace:: :fboxtt:`m`
.. |KeyI| replace:: :fboxtt:`i`
.. |KeyK| replace:: :fboxtt:`k`
.. |KeyP| replace:: :fboxtt:`p`
.. |KeyO| replace:: :fboxtt:`o`
.. |KeyW| replace:: :fboxtt:`w`
.. |KeyQ| replace:: :fboxtt:`q`
.. |KeyCapK| replace:: :fboxtt:`K`
.. |KeyCapS| replace:: :fboxtt:`S`
.. |Plus| replace:: :fboxtt:`+`
.. |KeyESC| replace:: :fboxtt:`ESC`
.. |CTRL| replace:: :fboxtt:`CTRL`
.. |CTRL_L| replace:: :fboxtt:`CTRL+L`
.. |CTRL_I| replace:: :fboxtt:`CTRL+I`
.. |CTRL_P| replace:: :fboxtt:`CTRL+P`
.. |CTRL_O| replace:: :fboxtt:`CTRL+O`
.. |CTRL_W| replace:: :fboxtt:`CTRL+W`
.. |CTRL_Q| replace:: :fboxtt:`CTRL+Q`
.. |CTRL_Down| replace:: :fboxtt:`CTRL+Down`
.. |CTRL_Up| replace:: :fboxtt:`CTRL+Up`
.. |CTRL_Left| replace:: :fboxtt:`CTRL+Left`
.. |CTRL_Right| replace:: :fboxtt:`CTRL+Right`
.. URLs
.. _Doxygen: http://www.stack.nl/~dimitri/doxygen/
.. _LaTeX2HTML: http://www.latex2html.org/
.. _FGR: http://vlsicad.eecs.umich.edu/BK/FGR/
.. _Box Router: http://www.cerc.utexas.edu/~thyeros/boxrouter/boxrouter.htm
.. _hMETIS: http://glaros.dtc.umn.edu/gkhome/views/metis
.. _Knik Thesis: http://www-soc.lip6.fr/en/users/damiendupuis/PhD/
.. _RapidJSON: http://miloyip.github.io/rapidjson/
.. _Python/C API Reference Manual: https://docs.python.org/2/c-api/index.html
.. _Apache License, Version 2.0: http://www.apache.org/licences/LICENSE-2.0
.. _FreePDK45: https://www.eda.ncsu.edu/wiki/FreePDK45:Contents
.. _Yosys: http://www.clifford.at/yosys/
.. _GHDL: https://github.com/ghdl/ghdl
.. _Si2: http://www.si2.org/
.. _GPL: http://www.gnu.org/copyleft/gpl.txt
.. _LGPL: https://www.gnu.org/licenses/lgpl-3.0.html
.. _Apache License, Version 2.0: http://www.apache.org/licences/LICENSE-2.0
.. _Tokai University: http://www.u-tokai.ac.jp/international/
.. _Shimizu Lab: http://labo.nshimizu.com/
.. _Smartlabs: http://www.smartlabsinc.com/
.. _Don Bosco University: http://www.udb.edu.sv/
.. _MyCMP: https://www.mycmp.fr/
.. Standard CAO/VLSI Concepts.
.. |netlist| replace:: *netlist*
.. |netlists| replace:: *netlists*
.. |layout| replace:: *layout*
.. |layouts| replace:: *layouts*
.. |VLSI| replace:: :sc:`vlsi`
.. |GDS| replace:: :sc:`gds`
.. |GDSII| replace:: :sc:`gdsii`
.. |CMOS| replace:: :sc:`cmos`
.. |VHDL| replace:: :sc:`vhdl`
.. |NWELL| replace:: :sc:`nwell`
.. |POWER| replace:: :sc:`power`
.. |GROUND| replace:: :sc:`ground`
.. Alliance & MBK Concepts
.. |MBK| replace:: :sc:`mbk`
.. |LOFIG| replace:: :cb:`Lofig`
.. |PHFIG| replace:: :cb:`Phfig`
.. |SxLib| replace:: :sc:`SxLib`
.. |RDS| replace:: :sc:`rds`
.. |s2r| replace:: :cb:`s2r`
.. Hurricane Concepts.
.. |hypernet| replace:: *hypernet*
.. |hypernets| replace:: *hypernets*
.. |Cell| replace:: *Cell*
.. |Rings| replace:: *Rings*
.. |QuadTrees| replace:: *QuadTrees*
.. |Collections| replace:: *Collections*
.. |ap| replace:: :cb:`ap`
.. |vst| replace:: :cb:`vst`
.. |kgr| replace:: :cb:`kgr`
.. |dot_conf| replace:: :cb:`.conf`

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.. Coriolis documentation master file, created by
sphinx-quickstart on Fri Jan 14 15:11:42 2022.
You can adapt this file completely to your liking, but it should at least
contain the root `toctree` directive.
Welcome to Coriolis's documentation!
====================================
.. toctree::
:maxdepth: 2
:caption: Contents:
pages/users-guide/UsersGuide.rst
pages/hurricane/hurricane.rst
.. pages/users-guide/LicenseCredits.rst
pages/users-guide/Configuration.rst
pages/users-guide/Installation.rst
pages/users-guide/DesignFlow.rst
pages/users-guide/ViewerTools.rst
pages/users-guide/Releases.rst
pages/users-guide/ScriptsPlugins.rst
pages/hurricane/hurricane.rst
Indices and tables
==================
* :ref:`genindex`
* :ref:`modindex`
* :ref:`search`

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Hurricane
=========
.. doxygenclass:: Hurricane::Segment
:project: Hurricane
:members:

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.. include:: ../../etc/definitions.rst
Abstract
========
|Coriolis| is a set of tools for |VLSI| backend. It's main features are :
* An analytic placer |Etesian| (based on |Coloquinte|).
* A router |Katana| for digital designs. An extension toward mixed design
is currently under development.
* |Python| fast prototyping capabilities and layout procedural description.
|Coriolis| is a replacement of the |Alliance| place and route tools.
.. This page is only an excerpt form the `Coriolis User's Guide`_ focused on how
.. to get and build the toolchain.

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.. -*- Mode: rst -*-
.. include:: ../../etc/definitions.rst
.. URLs that changes between the various backends.
.. _Coriolis Tools Documentation: file:///usr/share/doc/coriolis2/index.html
.. |CoriolisSoftSchema| image:: ./images/Coriolis-Soft-Schema.png
:alt: Coriolis Software Schematic
:align: middle
:width: 60%
Coriolis Configuration & Initialisation
=======================================
General Software Architecture
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|Coriolis| has been built with respect of the classical paradigm that the
computational intensive parts have been written in C++, and almost
everything else in |Python|. To build the |Python| interface we used
two methods:
* For self-contained modules :cb:`boost::python` (mainly in :cb:`vlsisapd`).
* For all modules based on |Hurricane|, we created our own wrappers due
to very specific requirements such as shared functions between modules
or C++/|Python| secure bi-directional object deletion.
.. note:: **Python Documentation:**
Most of the documentation is related to the C++ API and implemetation of
the tools. However, the |Python| bindings have been created so they
mimic *as closely as possible* the C++ interface, so the documentation
applies to both languages with only minor syntactic changes.
|bcenter| |CoriolisSoftSchema| |ecenter|
Configuration & User's Settings
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
All configurations files are shipped under the form of |Python| modules.
They are to be loaded through ``import`` statements. The user's configuration
files must be put in a ``./coriolis2/`` directory under the working directory.
It must be made a |Python| module so it must contains a ``__init__.py`` file
(kept empty most of the time). And as they are true |Python| files, you may use
in them any valid code you see fit.
If no user configuration files are present, |Coriolis| will use the default
``symbolic.cmos`` technology which matches the |Alliance| symbolic default one.
Contents of the user's configuration directory ``./coriolis2/``:
+----------------------------------+----------------------------------------------+
| File | Contents/Meaning |
+==================================+==============================================+
| :cb:`./coriolis2/__init__.py` | **Mandatory.** Tells |Python| this directory |
| | *is* a module. Can be left empty |
+----------------------------------+----------------------------------------------+
| :cb:`./coriolis2/settings.py` | **Mandatory.** The user's settings, it must |
| | setup the technology intended for use and |
| | perform any configuration variable settings |
+----------------------------------+----------------------------------------------+
| :cb:`./coriolis2/ioring.py` | **Optional.** Define how the I/O pads are to |
| | be placed on the periphery of the chip along |
| | the chip and core sizes |
+----------------------------------+----------------------------------------------+
| :cb:`./coriolis2/katana.py` | **Optional.** Hook file for |Katana|, run |
| | just after the tool has been created for a |
| | ``Cell``. Mostly to setup ``Nets`` to be |
| | traced |
+----------------------------------+----------------------------------------------+
For example, to use |MOSIS| 180nm, you can put in your :cb:`./coriolis2/setting.py`:
.. code-block:: python
# -*- Mode:Python -*-
import node180.scn6m_deep_09
A Comprehensive Example of :cb:`./coriolis2/setting.py`
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. code-block:: python
import os
import Cfg
import Viewer
import CRL
import node180.scn6m_deep_09
from helpers import l, u, n
allianceTop = None
if os.environ.has_key('ALLIANCE_TOP'):
allianceTop = os.environ['ALLIANCE_TOP']
if not os.path.isdir(allianceTop):
allianceTop = None
if not allianceTop: allianceTop = '/soc/alliance'
Cfg.Configuration.pushDefaultPriority( Cfg.Parameter.Priority.UserFile )
Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
cellsTop = allianceTop+'/cells'
# Alliance related settings.
af = CRL.AllianceFramework.get()
env = af.getEnvironment()
env.setSCALE_X ( 100 )
env.setCATALOG ( 'CATAL' )
env.setIN_LO ( 'vst' )
env.setIN_PH ( 'ap' )
env.setOUT_LO ( 'vst' )
env.setOUT_PH ( 'ap' )
env.setPOWER ( 'vdd' )
env.setGROUND ( 'vss' )
env.setCLOCK ( '.*ck.*|.*nck.*' )
env.setBLOCKAGE ( 'blockage[Nn]et.*' )
env.setPad ( '.*_mpx$' )
env.setWORKING_LIBRARY( '.' )
env.addSYSTEM_LIBRARY ( library=cellsTop+'/nsxlib', mode=CRL.Environment.Append )
env.addSYSTEM_LIBRARY ( library=cellsTop+'/mpxlib', mode=CRL.Environment.Append )
# Misc. setting parameters.
Cfg.getParamBool ( 'misc.logMode' ).setBool ( False )
Cfg.getParamBool ( 'misc.verboseLevel1' ).setBool ( True )
Cfg.getParamBool ( 'misc.verboseLevel2' ).setBool ( True )
# P&R related parameters.
Cfg.getParamString ( 'anabatic.routingGauge' ).setString ( 'msxlib4' )
Cfg.getParamString ( 'anabatic.topRoutingLayer' ).setString ( 'METAL4' )
Cfg.getParamInt ( 'katana.hTracksReservedLocal' ).setInt ( 6 )
Cfg.getParamInt ( 'katana.vTracksReservedLocal' ).setInt ( 3 )
Cfg.Configuration.popDefaultPriority()
|noindent| The example above shows the user's configuration file, with all the
available settings for |Alliance| and a small subset for other tools. Some remarks
about this file:
* The ``Cfg.Configuration.pushDefaultPriority()`` and ``Cfg.Configuration.popDefaultPriority()``
statements are there so the value sets by the user will not be overriden by system
ones event if they are setup afterwards. This priority system is introduced so the
various configuration files could be loaded in out of order.
* The ``Viewer.Graphics.setStyle()`` allows you to choose the look of your liking from
the start.
* For |Alliance|, the user does not need to redefine all the settings,
just the one he wants to change. In most of the cases, the ``addSYSTEM_LIBRARY()``,
the ``setWORKING_LIBRARY()`` and the special net names (at this point there is not
much alternatives for the others settings).
* ``addSYSTEM_LIBRARY()`` adds a directory to the library search path.
Each library entry will be added to the search path according to the second parameter:
* :cb:`CRL.Environment::Append`: append to the search path.
* :cb:`CRL.Environment::Prepend`: insert in head of the search path.
* :cb:`CRL.Environment::Replace`: look for a library of the same name and replace
it, whithout changing the search path order. If no library of that name
already exists, it is appended.
A library is identified by its name, this name is the last component of the
path name. For instance: ``/soc/alliance/sxlib`` will be named ``sxlib``.
Implementing the |Alliance| specification, when looking for a |Cell| ``name``,
the system will browse sequentially through the library list and returns
the first |Cell| whose name match.
* For ``setPOWER()``, ``setGROUND()``, ``setCLOCK()`` and ``setBLOCKAGE()`` net names,
a regular expression (|GNU| regexp) is expected.
* For other tools parameters, just use getter and setter according to their types:
+------------------+-----------------------------------------------------------+
| Type | Getter/Setter |
+==================+===========================================================+
| ``Bool`` | ``Cgt.getParamBool('name').setBool( True )`` |
+------------------+-----------------------------------------------------------+
| ``Int`` | ``Cgt.getParamInt('name').setBool( 12 )`` |
+------------------+-----------------------------------------------------------+
| ``Enumerate`` | ``Cgt.getParamEnumerate('name').setBool( 12 )`` |
+------------------+-----------------------------------------------------------+
| ``Double`` | ``Cgt.getParamDouble('name').setDouble( 254.5 )`` |
+------------------+-----------------------------------------------------------+
| ``Percentage`` | ``Cgt.getParamPercentage('name').setPercentage( 75.0 )`` |
+------------------+-----------------------------------------------------------+
| ``String`` | ``Cgt.getParamString('name').setString( 'machin' )`` |
+------------------+-----------------------------------------------------------+
Lists of the configurable parameters of most interest to the user are given in
:ref:`Viewer & Tools`.

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.. -*- Mode: rst -*-
|newpage|
Complete Design Flow & Examples
===============================
While |Coriolis| can be used stand-alone, it is in fact part of a more complete
design flow build upon |Yosys| and |Alliance|. In addition, a set of demos and
examples are supplied in the repository |alliance-check-toolkit|.
* |Yosys| : http://www.clifford.at/yosys/
An |rpm| packaged version is available here:
https://ftp.lip6.fr/pub/linux/distributions/slsoc/soc/7/addons/x86_64/repoview/yosys.html
* Alliance : https://www-soc.lip6.fr/equipe-cian/logiciels/alliance/
* |alliance-check-toolkit| |git| repository:
https://www-soc.lip6.fr/git/alliance-check-toolkit.git/

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.. -*- Mode: rst -*-
Installation
============
.. note::
As the sources are being released, the binary packaging is dropped.
You may still find (very) old versions here: http://asim.lip6.fr/pub/coriolis/2.0 .
In a nutshell, building source consists in pulling the |git| repository then
running the |ccb| installer.
.. note::
The documentation is already generated and commited in the |git| tree.
You may not install the additional prerequisites for the documentation.
By default the documentation is not generated, just installed by |ccb|.
If you really want to re-generate it, add the ``--doc`` flag to |ccb|.
Main building prerequisites:
* cmake
* C++11-capable compiler
* BFD library (provided through ``binutils``).
* RapidJSON_
* python2.7
* boost
* libxml2
* bzip2
* yacc & lex
* Qt 4 or Qt 5
* PyQt 4 or PyQt 5
* Qwt 6
Building documentation prerequisites:
* doxygen
* latex
* python-docutils (for reStructuredText)
* pelican
The following libraries get directly bundled with |Coriolis|:
* LEF/DEF (from Si2_)
* FLUTE (from `Chris C. N. Chu <http://home.eng.iastate.edu/~cnchu/flute.html>`_)
For other distributions, refer to their own packaging system.
Fixed Directory Tree
~~~~~~~~~~~~~~~~~~~~
In order to simplify the work of the |ccb| installer, the source, build
and installation tree is fixed. To successfully compile |Coriolis| you must
follow it exactly. The tree is relative to the home directory of the user
building it (note :fboxtt:`~/` or :fboxtt:`$HOME/`). Only the source
directory needs to be manually created by the user, all others will be
automatically created either by |ccb| or the build system.
+--------------------------------------------------------------------------------------------------------------+
| **Sources** |
+------------------------------+-------------------------------------------------------------------------------+
| | Sources root | | ~/coriolis-2.x/src |
| | **under git** | | ~/coriolis-2.x/src/coriolis |
+------------------------------+-------------------------------------------------------------------------------+
| **Architecture Dependant Build** |
+------------------------------+-------------------------------------------------------------------------------+
| | Linux, SL 7, 64b | | ~/coriolis-2.x/Linux.el7_64/Release.Shared/build/<tool> |
| | Linux, SL 6, 32b | | ~/coriolis-2.x/Linux.slsoc6x/Release.Shared/build/<tool> |
| | Linux, SL 6, 64b | | ~/coriolis-2.x/Linux.slsoc6x_64/Release.Shared/build/<tool> |
| | Linux, Fedora, 64b | | ~/coriolis-2.x/Linux.fc_64/Release.Shared/build/<tool> |
| | Linux, Fedora, 32b | | ~/coriolis-2.x/Linux.fc/Release.Shared/build/<tool> |
| | FreeBSD 8, 32b | | ~/coriolis-2.x/FreeBSD.8x.i386/Release.Shared/build/<tool> |
| | FreeBSD 8, 64b | | ~/coriolis-2.x/FreeBSD.8x.amd64/Release.Shared/build/<tool> |
| | Windows 7, 32b | | ~/coriolis-2.x/Cygwin.W7/Release.Shared/build/<tool> |
| | Windows 7, 64b | | ~/coriolis-2.x/Cygwin.W7_64/Release.Shared/build/<tool> |
| | Windows 8.x, 32b | | ~/coriolis-2.x/Cygwin.W8/Release.Shared/build/<tool> |
| | Windows 8.x, 64b | | ~/coriolis-2.x/Cygwin.W8_64/Release.Shared/build/<tool> |
+------------------------------+-------------------------------------------------------------------------------+
| **Architecture Dependant Install** |
+------------------------------+-------------------------------------------------------------------------------+
| Linux, SL 6, 32b | ~/coriolis-2.x/Linux.slsoc6x/Release.Shared/install/ |
+------------------------------+-------------------------------------------------------------------------------+
| **FHS Compliant Structure under Install** |
+------------------------------+-------------------------------------------------------------------------------+
| | Binaries | | .../install/bin |
| | Libraries (Python) | | .../install/lib |
| | Include by tool | | .../install/include/coriolis2/<project>/<tool> |
| | Configuration files | | .../install/etc/coriolis2/ |
| | Doc, by tool | | .../install/share/doc/coriolis2/en/html/<tool> |
+------------------------------+-------------------------------------------------------------------------------+
.. note:: *Alternate build types:* the ``Release.Shared`` means an optimized build
with shared libraries. But there are also available ``Static`` instead of ``Shared``
and ``Debug`` instead of ``Release`` and any combination of them.
``Static`` does not work because I don't know yet to mix statically linked binaries
and Python modules (which must be dynamic).
Building Coriolis
~~~~~~~~~~~~~~~~~
The actively developed branch
-----------------------------
The **devel_anabatic** branch is now closed and we go back to a more classical
scheme where **master** is the stable version and **devel** the development one.
The |Coriolis| |git| repository is https://gitlab.lip6.fr/vlsi-cad/coriolis.git
.. note::
Again, the **devel_anabatic** branch is now closed. Please revert to **devel**
or **master**.
.. note::
As it is now possible to mix |PyQt| widget with |Coriolis| ones, it is simpler
for us to revert to |Qt| 4 only. Our reference |OS| being |RHEL| 7, there is no
compatible |PyQt5| build compatible with their |Qt| 5 version (we fall short of
one minor, they provides |Qt| 5.9 were we need at least |Qt| 5.10).
.. note::
Under |RHEL| 7 or clones, they upgraded their version of |Qt| 4 (from 4.6 to 4.8)
so the *diagonal line* bug no longer occurs. So we can safely use the default
system |Qt| again.
Installing on |RedHat| or compatible distributions
--------------------------------------------------
1. Install or check that the required prerequisites are installed :
.. code-block:: bash
dummy@lepka:~> yum install -y git cmake bison flex gcc-c++ libstdc++-devel \
binutils-devel \
boost-devel boost-python boost-filesystem \
boost-regex boost-wave \
python-devel libxml2-devel bzip2-devel \
qt-devel
The packages ``qwt`` and ``qwt-devel`` are not provided by any standard repository
(like |EPEL|). You may download them from the
`LIP6 Addons Repository <https://ftp.lip6.fr/pub/linux/distributions/slsoc/soc/7/addons/x86_64/repoview/letter_q.group.html>`_
Then run:
.. code-block:: sh
dummy@lepka:~> yum localinstall -y qwt-6.1.2-4.fc23.x86_64.rpm \
qwt-devel-6.1.2-4.fc23.x86_64.rpm # Qwt for Qt 4.
You may also install them directly (whithout an intermediate download):
.. code-block:: sh
dummy@lepka:~> yum install -y http://ftp.lip6.fr/pub/linux/distributions/slsoc/soc/7/addons/x86_64/RPMS/qwt-6.1.2-4.fc23.x86_64.rpm \
http://ftp.lip6.fr/pub/linux/distributions/slsoc/soc/7/addons/x86_64/RPMS/qwt-devel-6.1.2-4.fc23.x86_64.rpm
2. Install the unpackaged prerequisites. Currently, only RapidJSON_.
.. code-block:: sh
dummy@lepka:~> mkdir -p ~/coriolis-2.x/src/support
dummy@lepka:support> cd ~/coriolis-2.x/src/support
dummy@lepka:support> git clone http://github.com/miloyip/rapidjson
3. Create the source directory and pull the |git| repository:
.. code-block:: sh
dummy@lepka:~> mkdir -p ~/coriolis-2.x/src
dummy@lepka:src> cd ~/coriolis-2.x/src
dummy@lepka:src> git clone https://gitlab.lip6.fr/vlsi-cad/coriolis.git
4. Build & install:
.. code-block:: sh
dummy@lepka:src> cd coriolis
dummy@lepka:coriolis> git checkout devel
dummy@lepka:coriolis> ./bootstrap/ccb.py --project=support \
--project=coriolis \
--make="-j4 install"
.. note::
Pre-generated documentation will get installed by the previous command.
Only if you did made modifications to it you need to regenerate it with:
.. code-block:: sh
dummy@lepka:coriolis> ./bootstrap/ccb.py --project=support \
--project=coriolis \
--doc --make="-j1 install"
We need to perform a separate installation of the documentation because it
does not support to be generated with a parallel build. So we compile & install in a first
stage in ``-j4`` (or whatever) then we generate the documentation in ``-j1``
Under |RHEL6| or clones, you must build using the |devtoolset|, the version is to
be given as argument:
.. code-block:: sh
dummy@lepka:coriolis> ./bootstrap/ccb.py --project=coriolis \
--devtoolset=8 --make="-j4 install"
If you want to use Qt 5 instead of Qt 4, modify the previous steps as follows:
* At **step 1**, do not install the |QT| 4 related development package (``qt4-devel``),
but instead:
.. code-block:: sh
dummy@lepka:~> yum install -y qt5-qtbase-devel qt5-qtsvg-devel # Qt 5.
The package ``qwt-qt5-devel`` and it's dependency ``qwt-qt5`` are not provided
by any standard repository (like |EPEL|). You may download them from the
`LIP6 Addons Repository <https://ftp.lip6.fr/pub/linux/distributions/slsoc/soc/7/addons/x86_64/repoview/letter_q.group.html>`_
Then run:
.. code-block:: sh
dummy@lepka:~> yum localinstall -y qwt-qt5-6.1.2-4.fc23.x86_64.rpm \
qwt-qt5-devel-6.1.2-4.fc23.x86_64.rpm # Qwt for Qt 5.
* At **step 4**, add a ``--qt5`` argument to the ``ccb.py`` command line.
* The |Python| scripts that make use of |PyQt| in ``crlcore`` and ``cumulus`` must be
edited to import ``PyQt5`` instead of ``PtQt4`` (should find a way to automatically
switch between the two of them).
The complete list of |ccb| functionalities can be accessed with the ``--help`` argument.
It also may be run in graphical mode (``--gui``).
Building a Debug Enabled Version
--------------------------------
The ``Release.Shared`` default version of the |Coriolis| is built stripped of symbols
and optimized so that it makes analysing a core dump after a crash difficult. In the
(unlikely) case of a crash, you may want to build, alongside the optimized version,
a debug one which allows forensic examination by |gdb| (or |valgrind| or whatever).
Run again ``ccb.py``, adding the ``--debug`` argument:
.. code-block:: sh
dummy@lepka:coriolis> ./bootstrap/ccb.py --project=support \
--project=coriolis \
--make="-j4 install" --debug
As |cgt| is a |Python| script, the right command to run |gdb| is:
.. code-block:: sh
dummy@lepka:work> gdb python core.XXXX
.. Building the Devel Branch
.. -------------------------
..
.. In the |Coriolis| |git| repository, two branches are present:
..
.. * The :cb:`master` branch, which contains the latest stable version. This is the
.. one used by default if you follow the above instructions.
..
.. * The :cb:`devel` branch, which obviously contains the latest commits from the
.. development team. To use it instead of the :cb:`master` one, do the following
.. command just after the first step: ::
..
.. dummy@lepka:coriolis> git checkout devel
.. dummy@lepka:coriolis> ./bootstrap/ccb.py --project=coriolis \
.. --make="-j4 install" --debug
..
.. Be aware that it may require newer versions of the dependencies and may introduce
.. incompatibilities with the stable version.
|newpage|
Installing on |Debian| 9, |Ubuntu| 18 or compatible distributions
-----------------------------------------------------------------
First, install or check that the required prerequisites are installed:
.. code-block:: sh
dummy@lepka:~> sudo apt-get install -y build-essential binutils-dev \
git cmake bison flex gcc python-dev \
libboost-all-dev libboost-python-dev \
zlib1g-dev libxml2-dev rapidjson-dev libbz2-dev
To use with Qt 4:
.. code-block:: sh
dummy@lepka:~> sudo apt-get install -y qt4-dev-tools libqwt-dev python-qt4
To use with Qt 5:
.. code-block:: sh
dummy@lepka:~> sudo apt-get install -y qtbase5-dev libqt5svg5-dev libqwt-qt5-dev \
python-pyqt5
.. note:: **Do not install both versions of Qwt** (for Qt 4 and Qt 5),
this will confuse the installer and end up with a non functional software
(it uses the headers from one Qt and libraries from the other version).
Second step is to create the source directory and pull the |git| repository:
.. code-block:: sh
dummy@lepka:~> mkdir -p ~/coriolis-2.x/src
dummy@lepka:src> cd ~/coriolis-2.x/src
dummy@lepka:src> git clone https://gitlab.lip6.fr/vlsi-cad/coriolis.git
Third and final step, build & install:
.. code-block:: sh
dummy@lepka:src> cd coriolis
dummy@lepka:coriolis> git checkout devel
dummy@lepka:coriolis> ./bootstrap/ccb.py --project=coriolis \
--make="-j4 install"
Additionnal Requirement under |MacOS|
-------------------------------------
|Coriolis| makes use of the :cb:`boost::python` module, but the |macports| |boost|
seems unable to work with the |Python| bundled with |MacOS|. So you have to install
both of them from |macports|:
.. code-block:: sh
dummy@macos:~> port install boost +python27
dummy@macos:~> port select python python27
dummy@macos:-> export DYLD_FRAMEWORK_PATH=/opt/local/Library/Frameworks
The last two lines tell |MacOS| to use the |Python| from |macports| and *not* from
the system.
Then proceed with the generic install instructions.
|Coriolis| & Docker
~~~~~~~~~~~~~~~~~~~
Under ``bootstrap/docker/`` scripts and configuration files are provided that
allow to rebuild |Alliance| and |Coriolis| and perform the regression tests
of ``alliance-check-toolkit``. You may have a look at the ``Dockerfile.system``
configuration file to see exactly how to setup a vanilla system to build
|Coriolis|.
To run the docker tests, call the ``dockerManage.sh`` scripts with the relevant
arguments:
.. code-block:: sh
ego@home:debian-9> ../../dockerManage.sh -bS # build both system & coriolis images.
ego@home:debian-9> ../../dockerManage.sh -r # compile & check coriolis.
ego@home:debian-9> ../../dockerManage.sh -C # clear the images.
Packaging Coriolis
~~~~~~~~~~~~~~~~~~
Packager should not use |ccb|, instead ``bootstrap/Makefile.package`` is provided
to emulate a top-level ``autotool`` makefile. Just copy it in the root of the
|Coriolis| git repository (``~/corriolis-2.x/src/coriolis/``) and build.
Sligthly outdated packaging configuration files can also be found under ``bootstrap/``:
* ``bootstrap/coriolis2.spec.in`` for |rpm| based distributions.
* ``bootstrap/debian`` for |Debian| based distributions.
Hooking up into |Alliance|
~~~~~~~~~~~~~~~~~~~~~~~~~~
|Coriolis| relies on |Alliance| for the cell libraries. So after installing or
packaging, you must configure it so that it can found those libraries.
The easiest way is to setup the |Alliance| environment (i.e. sourcing
``.../etc/profile.d/alc_env.{sh,csh}``) **before** setting up |Coriolis| environment
(see the next section). To understand how |Coriolis| find/setup |Alliance| you may
have look to the `Alliance Helper`.
Setting up the Environment (coriolisEnv.py)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
To simplify the tedious task of configuring your environment, a helper is provided
in the ``bootstrap`` source directory (also installed in the directory
``.../install/etc/coriolis2/``) :
.. code-block:: sh
~/coriolis-2.x/src/coriolis/bootstrap/coriolisEnv.py
Use it like this:
.. code-block:: sh
dummy@lepka:~> eval `~/coriolis-2.x/src/coriolis/bootstrap/coriolisEnv.py`
.. note:: **Do not call that script in your environement initialisation.**
When used under |RHEL6| or clones, it needs to be run in the |devtoolset|
environement. The script then launch a new shell, which may cause an
infinite loop if it's called again in, say :cb:`~/.bashrc`.
Instead you may want to create an alias:
.. code-block:: sh
alias c2r='eval "`~/coriolis-2.x/src/coriolis/bootstrap/coriolisEnv.py`"'

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.. -*- Mode: rst -*-
Credits & License
=================
.. raw:: html
<table style="border: none; width: 80%; align: center; margin-left: auto; margin-right: auto; font-size: 110%">
<tr>
<td style="text-align: left" ><span><span class="sc">Hurricane</span></span></td>
<td style="text-align: right"><span>Rémy <span class="sc">Escassut</span> &amp;
Christian <span class="sc">Masson</span></span</td>
</tr>
<tr>
<td style="text-align: left" ><span class="left"><span class="sc">Etesian</span></span></td>
<td style="text-align: right"><span class="right">Gabriel <span class="sc">Gouvine</span></span></td>
</tr>
<tr>
<td style="text-align: left" ><span class="left"><span class="sc">Stratus</span></span></td>
<td style="text-align: right"><span class="right">Sophie <span class="sc">Belloeil</span></span></td>
</tr>
<tr>
<td style="text-align: left" ><span class="left"><span class="sc">Katana</span> (global)</span></td>
<td style="text-align: right"><span class="right">Damien <span class="sc">Dupuis</span></span></td>
</tr>
<tr>
<td style="text-align: left" ><span class="left"><span class="sc">Katana</span> (detailed),
<span class="sc">Unicorn</span></span></span></td>
<td style="text-align: right"><span class="right">Jean-Paul <span class="sc">Chaput</span></span></td>
</tr>
</table>
.. raw:: latex
\begin{center}\begin{minipage}[t]{.8\textwidth}
\noindent\DUrole{sc}{Hurricane} \dotfill Rémy \DUrole{sc}{Escassut} \&
Christian \DUrole{sc}{Masson} \\
\noindent\DUrole{sc}{Etesian} \dotfill Gabriel \DUrole{sc}{Gouvine} \\
\noindent\DUrole{sc}{Stratus} \dotfill Sophie \DUrole{sc}{Belloeil} \\
\noindent\DUrole{sc}{Katana} (global) \dotfill Damien \DUrole{sc}{Dupuis} \\
\noindent\DUrole{sc}{Katana} (detailed),
\DUrole{sc}{Unicorn} \dotfill Jean-Paul \DUrole{sc}{Chaput} \\
\end{minipage}\end{center}
|medskip|
The |Hurricane| data-base is copyright© |Bull| 2000-2019 and is
released under the terms of the |LGPL| license. All other tools are
copyright© |UPMC| 2008-2018, |SorbonneUniversite| 2018-2019
and released under the |GPL| license.
Others important contributors to |Coriolis| are Christophe |Alexandre|,
Roselyne |Chotin|, Hugo |Clement|, Marek |Sroka| and Wu |Yifei|.
The |Katana| router makes use of the |Flute| software, which is
copyright© Chris C. N. |Chu| from the Iowa State University
(http://home.eng.iastate.edu/~cnchu/).

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.. -*- Mode: rst -*-
Release Notes
=============
Release 1.0.1475
~~~~~~~~~~~~~~~~
This is the first preliminary release of the |Coriolis2| framework.
This release mainly ships the global router |Knik| and the detailed router
|Kite|. Together they aim to replace the |Alliance| |Nero| router.
Unlike |Nero|, |Kite| is based on an innovating routing modeling and ad-hoc
algorithm. Although it is released under |GPL| license, the source code
will be avalaible later.
|medskip|
|noindent| Contents of this release:
1. A graphical user interface (viewer only).
2. The |Knik| global router.
3. The |Kite| detailed router.
|noindent| Supported input/output formats:
* |Alliance| |vst| (netlist) & |ap| (physical) formats.
* Even if there are some references to the |Cadence| |LEFDEF| format, its
support is not included because it depends on a library only available
to |Si2| affiliated members.
Release 1.0.1963
~~~~~~~~~~~~~~~~
Release 1963 is alpha. All the tools from |Coriolis1| have been ported into
this release.
|noindent| Contents of this release:
#. The |Stratus| netlist capture language (|GenLib| replacement).
#. The |Mauka| placer (still contains bugs).
#. A graphical user interface (viewer only).
#. The |Knik| global router.
#. The |Kite| detailed router.
#. Partially implemented python support for configuration files
(alternative to |XML|).
#. A documentation (imcomplete/obsoleted in |Hurricane|'s case).
Release 1.0.2049
~~~~~~~~~~~~~~~~
Release `2049` is Alpha.
|noindent| Changes of this release:
#. The |Hurricane| documentation is now accurate. Documentation
for the Cell viewer and |CRLcore| has been added.
#. More extensive Python support for all the components of
|Coriolis|.
#. Configuration is now completly migrated under Python.
|XML| loaders can still be used for compatibilty.
#. The |cgt| main has been rewritten in Python.
Release v2.0.1
~~~~~~~~~~~~~~
#. Migrated the repository from |svn| to |git|, and release complete sources.
As a consequence, we drop the distribution packaging support and give
public read-only access to the repository.
#. Deep rewrite of the |Katabatic| database and |Kite| detailed router,
achieve a speedup factor greater than 20...
Release v2.1
~~~~~~~~~~~~
#. Replace the old simulated annealing placer |Mauka| by the analytical placer
|Etesian| and its legalization and detailed placement tools.
#. Added a Blif format parser to process circuits generated by the Yosys and ABC
logic synthetizers.
#. The multiple user defined configuration files are now grouped under
a common hidden (dot) directory ``.coriolis2`` and the file extension
is back from ``.conf`` to ``.py``.
.. #. Under |RHEL7| / |SL7|, there is a known bug in the graphical visualizer.
.. When shifting to the left, the right-half part of the screen gets
.. badly redrawn. Uses |CTRL_L| to refresh. It will be corrected as soon
.. as possible.
Release v2.2
~~~~~~~~~~~~
#. Added JSON import/export of the whole Hurricane DataBase. Two save mode
are supported: *Cell* mode (standalone) or *Blob* mode, which dump the
whole design down and including the standard cells.
Release v2.3
~~~~~~~~~~~~
#. Reverts to a more standard organisation of the branches. **devel_anabatic** is
closed and we go on with **master** (stable version) and **devel**.
#. Makes |Katana| the default global & detailed router. Put |Knik| & |Kite| in the
obsolete menus.
#. Finally makes use of |PyQt4| widgets. Seems to integrate without problems
with the |Coriolis| own |Qt| widget. The drawback is that to build against |Qt| 5
needs adjustement from the user.
#. Improved support for whole chip management. The outer part of the chip containing
the pad is decoupled from the core. This allows to cleanly separate real pads from
the foundry from a symbolic core. But this does not preclude other combinations
as fully symbolic or fully real.
To perform the separation, an intermediate hierarchical level ``corona`` between chip
and core has been introduced.

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.. -*- Mode: rst -*-
.. URLs that changes between the various backends.
.. _Stratus Documentation: file:///usr/share/doc/coriolis2/en/html/stratus/index.html
.. .. |ChipStructure-1| image:: ./images/chip-structure-1.png
.. :alt: Chip Top Structure
.. :align: middle
.. :width: 90%
.. _Python Interface to Coriolis:
|newpage|
Python Interface for |Hurricane| / |Coriolis|
=============================================
The (almost) complete interface of |Hurricane| is exported as a |Python| module
and some part of the other components of |Coriolis| (each one in a separate
module). The interface has been made to mirror as closely as possible the
C++ one, so the C++ doxygen documentation could be used to write code with
either languages.
`Summary of the C++ Documentation <file:../../../index.html>`_
A script could be run directly in text mode from the command line or through
the graphical interface (see `Python Scripts in Cgt`).
Aside for this requirement, the python script can contain anything valid
in |Python|, so don't hesitate to use any package or extention.
Small example of Python/Stratus script:
.. code-block:: python
from Hurricane import *
from Stratus import *
def doSomething ():
# ...
return
def scriptMain ( **kw ):
editor = None
if kw.has_key('editor') and kw['editor']:
editor = kw['editor']
stratus.setEditor( editor )
doSomething()
return
if __name__ == "__main__" :
kw = {}
success = scriptMain( **kw )
shellSuccess = 0
if not success: shellSuccess = 1
sys.exit( shellSuccess )
scriptMain ()
This typical script can be executed in two ways:
#. Run directly as a |Python| script, thanks to the
.. code-block:: python
if __name__ == "__main__" :
part (this is standart |Python|). It is a simple adapter that will
calls :cb:`scriptMain()`.
#. Through |cgt|, either in text or graphical mode. In that case, the
:cb:`scriptMain()` is directly called trough a sub-interpreter.
The arguments of the script are passed through the ``**kw`` dictionnary.
+----------------------+-----------------------------------------------+
| \*\*kw Dictionnary |
+----------------------+-----------------------------------------------+
| Parameter Key/Name | Contents type |
+======================+===============================================+
| ``'cell'`` | A Hurricane cell on which to work. Depending |
| | on the context, it may be ``None``. |
| | For example, when run from |cgt|, it the cell |
| | currently loaded in the viewer, if any. |
+----------------------+-----------------------------------------------+
| ``'editor'`` | The viewer from which the script is run, when |
| | lauched through |cgt|. |
+----------------------+-----------------------------------------------+
Plugins
~~~~~~~
Plugins are |Python| scripts specially crafted to integrate with |cgt|.
Their entry point is a :cb:`scriptMain()` method as described in
`Python Interface to Coriolis`_. They can be called by user scripts
through this method.
Chip Placement
--------------
Automatically perform the placement of a complete chip. This plugin, as well
as the other P&R tools expect a specific top-level hierarchy for the design.
The top-level hierarchy must contains the instances of all the I/O pads and
**exactly one** instance named ``corona`` of an eponym cell ``corona``.
The ``corona`` cell in turn containing the instance of the chip's core model.
The intermediate ``corona`` hierarchical level has been introduced to handle
the possible discoupling between real I/O pads supplied by a foundry and a
symbolic core. So the *chip* level contains only real layout and the corona
and below only symbolic layer.
.. note:: This do not prevent having a design either fully symbolic (pads and core)
or fully real.
.. note:: The ``corona`` also avoid the router to actually have to manage directly
the pads which simplificate it's configuration and accessorily avoid
to have the pads stuffed with blockages.
|bcenter| |ChipStructure-1| |ecenter|
The designer must provide a configuration file that defines the rules for the
placement of the top-level hierarchy (that is, the pads and the core).
This file must be named after the chip's name, by appending ``_ioring.py``
(obviously, it is a |Python| file). For instance if the chip netlist file
is called ``amd2901.vst``, then the configuration file must be named
``amd2901_ioring.vst``.
Example of chip placement configuration file (for ``AM2901``):
.. code-block:: python
from helpers import l, u, n
chip = \
{ 'pads.ioPadGauge' : 'pxlib'
, 'pads.south' : [ 'p_a3' , 'p_a2' , 'p_a1' , 'p_r0'
, 'p_vddick0', 'p_vssick0', 'p_a0' , 'p_i6'
, 'p_i8' , 'p_i7' , 'p_r3' ]
, 'pads.east' : [ 'p_zero' , 'p_i0' , 'p_i1' , 'p_i2'
, 'p_vddeck0', 'p_vsseck0', 'p_q3' , 'p_b0'
, 'p_b1' , 'p_b2' , 'p_b3' ]
, 'pads.north' : [ 'p_noe' , 'p_y3' , 'p_y2' , 'p_y1'
, 'p_y0' , 'p_vddeck1', 'p_vsseck1', 'p_np'
, 'p_ovr' , 'p_cout' , 'p_ng' ]
, 'pads.west' : [ 'p_cin' , 'p_i4' , 'p_i5' , 'p_i3'
, 'p_ck' , 'p_d0' , 'p_d1' , 'p_d2'
, 'p_d3' , 'p_q0' , 'p_f3' ]
, 'core.size' : ( l(1500), l(1500) )
, 'chip.size' : ( l(3000), l(3000) )
, 'chip.clockTree' : True
}
The file must contain *one dictionnary* named ``chip``.
+----------------------+-------------------------------------------------------+
| Chip Dictionnary |
+----------------------+-------------------------------------------------------+
| Parameter Key/Name | Value/Contents type |
+======================+=======================================================+
| ``'pad.ioPadGauge'`` | The routing gauge to use for the pad. Must be given |
| | as it differs from the one used to route standard |
| | inside the core |
+----------------------+-------------------------------------------------------+
| ``'pad.south'`` | Ordered list (left to right) of pad instances names |
| | to put on the south side of the chip |
+----------------------+-------------------------------------------------------+
| ``'pad.east'`` | Ordered list (down to up) of pad instances names |
| | to put on the east side of the chip |
+----------------------+-------------------------------------------------------+
| ``'pad.north'`` | Ordered list (left to right) of pad instances names |
| | to put on the north side of the chip |
+----------------------+-------------------------------------------------------+
| ``'pad.west'`` | Ordered list (down to up) of pad instances names |
| | to put on the west side of the chip |
+----------------------+-------------------------------------------------------+
| ``'core.size'`` | The size of the core (to be used by the placer) |
+----------------------+-------------------------------------------------------+
| ``'chip.size'`` | The size of the whole chip. The sides must be great |
| | enough to accomodate all the pads |
+----------------------+-------------------------------------------------------+
| ``'chip.clockTree'`` | Whether to generate a clock tree or not. This calls |
| | the ClockTree plugin |
+----------------------+-------------------------------------------------------+
Configuration parameters, defaults are defined in ``etc/coriolis2/<STECHNO>/plugins.conf``.
+-----------------------------------+------------------+----------------------------+
| Parameter Identifier | Type | Default |
+===================================+==================+============================+
| **Chip Plugin Parameters** |
+-----------------------------------+------------------+----------------------------+
|``chip.block.rails.count`` | TypeInt | :cb:`5` |
| +------------------+----------------------------+
| | The minimum number of rails around the core |
| | block. Must be odd and suppérior to 5. |
| | One rail for the clock and at least two pairs |
| | of power/grounds |
+-----------------------------------+------------------+----------------------------+
|``chip.block.rails.hWidth`` | TypeInt | :cb:`12` |lambda| |
| +------------------+----------------------------+
| | The horizontal with of the rails |
+-----------------------------------+------------------+----------------------------+
|``chip.block.rails.vWidth`` | TypeInt | :cb:`12` |lambda| |
| +------------------+----------------------------+
| | The vertical with of the rails |
+-----------------------------------+------------------+----------------------------+
|``chip.block.rails.hSpacing`` | TypeInt | :cb:`6` |lambda| |
| +------------------+----------------------------+
| | The spacing, *edge to edge* of two adjacent |
| | horizontal rails |
+-----------------------------------+------------------+----------------------------+
|``chip.block.rails.vSpacing`` | TypeInt | :cb:`6` |lambda| |
| +------------------+----------------------------+
| | The spacing, *edge to edge* of two adjacent |
| | vertical rails |
+-----------------------------------+------------------+----------------------------+
.. note::
If no clock tree is generated, then the clock rail is *not* created.
So even if the requested number of rails ``chip.block.rails.count`` is, say 5,
only four rails (2* ``power``, 2* ``ground``) will be generateds.
Clock Tree
----------
Inserts a clock tree into a block. The clock tree uses the H strategy.
The clock net is splitted into sub-nets, one for each branch of the
tree.
* On **chip** design, the sub-nets are created in the model of the
core block (then trans-hierarchically flattened to be shown at
chip level).
* On **blocks**, the sub nets are created directly in the top block.
* The sub-nets are named according to a simple geometrical scheme.
A common prefix ``ck_htree``, then one postfix by level telling
on which quarter of plane the sub-clock is located:
#. ``_bl``: bottom left plane quarter.
#. ``_br``: bottom right plane quarter.
#. ``_tl``: top left plane quarter.
#. ``_tr``: top right plane quarter.
We can have ``ck_htree_bl``, ``ck_htree_bl_bl``, ``ch_htree_bl_tl`` and so on.
The clock tree plugin works in four steps:
#. Builds the clock tree: creates the top-block abutment box, compute the
required levels of H tree and places the clock buffers.
#. Once the clock buffers are placed, calls the placer (|etesian|) to place
the ordinary standard cells, whithout disturbing clock H-tree buffers.
#. At this point we know the exact positions of all the DFFs, so we can
connect them to the nearest H-tree leaf clock signal.
#. Leaf clock signals that are not connected to any DFFs are removed.
Netlist reorganisation:
* Obviously the top block or chip core model netlist is modified to
contain all the clock sub-nets. The interface is *not* changed.
* If the top block contains instances of other models *and* those models
contain DFFs that get re-connected to the clock sub-nets (from the
top level). Changes both the model netlist and interface to propagate
the relevant clock sub-nets to the instanciated model. The new model
with the added clock signal is renamed with a ``_cts`` suffix.
For example, the sub-block model ``ram.vst`` will become ``ram_cts.vst``.
.. note::
If you are to re-run the clock tree plugin on a netlist, be careful
to erase any previously generated ``_cts`` file (both netlist and
layout: ``rm *_cts.{ap,vst}``). And restart |cgt| to clear its
memory cache.
Configuration parameters, defaults are defined in ``etc/coriolis2/<STECHNO>/plugins.conf``.
+-----------------------------------+------------------+----------------------------+
| Parameter Identifier | Type | Default |
+===================================+==================+============================+
| **ClockTree Plugin Parameters** |
+-----------------------------------+------------------+----------------------------+
|``clockTree.minimumSide`` | TypeInt | :cb:`300` |lambda| |
| +------------------+----------------------------+
| | The minimum size below which the clock tree |
| | will stop to perform quadri-partitions |
+-----------------------------------+------------------+----------------------------+
|``clockTree.buffer`` | TypeString | :cb:`buf_x2` |
| +------------------+----------------------------+
| | The buffer model to use to drive sub-nets |
+-----------------------------------+------------------+----------------------------+
Recursive-Save (RSave)
----------------------
Performs a recursive top down save of all the models from the top cell
loaded in |cgt|. Forces a write of any non-terminal model. This plugin is used
by the clock tree plugin after the netlist clock sub-nets creation.
A Simple Example: AM2901
~~~~~~~~~~~~~~~~~~~~~~~~
To illustrate the capabilities of |Coriolis| tools and |Python| scripting, a small
example, derived from the |Alliance| :cb:`AM2901` is supplied.
This example contains only the synthetized netlists and the :cb:`doChip.py` script
which perform the whole P&R of the design.
You can generate the chip using one of the following method:
#. **Command line mode:** directly run the script:
.. code-block:: sh
dummy@lepka:AM2901> ./doChip -V --cell=amd2901
#. **Graphic mode:** launch |cgt|, load chip netlist ``amd2901`` (the top cell)
then run the |Python| script :cb:`doChip.py`.
.. note::
Between two consecutive run, be sure to erase the netlist/layout generateds:
.. code-block:: sh
dummy@lepka:AM2901> rm *_cts*.vst *.ap

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.. -*- Mode: rst -*-
.. role:: raw-html(raw)
:format: html
.. URLs that changes between the various backends.
.. _Coriolis Tools Documentation: http://coriolis.lip6.fr/
.. _Stratus Documentation: http://coriolis.lip6.fr/pages/stratus-language.html
.. _Here: ../../images/users-guide/UsersGuide.pdf
.. _Coriolis User's Guide: ../../images/users-guide/UsersGuide.pdf
.. For PDF backend
.. |BigMouse| image:: ./images/ComputerMouse.png
:width: 30%
.. |ViewerSnapshot_1| image:: ./images/Viewer-1.png
:alt: Viewer Basic Snapshot
:align: middle
:width: 80%
.. |ControllerSnapshot_1| image:: ./images/Controller-1.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ControllerLook_1| image:: ./images/Controller-Look-1.png
:alt: Controller Look, Snapshot 1
:align: middle
:width: 80%
.. |ControllerFilter_1| image:: ./images/Controller-Filter-1.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ControllerLayersGos_1| image:: ./images/Controller-LayersGos-1.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ControllerNetlist_1| image:: ./images/Controller-Netlist-1.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ViewerNetlist_1| image:: ./images/Viewer-Netlist-1.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ControllerSelection_1| image:: ./images/Controller-Selection-1.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ControllerInspector_1| image:: ./images/Controller-Inspector-1.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ControllerInspector_2| image:: ./images/Controller-Inspector-2.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ControllerInspector_3| image:: ./images/Controller-Inspector-3.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ControllerSettings_1| image:: ./images/Controller-Settings-1.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |Etesian-1| image:: ./images/etesian-1.png
:alt: Etesian Abutment Box
:align: middle
:width: 80%
.. |ChipStructure-1| image:: ./images/chip-structure-1.png
:alt: Chip Top Structure
:align: middle
.. raw:: latex
\newpage
\pagestyle{empty}
\begin{center}
\hfill \includegraphics[height=2.0cm]{../../../etc/images/Logo-LIP6-bleugris}
\hfill \includegraphics[height=1.8cm]{../../../etc/images/Logo-SU}
\hfill \includegraphics[height=2.0cm]{../../../etc/images/Logo-CNRS}
\hfill
\\*[2cm]
\huge \textsc{Sorbonne Université} \\*[1cm]
\huge {\textsc{lip6} Laboratory} \\*[3cm]
\Huge \textbf{\textsc{Coriolis}} \\*[1cm]
\Huge \textbf{User's Guide} \\*[1cm]
\huge {Jean-Paul \textsc{Chaput}} \\
\Large\href{mailto:Jean-Paul.Chaput@lip6.fr}{Jean-Paul.Chaput@lip6.fr}\\*[4cm]
\includegraphics[scale=1.0]{../../../etc/images/logoCC.pdf}
\normalsize
This work is licensed under a \\
Creative Commons Attribution-NonCommercial-ShareALike 4.0 International License. \\
Creative Commons License \href{https://creativecommons.org/licenses/by-nc-sa/4.0/}{creativecommons.org/licenses/by-nc-sa/4.0/}
\end{center}
\newpage
\pagestyle{fancy}
|pagestylefancy|
.. contents::
|newpage|
.. include:: Abstract.rst
.. include:: LicenseCredits.rst
.. include:: DesignFlow.rst
.. include:: Installation.rst
.. include:: ViewerTools.rst
.. .. include:: ScriptsPlugins.rst

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.. -*- Mode: rst -*-
=====================
Coriolis User's Guide
=====================
:slug: users-guide
:date: 2019-12-20 16:00
:Authors: Jean-Paul Chaput
:Contact: <Jean-Paul.Chaput@lip6.fr>
:Version: June 4, 2019 (jpc)
:status: hidden
.. role:: raw-html(raw)
:format: html
.. URLs that changes between the various backends.
.. _Coriolis Tools Documentation: ../documentation.rst
.. _Stratus Documentation: ../stratus/Stratus_HTML.rst
.. _Here: {filename}/pdfs/UsersGuide.pdf
.. _Coriolis User's Guide: {filename}/pdfs/UsersGuide.pdf
.. For HTML backend
.. |BigMouse| image:: {attach}images/ComputerMouse.png
:width: 30%
.. |ViewerSnapshot_1| image:: {attach}images/Viewer-1.png
:alt: Viewer Basic Snapshot
:align: middle
:width: 80%
.. |ControllerSnapshot_1| image:: {attach}images/Controller-1.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ControllerLook_1| image:: {attach}images/Controller-Look-1.png
:alt: Controller Look, Snapshot 1
:align: middle
:width: 80%
.. |ControllerFilter_1| image:: {attach}images/Controller-Filter-1.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ControllerLayersGos_1| image:: {attach}images/Controller-LayersGos-1.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ControllerNetlist_1| image:: {attach}images/Controller-Netlist-1.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ViewerNetlist_1| image:: {attach}images/Viewer-Netlist-1.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ControllerSelection_1| image:: {attach}images/Controller-Selection-1.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ControllerInspector_1| image:: {attach}images/Controller-Inspector-1.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ControllerInspector_2| image:: {attach}images/Controller-Inspector-2.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ControllerInspector_3| image:: {attach}images/Controller-Inspector-3.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |ControllerSettings_1| image:: {attach}images/Controller-Settings-1.png
:alt: Controller Basic Snapshot
:align: middle
:width: 80%
.. |Etesian-1| image:: {attach}images/etesian-1.png
:alt: Etesian Abutment Box
:align: middle
:width: 80%
.. |ChipStructure-1| image:: {attach}images/chip-structure-1.png
:alt: Chip Top Structure
:align: middle
Printable Version of this Document
==================================
`Coriolis User's Guide`_.
.. contents::
:depth: 2
.. include:: ../../../etc/definitions.rst
.. include:: Abstract.rst
.. include:: LicenseCredits.rst
.. include:: DesignFlow.rst
.. include:: Installation.rst
.. include:: ViewerTools.rst
.. .. include:: ScriptsPlugins.rst

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.. -*- Mode: rst -*-
CGT - The Graphical Interface
=============================
The |Coriolis| graphical interface is split up into two windows.
* The **Viewer**, with the following features:
* Basic load/save capabilities.
* Displays the current working cell. Could be empty if the design
is not yet placed.
* Executes Stratus Scripts.
* Menu to run the tools (placement, routage).
Features are detailed in `Viewer & Tools`_.
|ViewerSnapShot_1|
* The **Controller**, which allows to:
* Tweak what is displayed by the *Viewer*. Through the *Look*,
*Filter* and *Layers&Gos* tabs.
* Browse the |netlist| with eponym tab.
* Show the list of selected objects (if any) with *selection*
* Walk through the Database, the Cell or the Selection with *Inspector*.
This is an advanced feature, reserved for experimented users.
* The tab *Settings* which gives access to all the settings.
They are closely related to Configuration & Initialisation.
|bcenter| |ControllerSnapShot_1| |ecenter|
.. _Viewer & Tools:
Viewer & Tools
~~~~~~~~~~~~~~
|Stratus| Netlist Capture
-------------------------
|Stratus| is the replacement for |GenLib| procedural netlist capture language.
It is designed as a set of |Python| classes, and comes with it's own documentation
(`Stratus Documentation`_)
The |Hurricane| Data-Base
-------------------------
The |Alliance| flow is based on the |MBK| data-base, which has one data-structure
for each view. That is, |LOFIG| for the *logical* view and |PHFIG| for the *physical*
view. The place and route tools were responsible for maintaining (or not) the
coherency between views. Reflecting this weak coupling between views, each one
was stored in a separate file with a specific format. The *logical* view is stored
in a |vst| file in |VHDL| format and the *physical* in an |ap| file in an ad-hoc format.
The |Coriolis| flow is based on the |Hurricane| data-base, which has a unified
structure for *logical* and *physical* view. That data structure is the |Cell| object.
The |Cell| can have any state between pure netlist and completly placed and
routed design. Although the memory representation of the views has deeply
changed we still use the |Alliance| files format, but they now really represent
views of the same object. The point is that one must be very careful about
view coherency when going to and from |Coriolis|.
As for the second release, |Coriolis| can be used only for three purposes :
* **Placing a design**, in which case the |netlist| view must be present.
* **Routing a design**, in that case the |netlist|
view and the |layout| view must be present and |layout| view must contain
a placement. Both views must have the same name. When saving the routed design,
it is advised to change the design name otherwise the original unrouted placement
in the |layout| view will be overwritten.
* **Viewing a design**, the |netlist| view must be present, if a |layout|
view is present it still must have the same name but it can be in any
state.
Synthetizing and loading a design
---------------------------------
|Coriolis| supports several file formats. It can load all file format
from the |Alliance| toolchain (.ap for layout, behavioural and structural vhdl .vbe and .vst),
BLIF netlist format as well as benchmark formats from the ISPD contests.
It can be compiled with LEF/DEF support, although it requires acceptance of the SI2 license
and may not be compiled in your version of the software.
Synthesis under Yosys
.....................
You can create a BLIF file from the |Yosys| synthetizer, which can be imported under Coriolis.
Most libraries are specified as a .lib liberty file and a .lef LEF file.
|Yosys| opens most .lib files with minor modifications, but LEF support in Coriolis relies on SI2.
If Coriolis hasn't been compiled against it, the library is given in |Alliance| .ap format.
`Some free libraries <http://vlsitechnology.org>`_ already provide both .ap and .lib files.
Once you have installed a common library under |Yosys| and Coriolis, just synthetize your design
with |Yosys| and import it (as Blif without the extension) under Coriolis to perform place&route.
Synthesis under Alliance
........................
|Alliance| is an older toolchain but has been extensively used for years. Coriolis can import
and write Alliance designs and libraries directly.
Etesian -- Placer
-----------------
The |Etesian| placer is a state of the art (as of 2015) analytical placer. It is
within ``5%`` of other placers' solutions, but is normally a bit worse than ePlace.
This |Coriolis| tool is actually an encapsulation of |Coloquinte| which *is* the placer.
.. note:: *Instance Uniquification:* a same logical instance cannot have
two different placements. So, if you don't supply a placement for it, it will be
uniquified (cloned) and you will see the copy files appears on disk upon saving.
|noindent|
**Hierarchical Placement**
The placement area is defined by the top cell abutment box.
When placing a complete hierarchy, the abutment boxes of the cells (models) other than
the top cell are set identical to the one of the top cell and their instances are
all placed at position ``(0,0,ID)``. That is, all the abutments boxes, whatever the
hierarchical level, define the same area (they are exactly superposed).
We choose this scheme because the placer will see all the instances as virtually
flattened, so they can be placed anywhere inside the top-cell abutment box.
|bcenter| |Etesian-1| |ecenter|
|noindent|
**Computing the Placement Area**
The placement area is computed using the ``etesian.aspectRatio`` and ``etesian.spaceMargin``
parameters only if the top-cell has an empty abutment box. If the top-cell abutment
box has to be set, then it is propagated to all the instances models recursively.
|noindent|
**Reseting the Placement**
Once a placement has been done, the placer cannot reset it (will be implemented
later). To perform a new placement, you must restart |cgt|. In addition, if you
have saved the placement on disk, you must erase any :cb:`.ap` file, which are
automatically reloaded along with the netlist (:cb:`.vst`).
|noindent|
**Limitations**
Etesian supports standard cells and fixed macros. As for the Coriolis 2.1 version,
it doesn't support movable macros, and you must place every macro beforehand.
Timing and routability analysis are not included either, and the returned placement
may be unroutable.
Etesian Configuration Parameters
................................
+-----------------------------------+------------------+----------------------------+
| Parameter Identifier | Type | Default |
+===================================+==================+============================+
| **Etesian Parameters** |
+-----------------------------------+------------------+----------------------------+
|``etesian.aspectRatio`` | TypePercentage | :cb:`100` |
| +------------------+----------------------------+
| | Define the height on width ``H/W`` aspect |
| | ratio, can be comprised between 10 and 1000 |
+-----------------------------------+------------------+----------------------------+
|``etesian.spaceMargin`` | TypePercentage | :cb:`5` |
| +------------------+----------------------------+
| | The extra white space added to the total area |
| | of the standard cells |
+-----------------------------------+------------------+----------------------------+
|``etesian.uniformDensity`` | TypeBool | :cb:`False` |
| +------------------+----------------------------+
| | Whether the cells will be spread envenly |
| | across the area or allowed to form denser |
| | clusters |
+-----------------------------------+------------------+----------------------------+
|``etesian.effort`` | TypeInt | :cb:`2` |
| +------------------+----------------------------+
| | Sets the balance between the speed of the |
| | placer and the solution quality |
+-----------------------------------+------------------+----------------------------+
|``etesian.routingDriven`` | TypeBool | :cb:`False` |
| +------------------+----------------------------+
| | Whether the tool will try routing iterations |
| | and whitespace allocation to improve |
| | routability; to be implemented |
+-----------------------------------+------------------+----------------------------+
|``etesian.graphics`` | TypeInt | :cb:`2` |
| +------------------+----------------------------+
| | How often the display will be refreshed |
| | More refreshing slows the placer. |
| | |
| | * ``1`` shows both upper and lower bounds |
| | * ``2`` only shows lower bound results |
| | * ``3`` only shows the final results |
+-----------------------------------+-----------------------------------------------+
|newpage|
Katana -- Global Router
-----------------------
The quality of |Katana| global routing solutions are equivalent to those of FGR_ 1.0.
For an in-depth description of |Katana| algorithms, you may download the thesis of
D. |Dupuis| avalaible from here~: `Knik Thesis`_ (|Knik| has been rewritten as part
of |Katana|, the algorithms remains essentially the same).
The global router is now deterministic.
Katana -- Detailed Router
-------------------------
|Katana| no longer suffers from the limitations of |Nero|. It can route big designs
as its runtime and memory footprint is almost linear (with respect to the number
of gates). It has successfully routed design of more than `150K` gates.
|medskip|
.. note::
**Slow Layer Assignment.** Most of the time, the layer assignment stage is
fast (less than a dozen seconds), but in some instances it can take more
than a dozen *minutes*. This is a known bug and will be corrected in later
releases.
After each run, |Katana| displays a set of *completion ratios* which must all
be equal to `100%` or (``NNNN+0``) if the detailed routing has been successfull.
In the event of a failure, on a saturated design, you may tweak the three
following configuration parameters:
#. ``katana.hTrackReservedLocal``, the number of track reserved for local routing,
that quantity is substracted from the edge capacities (global routing) to
give a sense of the cluttering inside the GCells.
#. ``katana.vTrackReservedLocal``, same as above.
#. ``etesian.spaceMargin``, increases the free area of the overall design so the
routing density decrease.
The idea is to increase the horizontal and vertical local track reservation until
the detailed router succeeds. But in doing so we make the task of the global router
more and more difficult as the capacity of the edges decreases, and at some point
it will fail too. So this is a balance.
Routing a design is done in four ordered steps:
#. Detailed pre-route :math:`\textbf{P\&R} \rightarrow \textbf{Step by Step} \rightarrow \textbf{Detailed PreRoute}`
#. Global routing :math:`\textbf{P\&R} \rightarrow \textbf{Step by Step} \rightarrow \textbf{Global Route}`
#. Detailed routing :math:`\textbf{P\&R} \rightarrow \textbf{Step by Step} \rightarrow \textbf{Detailed Route}`
#. Finalize routing :math:`\textbf{P\&R} \rightarrow \textbf{Step by Step} \rightarrow \textbf{Finalize Route}`
It is possible to supply to the router a complete wiring for some nets that the user
wants to be routed according to a specific topology. The supplied topology must respect
the building rules of the |Anabatic| database (contacts must be, *terminals*, *turns*, *h-tee*
& *v-tee* only). During the first step :fboxtt:`Detailed Pre-Route` the router will solve
overlaps between the segments, without making any dogleg. If no pre-routed topologies
are present, this step may be ommited. Any net routed at this step is then fixed and
become unmovable for the later stages.
After the detailed routing step the |Katana| data-structure is still active
(the Hurricane wiring is decorated). The finalize step performs the removal of
the |Katana| data-structure, and it is not advisable to save the design before
that step.
You may visualize the density (saturation) of either the edges (global routing)
or the GCells (detailed routing) until the routing is finalized. Special layers appear
to that effect in the `The Layers&Go Tab`_.
Katana Configuration Parameters
...............................
The |Anabatic| parameters control the layer assignment step.
All the defaults value given below are from the default |Alliance| technology
(:cb:`cmos` and :cb:`SxLib` cell gauge/routing gauge).
+-----------------------------------+------------------+----------------------------+
| Parameter Identifier | Type | Default |
+===================================+==================+============================+
| **Anabatic Parameters** |
+-----------------------------------+------------------+----------------------------+
|``anabatic.topRoutingLayer`` | TypeString | :cb:`METAL5` |
| +------------------+----------------------------+
| | Define the highest metal layer that will be |
| | used for routing (inclusive). |
+-----------------------------------+------------------+----------------------------+
|``anabatic.globalLengthThreshold`` | TypeInt | :cb:`1450` |
| +------------------+----------------------------+
| | This parameter is used by a layer assignment |
| | method which is no longer used (did not give |
| | good results) |
+-----------------------------------+------------------+----------------------------+
| ``anabatic.saturateRatio`` | TypePercentage | :cb:`80` |
| +------------------+----------------------------+
| | If ``M(x)`` density is above this ratio, |
| | move up feedthru global segments up from |
| | depth ``x`` to ``x+2`` |
+-----------------------------------+------------------+----------------------------+
| ``anabatic.saturateRp`` | TypeInt | :cb:`8` |
| +------------------+----------------------------+
| | If a GCell contains more terminals |
| | (:cb:`RoutingPad`) than that number, force a |
| | move up of the connecting segments to those |
| | in excess |
+-----------------------------------+------------------+----------------------------+
| **Katana Parameters** |
+-----------------------------------+------------------+----------------------------+
| ``katana.hTracksReservedLocal`` | TypeInt | :cb:`3` |
| +------------------+----------------------------+
| | To take account the tracks needed *inside* a |
| | GCell to build the *local* routing, decrease |
| | the capacity of the edges of the global |
| | router. Horizontal and vertical locally |
| | reserved capacity can be distinguished for |
| | more accuracy. |
+-----------------------------------+------------------+----------------------------+
| ``katana.vTracksReservedLocal`` | TypeInt | :cb:`3` |
| +------------------+----------------------------+
| | cf. ``kite.hTracksReservedLocal`` |
+-----------------------------------+------------------+----------------------------+
| ``katana.eventsLimit`` | TypeInt | :cb:`4000002` |
| +------------------+----------------------------+
| | The maximum number of segment displacements, |
| | this is a last ditch safety against infinite |
| | loop. It's perhaps a little too low for big |
| | designs |
+-----------------------------------+------------------+----------------------------+
| ``katana.ripupCost`` | TypeInt | :cb:`3` |
| +------------------+----------------------------+
| | Differential introduced between two ripup |
| | costs to avoid a loop between two ripped up |
| | segments |
+-----------------------------------+------------------+----------------------------+
| ``katana.strapRipupLimit`` | TypeInt | :cb:`16` |
| +------------------+----------------------------+
| | Maximum number of ripup for *strap* segments |
+-----------------------------------+------------------+----------------------------+
| ``katana.localRipupLimit`` | TypeInt | :cb:`9` |
| +------------------+----------------------------+
| | Maximum number of ripup for *local* segments |
+-----------------------------------+------------------+----------------------------+
| ``katana.globalRipupLimit`` | TypeInt | :cb:`5` |
| +------------------+----------------------------+
| | Maximum number of ripup for *global* segments,|
| | when this limit is reached, triggers topologic|
| | modification |
+-----------------------------------+------------------+----------------------------+
| ``katana.longGlobalRipupLimit`` | TypeInt | :cb:`5` |
| +------------------+----------------------------+
| | Maximum number of ripup for *long global* |
| | segments, when this limit is reached, triggers|
| | topological modification |
+-----------------------------------+------------------+----------------------------+
.. _Python Scripts in Cgt:
Executing Python Scripts in Cgt
-------------------------------
Python/Stratus scripts can be executed either in text or graphical mode.
.. note:: **How Cgt Locates Python Scripts:**
|cgt| uses the Python ``import`` mechanism to load Python scripts.
So you must give the name of your script whithout ``.py`` extension and
it must be reachable through the ``PYTHONPATH``. You may use the
dotted module notation.
A Python/Stratus script must contain a function called ``scriptMain()``
with one optional argument, the graphical editor into which it may be
running (will be set to ``None`` in text mode). The Python interface to
the editor (type: :cb:`CellViewer`) is limited to basic capabilities
only.
Any script given on the command line will be run immediatly *after* the
initializations and *before* any other argument is processed.
For more explanation on Python scripts see `Python Interface to Coriolis`.
Printing & Snapshots
--------------------
Printing or saving into a |pdf| is fairly simple, just use the **File -> Print**
menu or the |CTRL_P| shortcut to open the dialog box.
The print functionality uses exactly the same rendering mechanism as for the
screen, beeing almost *WYSIWYG*. Thus, to obtain the best results it is advisable
to select the ``Coriolis.Printer`` look (in the *Controller*), which uses a
white background and well suited for high resolutions ``32x32`` pixels patterns
There is also two modes of printing selectable through the *Controller*
**Settings -> Misc -> Printer/Snapshot Mode**:
=============== ================= =====================================================
Mode DPI (approx.) Intended Usage
--------------- ----------------- -----------------------------------------------------
**Cell Mode** 150 For single ``Cell`` printing or very small designs.
Patterns will be bigger and more readable.
**Design Mode** 300 For designs (mostly commposed of wires and cells
outlines).
=============== ================= =====================================================
.. note:: *The pdf file size*
Be aware that the generated |pdf| files are indeed only pixmaps.
So they can grew very large if you select paper format above ``A2``
or similar.
|noindent|
Saving into an image is subject to the same remarks as for |pdf|.
Memento of Shortcuts in Graphic Mode
------------------------------------
The main application binary is |cgt|.
+---------------+-------------------+-----------------------------------------------------------+
| Category | Keys | Action |
+===============+===================+===========================================================+
| **Moves** | | |KeyUp|, | Shifts the view in the according direction |
| | |KeyDown| | |
| | | |KeyLeft|, | |
| | |KeyRight| | |
+---------------+-------------------+-----------------------------------------------------------+
| **Fit** | |KeyF| | Fits to the Cell abutment box |
+---------------+-------------------+-----------------------------------------------------------+
| **Refresh** | |CTRL_L| | Triggers a complete display redraw |
+---------------+-------------------+-----------------------------------------------------------+
| **Goto** | |KeyG| | *apperture* is the minimum side of the area |
| | | displayed around the point to go to. It's an |
| | | alternative way of setting the zoom level |
+---------------+-------------------+-----------------------------------------------------------+
| **Zoom** | |KeyZ|, | Respectively zoom by a 2 factor and *unzoom* |
| | |KeyM| | by a 2 factor |
| +-------------------+-----------------------------------------------------------+
| | | |BigMouse| | You can perform a zoom to an area. |
| | | Area Zoom | Define the zoom area by *holding down the left |
| | | mouse button* while moving the mouse. |
+---------------+-------------------+-----------------------------------------------------------+
| **Selection** | | |BigMouse| | You can select displayed objects under an area. |
| | | Area Selection | Define the selection area by *holding down the |
| | | right mouse button* while moving the mouse. |
| +-------------------+-----------------------------------------------------------+
| | | |BigMouse| | You can toggle the selection of one object under |
| | | Toggle Selection| the mouse position by pressing |CTRL| and |
| | | pressing down *the right mouse button*. A popup |
| | | list of what's under the position shows up into |
| | | which you can toggle the selection state of one |
| | | item. |
| +-------------------+-----------------------------------------------------------+
| | |KeyCapS| | Toggle the selection visibility |
+---------------+-------------------+-----------------------------------------------------------+
| **Controller**| |CTRL_I| | Show/hide the controller window. |
| | | |
| | | It's the Swiss Army Knife of the viewer. |
| | | From it, you can fine-control the display and |
| | | inspect almost everything in your design. |
+---------------+-------------------+-----------------------------------------------------------+
| **Rulers** | |KeyK|, | One stroke on |KeyK| enters the ruler mode, in |
| | |KeyESC| | which you can draw one ruler. You can exit the |
| | | ruler mode by pressing |KeyESC|. Once in ruler |
| | | mode, the first click on the *left mouse button* |
| | | sets the ruler's starting point and the second |
| | | click the ruler's end point. The second click |
| | | exits automatically the ruler mode. |
| +-------------------+-----------------------------------------------------------+
| | |KeyCapK| | Clears all the drawn rulers |
+---------------+-------------------+-----------------------------------------------------------+
| **Print** | |CTRL_P| | Currently rather crude. It's a direct copy of |
| | | what's displayed in pixels. So the resulting |
| | | picture will be a little blurred due to |
| | | anti-aliasing mechanism. |
+---------------+-------------------+-----------------------------------------------------------+
| **Open/Close**| |CTRL_O| | Opens a new design. The design name must be |
| | | given without path or extention. |
| +-------------------+-----------------------------------------------------------+
| | |CTRL_W| | Closes the current viewer window, but does not quit |
| | | the application. |
| +-------------------+-----------------------------------------------------------+
| | |CTRL_Q| | `CTRL+Q` quits the application |
| | | (closing all windows). |
+---------------+-------------------+-----------------------------------------------------------+
| **Hierarchy** | |CTRL_Down| | Goes one hierarchy level down. That is, if there |
| | | is an *instance* under the cursor position, loads |
| | | its *model* Cell in place of the current one. |
| +-------------------+-----------------------------------------------------------+
| | |CTRL_Up| | Goes one hierarchy level up. If we have entered |
| | | the current model through |CTRL_Down| |
| | | reloads the previous model (the one |
| | | in which this model is instanciated). |
+---------------+-------------------+-----------------------------------------------------------+
Cgt Command Line Options
------------------------
Appart from the obvious ``--text`` options, all can be used for text and graphical mode.
+-----------------------------+------------------------------------------------+
| Arguments | Meaning |
+=============================+================================================+
| `-t|--text` | Instructs |cgt| to run in text mode. |
+-----------------------------+------------------------------------------------+
| `-L|--log-mode` | Disables the use of |ANSI| escape sequence on |
| | the |tty|. Useful when the output is |
| | redirected to a file. |
+-----------------------------+------------------------------------------------+
| `-c <cell>|--cell=<cell>` | The name of the design to load, without |
| | leading path or extention. |
+-----------------------------+------------------------------------------------+
| `-m <val>|--margin=<val>` | Percentage *val* of white space for the placer |
| | (|Etesian|). |
+-----------------------------+------------------------------------------------+
| `--events-limit=<count>` | The maximal number of events after which the |
| | router will stop. This is mainly a failsafe |
| | against looping. The limit is set to 4 |
| | millions of iteration which should suffice to |
| | any design of `100K`. gates. For bigger |
| | designs you may want to increase this limit. |
+-----------------------------+------------------------------------------------+
| `-G|--global-route` | Runs the global router (|Katana|). |
+-----------------------------+------------------------------------------------+
| `-R|--detailed-route` | Runs the detailed router (|Katana|). |
+-----------------------------+------------------------------------------------+
| `-s|--save-design=<routed>` | The design into which the routed layout will |
| | be saved. It is strongly recommanded to choose |
| | a different name from the source (unrouted) |
| | design. |
+-----------------------------+------------------------------------------------+
| `--stratus-script=<module>` | Run the Python/Stratus script ``module``. |
| | See `Python Scripts in Cgt`_. |
+-----------------------------+------------------------------------------------+
|newpage|
Some Examples :
* Run both global and detailed router, then save the routed design:
.. code-block:: sh
> cgt -v -t -G -R --cell=design --save-design=design_r
Miscellaneous Settings
----------------------
+---------------------------------------+------------------+----------------------------+
| Parameter Identifier | Type | Default |
+=======================================+==================+============================+
| **Verbosity/Log Parameters** |
+---------------------------------------+------------------+----------------------------+
| ``misc.info`` | TypeBool | :cb:`False` |
| +------------------+----------------------------+
| | Enables display of *info* level message |
| | (:cb:`cinfo` stream) |
+---------------------------------------+------------------+----------------------------+
| ``misc.bug`` | TypeBool | :cb:`False` |
| +------------------+----------------------------+
| | Enables display of *bug* level message |
| | (:cb:`cbug` stream), messages can be a little |
| | scarry |
+---------------------------------------+------------------+----------------------------+
| ``misc.logMode`` | TypeBool | :cb:`False` |
| +------------------+----------------------------+
| | If enabled, assumes that the output device |
| | is not a ``tty`` and suppresses any escape |
| | sequences |
+---------------------------------------+------------------+----------------------------+
| ``misc.verboseLevel1`` | TypeBool | :cb:`True` |
| +------------------+----------------------------+
| | First level of verbosity, disables level 2 |
+---------------------------------------+------------------+----------------------------+
| ``misc.verboseLevel2`` | TypeBool | :cb:`False` |
| +------------------+----------------------------+
| | Second level of verbosity |
+---------------------------------------+------------------+----------------------------+
| **Development/Debug Parameters** |
+---------------------------------------+------------------+----------------------------+
| ``misc.minTraceLevel`` | TypeInt | :cb:`0` |
+---------------------------------------+------------------+----------------------------+
| ``misc.maxTraceLevel`` | TypeInt | :cb:`0` |
| +------------------+----------------------------+
| | Displays trace information *between* those two|
| | levels (:cb:`cdebug` stream) |
+---------------------------------------+------------------+----------------------------+
| ``misc.catchCore`` | TypeBool | :cb:`False` |
| +------------------+----------------------------+
| | By default, |cgt| does not dump core. |
| | To generate one set this flag to :cb:`True` |
+---------------------------------------+------------------+----------------------------+
|newpage|
.. _The Controller:
The Controller
~~~~~~~~~~~~~~
The *Controller* window is composed of seven tabs:
#. `The Look Tab`_ to select the display style.
#. `The Filter Tab`_ the hierarchical levels to be displayed, the look of
rubbers and the dimension units.
#. `The Layers&Go Tab`_ to selectively hide/display layers.
#. `The Netlist Tab`_ to browse through the |netlist|. Works in association
with the *Selection* tab.
#. `The Selection Tab`_ allows to view all the currently selected elements.
#. `The Inspector Tab`_ browses through either the DataBase, the Cell or
the current selection.
#. `The Settings Tab`_ accesses all the tool's configuration settings.
.. _The Look Tab:
The Look Tab
------------
You can select how the layout will be displayed. There is a special one
``Printer.Coriolis`` specifically designed for `Printing & Snapshots`_.
You should select it prior to calling the print or snapshot dialog boxes.
|bcenter| |ControllerLook_1| |ecenter|
|newpage|
.. _The Filter Tab:
The Filter Tab
--------------
The filter tab let you select what hierarchical levels of your design will be
displayed. Hierarchy level are numbered top-down: the level 0 corresponds to
the top-level cell, the level one to the instances of the top-level Cell and
so on.
There are also check boxes to enable/disable the processing of Terminal Cell,
Master Cells and Components. The processing of Terminal Cell (hierarchy leaf
cells) is disabled by default when you load a hierarchical design and enabled
when you load a single Cell.
You can choose what kind of form to give to the rubbers and the type of
unit used to display coordinates.
.. note:: *What are Rubbers:* |Hurricane| uses *Rubbers* to materialize
physical gaps in net topology. That is, if some wires are missing to
connect two or more parts of net, a *rubber* will be drawn between them
to signal the gap.
For example, after the detailed routing no *rubber* should remain.
They have been made *very* visible as big violet lines...
|bcenter| |ControllerFilter_1| |ecenter|
|newpage|
.. _The Layers&Go Tab:
The Layers&Go Tab
-----------------
Control the individual display of all *layers* and *Gos*.
* *Layers* correspond to true physical layers. From a |Hurricane| point of
view they are all the *BasicLayers* (could be matched to GDSII).
* *Gos* stands from *Graphical Objects*, they are drawings that have no
physical existence but are added by the various tools to display extra
information. One good exemple is the density map of the detailed router,
to easily locate congested areas.
For each layer/Go there are two check boxes:
* The normal one triggers the display.
* The red-outlined allows objects of that layer to be selectable or not.
|bcenter| |ControllerLayersGos_1| |ecenter|
.. _The Netlist Tab:
The Netlist Tab
---------------
The *Netlist* tab shows the list of nets... By default the tab is not
*synched* with the displayed Cell. To see the nets you must check the
**Sync Netlist** checkbox. You can narrow the set of displayed nets by
using the filter pattern (supports regular expressions).
A very useful feature is to enable the **Sync Selection**, which will
automatically select all the components of the selected net(s). You can
select multiple nets. In the figure the net ``auxsc35`` is selected and
is highlighted in the *Viewer*.
|bcenter| |ControllerNetlist_1| |ecenter|
|bcenter| |ViewerNetlist_1| |ecenter|
.. _The Selection Tab:
The Selection Tab
-----------------
The *Selection* tab lists all the components currently selected. They
can be filtered thanks to the filter pattern.
Used in conjunction with the *Netlist* **Sync Selection** you will all see
all the components part of *net*.
In this list, you can toggle individually the selection of component by
pressing the ``t`` key. When unselected in this way a component is not
removed from the the selection list but instead displayed in red italic.
To see where a component is you may make it blink by repeatedly press
the ``t`` key...
|bcenter| |ControllerSelection_1| |ecenter|
.. _The Inspector Tab:
The Inspector Tab
-----------------
This tab is very useful, but mostly for |Coriolis| developpers. It allows
to browse through the live DataBase. The *Inspector* provides three entry points:
* **DataBase**: Starts from the whole |Hurricane| DataBase.
* **Cell**: Inspects the currently loaded Cell.
* **Selection**: Inspects the object currently highlighted in the *Selection* tab.
Once an entry point has been activated, you may recursively expore all
its fields using the right/left arrows.
.. note:: *Do not put your fingers in the socket:* when inspecting
anything, do not modify the DataBase. If any object under inspection
is deleted, you will crash the application...
.. note:: *Implementation Detail:* the inspector support is done with
``Slot``, ``Record`` and ``getString()``.
|bcenter| |ControllerInspector_1| |ecenter|
|bcenter| |ControllerInspector_2| |ecenter|
|bcenter| |ControllerInspector_3| |ecenter|
.. _The Settings Tab:
The Settings Tab
----------------
Here comes the description of the *Settings* tab.
|bcenter| |ControllerSettings_1| |ecenter|

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#FIG 3.2 Produced by xfig version 3.2.5b
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#FIG 3.2 Produced by xfig version 3.2.5b
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#FIG 3.2 Produced by xfig version 3.2.5b
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#FIG 3.2 Produced by xfig version 3.2.5b
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5250 1800 7800 1800 7800 2100 5250 2100 5250 1800
4 1 0 50 -1 18 11 0.0000 4 180 2325 6525 2025 Kite - Load Global Routing\001

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#FIG 3.2 Produced by xfig version 3.2.5b
Landscape
Center
Inches
Letter
100.00
Single
-2
1200 2
6 2700 1800 3300 2100
2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
2700 1800 3300 1800 3300 2100 2700 2100 2700 1800
4 1 0 50 -1 18 11 0.0000 4 135 390 3000 2025 P&R\001
-6
6 3600 1800 4950 2100
2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
3600 1800 4950 1800 4950 2100 3600 2100 3600 1800
4 1 0 50 -1 18 11 0.0000 4 180 1185 4275 2025 Step by Step\001
-6
6 5250 1800 7800 2100
2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
5250 1800 7800 1800 7800 2100 5250 2100 5250 1800
4 1 0 50 -1 18 11 0.0000 4 180 2370 6525 2025 Kite - Save Global Routing\001
-6
2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
1 1 1.00 90.00 180.00
3300 1950 3600 1950
2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
1 1 1.00 90.00 180.00
4950 1950 5250 1950

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