From 6ae3a902eec79463f150bb388fe817bb99a28787 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Tue, 26 Feb 2019 20:00:28 +0100 Subject: [PATCH] Correct H/K parameters for global routing. New cmos45 symbolic. * Change: In CRL/etc/cmos/kite.conf, setup correct H/K parameters for the Katana global router. Value copied from Knik. They give a faster solution. * New: In CRL/etc/cmos45/, new symbolic settings adapted to FreePDK 45nm. Courtesy of N. Shimizu. To be used with NSXLIB. * New In CRL::System, add "coriolis_top" to the set of pathes available to the user. --- crlcore/etc/symbolic/cmos/analog.conf | 2 +- crlcore/etc/symbolic/cmos/kite.conf | 20 +- crlcore/etc/symbolic/cmos/technology.conf | 2 +- crlcore/etc/symbolic/cmos45/alliance.conf | 39 ++++ crlcore/etc/symbolic/cmos45/analog.conf | 6 + crlcore/etc/symbolic/cmos45/devices.conf | 6 + crlcore/etc/symbolic/cmos45/display.conf | 11 + crlcore/etc/symbolic/cmos45/etesian.conf | 5 + crlcore/etc/symbolic/cmos45/hMetis.conf | 5 + crlcore/etc/symbolic/cmos45/kite.conf | 68 ++++++ crlcore/etc/symbolic/cmos45/mauka.conf | 5 + crlcore/etc/symbolic/cmos45/misc.conf | 9 + crlcore/etc/symbolic/cmos45/nimbus.conf | 5 + crlcore/etc/symbolic/cmos45/patterns.conf | 5 + crlcore/etc/symbolic/cmos45/plugins.conf | 27 +++ crlcore/etc/symbolic/cmos45/stratus1.conf | 13 ++ crlcore/etc/symbolic/cmos45/technology.conf | 245 ++++++++++++++++++++ crlcore/src/ccore/AllianceFramework.cpp | 2 + crlcore/src/ccore/Utilities.cpp | 4 + 19 files changed, 473 insertions(+), 6 deletions(-) create mode 100644 crlcore/etc/symbolic/cmos45/alliance.conf create mode 100644 crlcore/etc/symbolic/cmos45/analog.conf create mode 100644 crlcore/etc/symbolic/cmos45/devices.conf create mode 100644 crlcore/etc/symbolic/cmos45/display.conf create mode 100644 crlcore/etc/symbolic/cmos45/etesian.conf create mode 100644 crlcore/etc/symbolic/cmos45/hMetis.conf create mode 100644 crlcore/etc/symbolic/cmos45/kite.conf create mode 100644 crlcore/etc/symbolic/cmos45/mauka.conf create mode 100644 crlcore/etc/symbolic/cmos45/misc.conf create mode 100644 crlcore/etc/symbolic/cmos45/nimbus.conf create mode 100644 crlcore/etc/symbolic/cmos45/patterns.conf create mode 100644 crlcore/etc/symbolic/cmos45/plugins.conf create mode 100644 crlcore/etc/symbolic/cmos45/stratus1.conf create mode 100644 crlcore/etc/symbolic/cmos45/technology.conf diff --git a/crlcore/etc/symbolic/cmos/analog.conf b/crlcore/etc/symbolic/cmos/analog.conf index 33cdd8d7..4d4cf6a2 100644 --- a/crlcore/etc/symbolic/cmos/analog.conf +++ b/crlcore/etc/symbolic/cmos/analog.conf @@ -1,4 +1,4 @@ -# -*- Mode:Python; explicit-buffer-name: "analog.conf" -*- +# -*- Mode:Python; explicit-buffer-name: "analog.conf" -*- import helpers diff --git a/crlcore/etc/symbolic/cmos/kite.conf b/crlcore/etc/symbolic/cmos/kite.conf index e9c70335..b8897670 100644 --- a/crlcore/etc/symbolic/cmos/kite.conf +++ b/crlcore/etc/symbolic/cmos/kite.conf @@ -13,7 +13,6 @@ parametersTable = \ , ("katabatic.saturateRatio" ,TypePercentage,80 ) , ("katabatic.saturateRp" ,TypeInt ,8 ) , ('katabatic.topRoutingLayer' ,TypeString , 'METAL5') - , ('anabatic.routingGauge' ,TypeString , 'sxlib' ) # Kite parameters. , ("kite.hTracksReservedLocal" ,TypeInt ,3 , { 'min':0, 'max':20 } ) , ("kite.vTracksReservedLocal" ,TypeInt ,3 , { 'min':0, 'max':20 } ) @@ -23,17 +22,30 @@ parametersTable = \ , ("kite.localRipupLimit" ,TypeInt ,9 , { 'min':1 } ) , ("kite.globalRipupLimit" ,TypeInt ,5 , { 'min':1 } ) , ("kite.longGlobalRipupLimit" ,TypeInt ,5 , { 'min':1 } ) - # Anabatic parameters are temporarily hosted here. + # Anabatic & Katana parameters are temporarily hosted here. + , ('anabatic.routingGauge' ,TypeString , 'sxlib' ) + , ("anabatic.globalLengthThreshold" ,TypeInt ,1450 ) + , ("anabatic.saturateRatio" ,TypePercentage,80 ) + , ("anabatic.saturateRp" ,TypeInt ,8 ) + , ('anabatic.topRoutingLayer' ,TypeString , 'METAL5') , ("anabatic.edgeLength" ,TypeInt ,24 ) , ("anabatic.edgeWidth" ,TypeInt ,4 ) - , ("anabatic.edgeCostH" ,TypeDouble ,9.0 ) - , ("anabatic.edgeCostK" ,TypeDouble ,-10.0 ) + , ("anabatic.edgeCostH" ,TypeDouble ,19.0 ) + , ("anabatic.edgeCostK" ,TypeDouble ,-60.0 ) , ("anabatic.edgeHScaling" ,TypeDouble ,1.0 ) , ("anabatic.globalIterations" ,TypeInt ,10 , { 'min':1, 'max':100 } ) , ("anabatic.gcell.displayMode" ,TypeEnumerate ,1 , { 'values':( ("Boundary" , 1) , ("Density" , 2) ) } ) + , ("katana.hTracksReservedLocal" ,TypeInt ,3 , { 'min':0, 'max':20 } ) + , ("katana.vTracksReservedLocal" ,TypeInt ,3 , { 'min':0, 'max':20 } ) + , ("katana.eventsLimit" ,TypeInt ,4000002 ) + , ("katana.ripupCost" ,TypeInt ,3 , { 'min':0 } ) + , ("katana.strapRipupLimit" ,TypeInt ,16 , { 'min':1 } ) + , ("katana.localRipupLimit" ,TypeInt ,9 , { 'min':1 } ) + , ("katana.globalRipupLimit" ,TypeInt ,5 , { 'min':1 } ) + , ("katana.longGlobalRipupLimit" ,TypeInt ,5 , { 'min':1 } ) ) diff --git a/crlcore/etc/symbolic/cmos/technology.conf b/crlcore/etc/symbolic/cmos/technology.conf index 032ea1b7..8bdfb8ca 100644 --- a/crlcore/etc/symbolic/cmos/technology.conf +++ b/crlcore/etc/symbolic/cmos/technology.conf @@ -14,7 +14,7 @@ from helpers.Technology import initTechno # - # - -initTechno( { 'name' : 'cmos' +initTechno( { 'name' : 'cmos45' , 'precision' : 2 , 'gridValue' : 0.005 , 'gridUnit' : DbU.UnitPowerMicro diff --git a/crlcore/etc/symbolic/cmos45/alliance.conf b/crlcore/etc/symbolic/cmos45/alliance.conf new file mode 100644 index 00000000..1fa575f1 --- /dev/null +++ b/crlcore/etc/symbolic/cmos45/alliance.conf @@ -0,0 +1,39 @@ +# -*- Mode:Python; explicit-buffer-name: "alliance.conf" -*- + +import os +from helpers.Alliance import AddMode +from helpers.Alliance import Gauge + + +allianceTop = None +if os.environ.has_key('ALLIANCE_TOP'): + allianceTop = os.environ['ALLIANCE_TOP'] + if not os.path.isdir(allianceTop): + allianceTop = None + +if not allianceTop: allianceTop = '/soc/alliance' + +cellsTop = allianceTop+'/cells/' + + +allianceConfig = \ + ( ( 'CATALOG' , 'CATAL') + , ( 'WORKING_LIBRARY' , '.') + , ( 'SYSTEM_LIBRARY' , ( (cellsTop+'/nsxlib' , Environment.Append) + , (cellsTop+'/mpxlib' , Environment.Append)) ) + , ( 'SCALE_X' , 100) + , ( 'IN_LO' , 'vst') + , ( 'IN_PH' , 'ap') + , ( 'OUT_LO' , 'vst') + , ( 'OUT_PH' , 'ap') + , ( 'POWER' , 'vdd') + , ( 'GROUND' , 'vss') + , ( 'CLOCK' , '^ck.*') + , ( 'BLOCKAGE' , '^blockage[Nn]et*') + , ( 'PAD' , '.*_mpx$') + # The following are only read by the Alliance tool wrappers. + , ( 'ALLIANCE_TOP' , allianceTop) + , ( 'MBK_TARGET_LIB' , cellsTop+'/msxlib') + , ( 'RDS_TECHNO_NAME' , allianceTop+'/etc/scn6m_deep_09.rds') + , ( 'GRAAL_TECHNO_NAME' , allianceTop+'/etc/graal.rds') + ) diff --git a/crlcore/etc/symbolic/cmos45/analog.conf b/crlcore/etc/symbolic/cmos45/analog.conf new file mode 100644 index 00000000..e7ff617e --- /dev/null +++ b/crlcore/etc/symbolic/cmos45/analog.conf @@ -0,0 +1,6 @@ +# -*- Mode:Python; explicit-buffer-name: "analog.conf" -*- + +import helpers + + +execfile( helpers.ndaConfDir+'/common/analog.conf' ) diff --git a/crlcore/etc/symbolic/cmos45/devices.conf b/crlcore/etc/symbolic/cmos45/devices.conf new file mode 100644 index 00000000..96342ade --- /dev/null +++ b/crlcore/etc/symbolic/cmos45/devices.conf @@ -0,0 +1,6 @@ +# -*- Mode:Python; explicit-buffer-name: "devices.conf" -*- + +import helpers + + +execfile( helpers.ndaConfDir+'/common/devices.conf' ) diff --git a/crlcore/etc/symbolic/cmos45/display.conf b/crlcore/etc/symbolic/cmos45/display.conf new file mode 100644 index 00000000..86083d7d --- /dev/null +++ b/crlcore/etc/symbolic/cmos45/display.conf @@ -0,0 +1,11 @@ +# -*- Mode:Python; explicit-buffer-name: "display.conf" -*- + +import helpers + +# Provides standard settings for: +# - +# - + +scale = 0.5 + +execfile( helpers.sysConfDir+'/common/display.conf' ) diff --git a/crlcore/etc/symbolic/cmos45/etesian.conf b/crlcore/etc/symbolic/cmos45/etesian.conf new file mode 100644 index 00000000..0c16f79f --- /dev/null +++ b/crlcore/etc/symbolic/cmos45/etesian.conf @@ -0,0 +1,5 @@ +# -*- Mode:Python; explicit-buffer-name: "etesian.conf" -*- + +import helpers + +execfile( helpers.sysConfDir+'/common/etesian.conf' ) diff --git a/crlcore/etc/symbolic/cmos45/hMetis.conf b/crlcore/etc/symbolic/cmos45/hMetis.conf new file mode 100644 index 00000000..720cdc23 --- /dev/null +++ b/crlcore/etc/symbolic/cmos45/hMetis.conf @@ -0,0 +1,5 @@ +# -*- Mode:Python; explicit-buffer-name: "hMetis.conf" -*- + +import helpers + +execfile( helpers.sysConfDir+'/common/hMetis.conf' ) diff --git a/crlcore/etc/symbolic/cmos45/kite.conf b/crlcore/etc/symbolic/cmos45/kite.conf new file mode 100644 index 00000000..5cc4766e --- /dev/null +++ b/crlcore/etc/symbolic/cmos45/kite.conf @@ -0,0 +1,68 @@ +# -*- Mode:Python; explicit-buffer-name: "kite.conf" -*- + +import helpers +from helpers import l, u, n + +# Contains the layout (shared by all technologies). +execfile( helpers.sysConfDir+'/common/kite.conf' ) + + +parametersTable = \ + ( ('lefImport.minTerminalWidth' ,TypeDouble ,0.0 ) + , ("katabatic.globalLengthThreshold",TypeInt ,1450 ) # Katabatic parameters. + , ("katabatic.saturateRatio" ,TypePercentage,80 ) + , ("katabatic.saturateRp" ,TypeInt ,8 ) + , ('katabatic.topRoutingLayer' ,TypeString , 'METAL6') + # Kite parameters. + , ("kite.hTracksReservedLocal" ,TypeInt ,4 , { 'min':0, 'max':18 } ) + , ("kite.vTracksReservedLocal" ,TypeInt ,3 , { 'min':0, 'max':18 } ) + , ("kite.eventsLimit" ,TypeInt ,4000002 ) + , ("kite.ripupCost" ,TypeInt ,3 , { 'min':0 } ) + , ("kite.strapRipupLimit" ,TypeInt ,16 , { 'min':1 } ) + , ("kite.localRipupLimit" ,TypeInt ,9 , { 'min':1 } ) + , ("kite.globalRipupLimit" ,TypeInt ,5 , { 'min':1 } ) + , ("kite.longGlobalRipupLimit" ,TypeInt ,5 , { 'min':1 } ) + # Anabatic parameters are temporarily hosted here. + , ("anabatic.routingGauge" ,TypeString ,'msxlib' ) + , ("anabatic.edgeLength" ,TypeInt ,48 ) + , ("anabatic.edgeWidth" ,TypeInt ,8 ) + , ("anabatic.edgeCostH" ,TypeDouble ,19.0 ) + , ("anabatic.edgeCostK" ,TypeDouble ,-60.0 ) + , ("anabatic.edgeHInc" ,TypeDouble ,1.0 ) + , ("anabatic.edgeHScaling" ,TypeDouble ,1.0 ) + , ("anabatic.globalIterations" ,TypeInt ,20 , { 'min':1, 'max':100 } ) + , ("anabatic.gcell.displayMode" ,TypeEnumerate ,1 + , { 'values':( ("Boundary" , 1) + , ("Density" , 2) ) } + ) + ) + + +# Format of routingGaugesTable (dictionary): +# A list of entry of the form: +# ( METAL_NAME, (Direction, Type, depth, density, offset, pitch, wire_width, via_width, obs_dw) ) + +routingGaugesTable = {} + +routingGaugesTable['msxlib'] = \ + ( ( 'METAL1' , ( Gauge.Vertical , Gauge.PinOnly, 0, 0.0, l(0), l(10), l(3), l(2), l(7) ) ) + , ( 'METAL2' , ( Gauge.Horizontal, Gauge.Default, 1, 0.0, l(0), l(10), l(3), l(2), l(8) ) ) + , ( 'METAL3' , ( Gauge.Vertical , Gauge.Default, 2, 0.0, l(0), l(10), l(3), l(2), l(8) ) ) + , ( 'METAL4' , ( Gauge.Horizontal, Gauge.Default, 3, 0.0, l(0), l(20), l(6), l(4), l(8) ) ) + , ( 'METAL5' , ( Gauge.Vertical , Gauge.Default, 4, 0.0, l(0), l(20), l(6), l(4), l(8) ) ) + , ( 'METAL6' , ( Gauge.Horizontal, Gauge.Default, 5, 0.0, l(0), l(20), l(6), l(4), l(8) ) ) + ) + +routingGaugesTable['msxlib-2M'] = \ + ( ( 'METAL1', ( Gauge.Horizontal, Gauge.Default, 0, 0.0, l(0), l(10), l(3), l(3), l(7) ) ) + , ( 'METAL2', ( Gauge.Vertical , Gauge.Default, 1, 0.0, l(0), l(10), l(3), l(3), l(8) ) ) + ) + + +# Format of cellGaugesTable (dictionary): +# A list of entry of the form: +# ( METAL_PIN, xy_common_pitch, slice_height, slice_step ) + +cellGaugesTable = {} +cellGaugesTable['msxlib'] = ('metal2', l(10), l(100), l(10)) + diff --git a/crlcore/etc/symbolic/cmos45/mauka.conf b/crlcore/etc/symbolic/cmos45/mauka.conf new file mode 100644 index 00000000..99e1379d --- /dev/null +++ b/crlcore/etc/symbolic/cmos45/mauka.conf @@ -0,0 +1,5 @@ +# -*- Mode:Python; explicit-buffer-name: "mauka.conf" -*- + +import helpers + +execfile( helpers.sysConfDir+'/common/mauka.conf' ) diff --git a/crlcore/etc/symbolic/cmos45/misc.conf b/crlcore/etc/symbolic/cmos45/misc.conf new file mode 100644 index 00000000..010234c0 --- /dev/null +++ b/crlcore/etc/symbolic/cmos45/misc.conf @@ -0,0 +1,9 @@ +# -*- Mode:Python; explicit-buffer-name: "misc.conf" -*- + +import helpers + +# Provides standard settings for: +# # - +# # - +# +execfile( helpers.sysConfDir+'/common/misc.conf' ) diff --git a/crlcore/etc/symbolic/cmos45/nimbus.conf b/crlcore/etc/symbolic/cmos45/nimbus.conf new file mode 100644 index 00000000..e47b7a17 --- /dev/null +++ b/crlcore/etc/symbolic/cmos45/nimbus.conf @@ -0,0 +1,5 @@ +# -*- Mode:Python; explicit-buffer-name: "nimbus.conf" -*- + +import helpers + +execfile( helpers.sysConfDir+'/common/nimbus.conf' ) diff --git a/crlcore/etc/symbolic/cmos45/patterns.conf b/crlcore/etc/symbolic/cmos45/patterns.conf new file mode 100644 index 00000000..7069c3e3 --- /dev/null +++ b/crlcore/etc/symbolic/cmos45/patterns.conf @@ -0,0 +1,5 @@ +# -*- Mode:Python; explicit-buffer-name: "patterns.conf" -*- + +import helpers + +execfile( helpers.sysConfDir+'/common/patterns.conf' ) diff --git a/crlcore/etc/symbolic/cmos45/plugins.conf b/crlcore/etc/symbolic/cmos45/plugins.conf new file mode 100644 index 00000000..e97203d0 --- /dev/null +++ b/crlcore/etc/symbolic/cmos45/plugins.conf @@ -0,0 +1,27 @@ +# -*- Mode:Python; explicit-buffer-name: "plugins.conf" -*- + +import helpers + +# Contains the layout (shared by all technologies). +#execfile( helpers.sysConfDir+'/common/plugins.conf' ) + + +# WARNING: Those values have not been adjusted yet for this technologies. +# Must be done. +# +# Parameters for chip plugin. +parametersTable = \ + ( ("chip.block.rails.count" , TypeInt , 5 ) + , ("chip.block.rails.hWidth" , TypeInt , 24 ) + , ("chip.block.rails.vWidth" , TypeInt , 24 ) + , ("chip.block.rails.hSpacing" , TypeInt , 12 ) + , ("chip.block.rails.vSpacing" , TypeInt , 12 ) + , ('chip.pad.pck' , TypeString, 'pck_mpx') + , ('chip.pad.pvddick' , TypeString, 'pvddick_mpx') + , ('chip.pad.pvssick' , TypeString, 'pvssick_mpx') + , ('chip.pad.pvddeck' , TypeString, 'pvddeck_mpx') + , ('chip.pad.pvsseck' , TypeString, 'pvsseck_mpx') + , ('clockTree.minimumSide' , TypeInt , 1000) + , ('clockTree.buffer' , TypeString, 'buf_x2') + , ('clockTree.placerEngine' , TypeString, 'Etesian') + ) diff --git a/crlcore/etc/symbolic/cmos45/stratus1.conf b/crlcore/etc/symbolic/cmos45/stratus1.conf new file mode 100644 index 00000000..e8fb52ba --- /dev/null +++ b/crlcore/etc/symbolic/cmos45/stratus1.conf @@ -0,0 +1,13 @@ +# -*- Mode:Python; explicit-buffer-name: "stratus1.conf" -*- + +import helpers + + +# Status1 parameters. +parametersTable = \ + ( ("stratus1.format" , TypeString, "vst") + , ("stratus1.simulator" , TypeString, "asimut") + ,) + + +execfile( helpers.sysConfDir+'/common/stratus1.conf' ) diff --git a/crlcore/etc/symbolic/cmos45/technology.conf b/crlcore/etc/symbolic/cmos45/technology.conf new file mode 100644 index 00000000..c715c606 --- /dev/null +++ b/crlcore/etc/symbolic/cmos45/technology.conf @@ -0,0 +1,245 @@ +# -*- Mode:Python; explicit-buffer-name: "technology.conf" -*- + +from Hurricane import DbU +from helpers import sysConfDir +from helpers import l, u, n +from helpers.Technology import initTechno + +# The informations here are extracted from the Alliance ".rds" file, +# and must be consistent with it. +# +# Provides standard settings for: +# - +# - +# - +# - + + +# MOSIS SCN6M_DEEP is a portable technology where lengths are expresseds +# in symbolic unit (lambda). We only know that the lambda is equal to half +# the value of the technology, that is 180nm gives 90nm. We have no information +# about the foundry grid. +# +# We set the foundry grid to .0025um and set the gridsPerLambda to 10. + +initTechno( { 'name' : 'cmos45' + , 'precision' : 2 + , 'gridValue' : 0.0025 + , 'gridUnit' : DbU.UnitPowerMicro + , 'gridsPerLambda' : 10 + , 'symbolicGridStep': 1.0 + , 'polygonStep' : 10.0 + } ) + +execfile( sysConfDir+'/common/technology.conf' ) + + +# Format of : +# Each entry is a pair of (string, value). +# * string: a synthetic way to designate the real or symbolic layer on +# which it applies, an optional sub layer (BasicLayer) in case +# where there is more than one, and the dimension name. +# * value : the rule (dimension) value. +# Values/dimensions must be given using one of the following conversion +# function: +# * l(value) : value expressed in lambda (symbolic). +# * u(value) : value is expressed in microns. +# * n(value) : value is expressed in nanometers. + +def scaleUp ( extensionsTable ): + scaled = [] + for entry in extensionsTable: + scaled.append( ( entry[0], 2*entry[1] ) ) + return scaled + +#layersExtensionsTable = \ +# [ ('METAL1.minimalSpacing' , l( 6.0)) +# , ('METAL2.minimalSpacing' , l( 6.0)) +# , ('METAL3.minimalSpacing' , l( 6.0)) +# , ('METAL4.minimalSpacing' , l( 6.0)) +# , ('METAL5.minimalSpacing' , l( 6.0)) +# , ('METAL6.minimalSpacing' , l( 6.0)) +# ] + \ +# scaleUp( symbolicLayersExtensionsTable ) + +layersExtensionsTable = \ + ( ('METAL1.minimalSpacing' , l( 6.0)) + , ('METAL2.minimalSpacing' , l( 6.0)) + , ('METAL3.minimalSpacing' , l( 6.0)) + , ('METAL4.minimalSpacing' , l( 6.0)) + , ('METAL5.minimalSpacing' , l( 6.0)) + , ('METAL6.minimalSpacing' , l( 6.0)) + + , ('NWELL.nWell.extention.cap' , l( 4.0)) + , ('PWELL.pWell.extention.cap' , l( 4.0)) + + , ('NTIE.minimum.width' , l( 3.0)) + , ('NTIE.nWell.extention.cap' , l( 3.0)) + , ('NTIE.nWell.extention.width' , l( 2.0)) + , ('NTIE.nImplant.extention.cap' , l( 2.5)) + , ('NTIE.nImplant.extention.width' , l( 1.5)) + , ('NTIE.active.extention.cap' , l( 0.5)) + , ('NTIE.active.extention.width' , l(-0.5)) + + , ('PTIE.minimum.width' , l( 3.0)) + , ('PTIE.pWell.extention.cap' , l( 3.0)) + , ('PTIE.pWell.extention.width' , l( 2.0)) + , ('PTIE.pImplant.extention.cap' , l( 2.5)) + , ('PTIE.pImplant.extention.width' , l( 1.5)) + , ('PTIE.active.extention.cap' , l( 0.5)) + , ('PTIE.active.extention.width' , l(-0.5)) + + , ('NDIF.minimum.width' , l( 3.0)) + , ('NDIF.nImplant.extention.cap' , l( 4.0)) + , ('NDIF.nImplant.extention.width' , l( 2.0)) + , ('NDIF.active.extention.cap' , l( 2.0)) + , ('NDIF.active.extention.width' , l( 0.0)) + + , ('PDIF.minimum.width' , l( 3.0)) + , ('PDIF.pImplant.extention.cap' , l( 4.0)) + , ('PDIF.pImplant.extention.width' , l( 2.0)) + , ('PDIF.active.extention.cap' , l( 2.0)) + , ('PDIF.active.extention.width' , l( 0.0)) + + , ('GATE.minimum.width' , l( 2.0)) + , ('GATE.poly.extention.cap' , l( 2.5)) + + , ('NTRANS.minimum.width' , l( 2.0)) + , ('NTRANS.nImplant.extention.cap' , l( 2.0)) + , ('NTRANS.nImplant.extention.width' , l( 7.0)) + , ('NTRANS.active.extention.cap' , l( 0.0)) + , ('NTRANS.active.extention.width' , l( 3.0)) + , ('NTRANS.poly.extention.cap' , l( 3.0)) + , ('NTRANS.poly.extention.width' , l( 0.0)) + + , ('PTRANS.minimum.width' , l( 2.0)) + , ('PTRANS.nWell.extention.cap' , l( 2.5)) + , ('PTRANS.nWell.extention.width' , l( 7.5)) + , ('PTRANS.pImplant.extention.cap' , l( 2.0)) + , ('PTRANS.pImplant.extention.width' , l( 7.0)) + , ('PTRANS.active.extention.cap' , l( 0.0)) + , ('PTRANS.active.extention.width' , l( 3.0)) + , ('PTRANS.poly.extention.cap' , l( 3.0)) + , ('PTRANS.poly.extention.width' , l( 0.0)) + + , ('POLY.minimum.width' , l( 2.0)) + , ('POLY.poly.extention.cap' , l( 1.0)) + , ('POLY2.minimum.width' , l( 2.0)) + , ('POLY2.poly2.extention.cap' , l( 2.0)) + + # Routing Layers (symbolic). + , ('METAL1.minimum.width' , l( 2.0)) + , ('METAL1.metal1.extention.cap' , l( 2.0)) + , ('METAL1.metal1.extention.width' , l( 1.0)) + , ('METAL2.minimum.width' , l( 4.0)) + , ('METAL2.metal2.extention.cap' , l( 2.0)) + , ('METAL3.minimum.width' , l( 4.0)) + , ('METAL3.metal3.extention.cap' , l( 2.0)) + , ('METAL4.minimum.width' , l( 4.0)) + , ('METAL4.metal4.extention.cap' , l( 2.0)) + , ('METAL5.minimum.width' , l( 4.0)) + , ('METAL5.metal5.extention.cap' , l( 2.0)) + , ('METAL6.minimum.width' , l(10.0)) + , ('METAL6.metal6.extention.cap' , l( 5.0)) + #, ('METAL7.minimum.width' , l( 2.0)) + #, ('METAL7.metal7.extention.cap' , l( 2.5)) + #, ('METAL8.minimum.width' , l( 2.0)) + #, ('METAL8.metal8.extention.cap' , l( 2.5)) + + # Blockages (symbolic). + , ('BLOCKAGE1.minimum.width' , l( 4.0)) + , ('BLOCKAGE1.blockage1.extention.cap' , l( 2.0)) + , ('BLOCKAGE1.blockage1.extention.width', l( 0.5)) + , ('BLOCKAGE2.minimum.width' , l( 4.0)) + , ('BLOCKAGE2.blockage2.extention.cap' , l( 2.0)) + , ('BLOCKAGE3.minimum.width' , l( 4.0)) + , ('BLOCKAGE3.blockage3.extention.cap' , l( 2.0)) + , ('BLOCKAGE4.minimum.width' , l( 4.0)) + , ('BLOCKAGE4.blockage4.extention.cap' , l( 2.0)) + , ('BLOCKAGE5.minimum.width' , l( 4.0)) + , ('BLOCKAGE5.blockage5.extention.cap' , l( 2.0)) + , ('BLOCKAGE6.minimum.width' , l( 8.0)) + , ('BLOCKAGE6.blockage6.extention.cap' , l( 2.5)) + #, ('BLOCKAGE7.minimum.width' , l( 2.0)) + #, ('BLOCKAGE7.blockage6.extention.cap' , l( 4.0)) + #, ('BLOCKAGE8.minimum.width' , l( 2.0)) + #, ('BLOCKAGE8.blockage6.extention.cap' , l( 4.0)) + + # Contacts (i.e. Active <--> Metal) (symbolic). + , ('CONT_BODY_N.minimum.side' , l( 2.0)) + , ('CONT_BODY_N.nWell.enclosure' , l( 4.0)) + , ('CONT_BODY_N.nImplant.enclosure' , l( 3.5)) + , ('CONT_BODY_N.active.enclosure' , l( 1.5)) + , ('CONT_BODY_N.metal1.enclosure' , l( 1.0)) + + , ('CONT_BODY_P.minimum.side' , l( 2.0)) + , ('CONT_BODY_P.pWell.enclosure' , l( 4.0)) + , ('CONT_BODY_P.pImplant.enclosure' , l( 3.5)) + , ('CONT_BODY_P.active.enclosure' , l( 1.5)) + , ('CONT_BODY_P.metal1.enclosure' , l( 1.0)) + + , ('CONT_DIF_N.minimum.side' , l( 2.0)) + , ('CONT_DIF_N.nImplant.enclosure' , l( 4.0)) + , ('CONT_DIF_N.active.enclosure' , l( 2.0)) + , ('CONT_DIF_N.metal1.enclosure' , l( 1.0)) + + , ('CONT_DIF_P.minimum.side' , l( 2.0)) + , ('CONT_DIF_P.pImplant.enclosure' , l( 4.0)) + , ('CONT_DIF_P.active.enclosure' , l( 2.0)) + , ('CONT_DIF_P.metal1.enclosure' , l( 1.0)) + + , ('CONT_POLY.minimum.width' , l( 2.0)) + , ('CONT_POLY.poly.enclosure' , l( 2.0)) + , ('CONT_POLY.metal1.enclosure' , l( 1.0)) + + # VIAs (i.e. Metal <--> Metal) (symbolic). + , ('VIA12.minimum.side' , l( 2.0)) + , ('VIA12.metal1.enclosure' , l( 1.0)) + , ('VIA12.metal2.enclosure' , l( 1.0)) + , ('VIA23.minimum.side' , l( 2.0)) + , ('VIA23.metal2.enclosure' , l( 1.0)) + , ('VIA23.metal3.enclosure' , l( 1.0)) + , ('VIA34.minimum.side' , l( 2.0)) + , ('VIA34.metal3.enclosure' , l( 1.0)) + , ('VIA34.metal4.enclosure' , l( 1.0)) + , ('VIA45.minimum.side' , l( 2.0)) + , ('VIA45.metal4.enclosure' , l( 1.0)) + , ('VIA45.metal5.enclosure' , l( 1.0)) + , ('VIA56.minimum.side' , l( 5.0)) + , ('VIA56.metal5.enclosure' , l( 1.0)) + , ('VIA56.metal6.enclosure' , l( 1.5)) + #, ('VIA67.minimum.side' , l( 2.0)) + #, ('VIA67.metal6.enclosure' , l( 3.0)) + #, ('VIA67.metal7.enclosure' , l( 3.0)) + #, ('VIA78.minimum.side' , l( 2.0)) + #, ('VIA78.metal7.enclosure' , l( 3.0)) + #, ('VIA78.metal8.enclosure' , l( 3.0)) + ) + + +for entry in layersExtensionsTable: + print entry + +# Format of an entry in the table: +# (Symbolic_Name, CIF_Name, GDSII_Number) +gdsLayersTable = \ + ( ("pWell" , "CWN" , 41, 0) + , ("nWell" , "CWP" , 42, 0) + , ("active" , "CAA" , 43, 0) + , ("pImplant", "CSP" , 44, 0) + , ("nImplant", "CSN" , 45, 0) + , ("poly" , "CPG" , 46, 0) + , ("poly2" , "CM1" , 49, 0) # poly2 is in fact metal1. + , ("cut0" , "CCC" , 25, 0) + , ("metal1" , "CM1" , 49, 0) + , ("cut1" , "CV1" , 50, 0) + , ("metal2" , "CM2" , 51, 0) + , ("cut2" , "CV2" , 61, 0) + , ("metal3" , "CM3" , 62, 0) + , ("cut3" , "CV3" , 30, 0) + , ("metal4" , "CM4" , 31, 0) + , ("cut4" , "CV4" , 32, 0) + , ("metal5" , "CM5" , 33, 0) + , ("cut5" , "CV5" , 36, 0) + , ("metal6" , "CM6" , 37, 0) + ) diff --git a/crlcore/src/ccore/AllianceFramework.cpp b/crlcore/src/ccore/AllianceFramework.cpp index 3e2bf68a..d7d66dd1 100644 --- a/crlcore/src/ccore/AllianceFramework.cpp +++ b/crlcore/src/ccore/AllianceFramework.cpp @@ -29,6 +29,8 @@ #include "crlcore/RoutingLayerGauge.h" #include "crlcore/AllianceFramework.h" +#include "hurricane/SharedName.h" + namespace CRL { diff --git a/crlcore/src/ccore/Utilities.cpp b/crlcore/src/ccore/Utilities.cpp index 9acaf3b6..31dfff6b 100644 --- a/crlcore/src/ccore/Utilities.cpp +++ b/crlcore/src/ccore/Utilities.cpp @@ -281,6 +281,10 @@ namespace CRL { ); } + if ( arguments.count("coriolis_top") ) { + _pathes.insert ( make_pair("coriolis_top", arguments["coriolis_top"].as()) ); + } + Utilities::Path sysConfDir ( SYS_CONF_DIR ); if ( not sysConfDir.absolute() ) { if ( arguments.count("coriolis_top") ) {